Phase-Locked Loop Engineering Handbook for Integrated Circuits

Stanley Goldman

A R T E C H

H O U S E BOSTON|LONDON a r t e c h h o u s e . c o m

Contents

Preface xiii

Acknowledgments xxi

CHAPTER 1

Cetting Started with PLLs 1

1.1 Definition and Operation 1 1.2 Phase-Lock Loop Literature 5

1.2.1 Books 5 1.2.2 Articles 6 1.2.3 Background Books 6 1.2.4 WebSites 7

1.3 Loop Classifications 7 1.4 Example Applications 7

1.4.1 History 8 1.4.2 Doppler Radar 9 1.4.3 Satellite Communications 10 1.4.4 Cellular Phones 10 1.4.5 Telecommunications Systems 11 Questions 12 References 13

CHAPTER 2

System Analysis 15

2.1 VCO Mathematical Description 15 2.2 Phase Detector Mathematical Relationship 16 2.3 PLL Transfer Function and Control-Systems Theory 19 2.4 Error Tracking 23 2.5 Type 2, Second-Order Active Loop-to-Servo Terminology 24 2.6 Loop Stability: Bode Plot Analysis 26 2.7 Loop Stability: Root-Locus Analysis 28 2.8 Charge Pump Synthesis Example of Loop-Component Values 30 2.9 Summary 32

Questions 33 References 33

VII

VIII Contents

CHAPTER 3

System Requirements 35

3.1 Noise Basics 35 3.1.1 Sources of Noise 36 3.1.2 Noise Models 41 3.1.3 Equivalent Input Noise 44 3.1.4 Noise Figure 48 3.1.5 Bipolar Versus CMOS Noise Comparison 50

3.2 Phase-Noise and Oscillator Theory 53 3.2.1 FM Theory 54 3.2.2 Relationship of Phase Noise to FM 55 3.2.3 Different Measures of Phase Noise 59 3.2.4 Oscillator Design and Phase-Noise Modeling 63 3.2.5 Negative-Resistance Oscillator Model 68 3.2.6 Power Slopes of Oscillators 68 3.2.7 Resonator Effects on Oscillator Phase Noise 72 3.2.8 Allan Variance and Residual FM Calculations 74 3.2.9 Phase Noise in PLLs 76

3.3 Jitter in PLLs 82 3.3.1 Causes of Jitter 83 3.3.2 Phase-Noise Analysis on Jitter 84 3.3.3 Analysis of Spurious Signals on Jitter 91 3.3.4 Spurious-Noise-Reduction Techniques 95

3.4 Time-Domain Solution 96 3.4.1 Importance of Solving for the Time-Domain Response 96 3.4.2 Time-Domain Solution Using La Place Transforms 97 3.4.3 Relationship of Error Function to Closed Loop 103 3.4.4 Output Responses to Unnormalized Input Steps 107 3.4.5 Ramp Phase Solution 109 3.4.6 Parabolic Phase Solution 110

3.5 Acquisition of Lock 112 3.5.1 Derivation of the Second-Order, Nonlinear, Ordinary

Differential Equation 114 3.5.2 Simplifying and Normalizing the Nonlinear Equation 117 3.5.3 Difference Equation for Making the Phase-Plane Trajectory

Plot 118 3.5.4 Unnormalized Solution 119 3.5.5 Measured Step Responses Inside and Outside the Separatrix 121

3.6 Spurious Signals 123 3.6.1 Intermodulation Products 124 3.6.2 Minimizing the Generation of Reference Sidebands 130 3.6.3 Noise-Reduction Techniques 145

3.7 Summary 154 Questions 155 References 159

Appendix 3A: Single-Ended Explanation of Offset Currents 161

Contents IX

CHAPTER 4

Components, Part 1—Dividers and Oscillators 163

4.1 Dividers 163 4.1.1 Programmable Divider 164 4.1.2 Pulse Swallowing 168 4.1.3 Fractional Divide-by-N 174

4.2 Voltage-Controlled Oscillators 181 4.2.1 Operation of a Ring Oscillator 183 4.2.2 Differential Ring Oscillators 190 4.2.3 Multivibrators 197 4.2.4 LC Resonant Oscillators 204 4.2.5 LC Multivibrators 212

4.3 Reference Oscillators 216 4.3.1 Oscillator Circuits, Stability, and Startup Time 221 4.3.2 Equations for Oscillation 223 4.3.3 Stability of Oscillation 224 4.3.4 Startup Time 227

4.4 Summary 231 Questions 232 References 233

CHAPTER 5

Components, Part 2—Detectors and Other Circuits 235

5.1 Phase Detectors 235 5.1.1 Linear Model 236 5.1.2 Phase Detector Figure of Merit 236 5.1.3 Balanced Mixer 238 5.1.4 Gilbert Multiplier 242 5.1.5 Exclusive-OR Phase Detector 245 5.1.6 RS Phase Detector (Two States) 249 5.1.7 Phase/Frequency Detector 252 5.1.8 Conclusion 268

5.2 Lock Detection 268 5.2.1 Quadrature Lock Detection 269 5.2.2 Tune-Voltage Window Comparator 269 5.2.3 Time-Window Edge Comparison 270 5.2.4 Cycle-Slip Detector 271 5.2.5 Cycle-Slip Detector Versus Time-Window Comparator 273

5.3 Acquisition Aids 275 5.3.1 Open-Loop Sweep 276 5.3.2 Closed-Loop Sweep 277 5.3.3 Discriminator Aided 277

5.4 Charge Pumps 280 5.5 Design Considerations for Opamps in a PLL 286

5.5.1 Architecture Selection, Comparison to Basic Two-Stage Opamp 288

Contents

5.5.2 Basic Opamp 288 5.5.3 Folded Cascode 292

5.6 Differences Between Charge Pump and Operational Ampiifier Compensation 297 5.6.1 Error Tracking of Charge Pump and Active Compensation 297 5.6.2 Phase-Noise Suppression 300 5.6.3 Phase-Error Tracking for Changing Input Frequency 301

5.7 Summary 302 Questions 304 References 306

CHAPTER 6

Loop-Compensation Synthesis Revisited 307

6.1 Ranking Requirements for PLLs 308 6.2 Loop-Component Synthesis 313 6.3 Active Compensation and Maximum Capacitor Value 319 6.4 Sampling-Delay Synthesis 321

6.4.1 Magnitude Response and Gain Constant of the Open-Loop-Gain Function 324

6.4.2 Solving for PLL Component Values 325 6.4.3 PLL Design with Sampling-Delay Examples 326

6.5 Fast Switching Time 330 6.6 Minimum Bandwidth of a PLL 332

6.6.1 VCO Phase-Noise Limit 333 6.6.2 Component Limits of Standard APLL 335

6.7 Maximum-Divide-Ratio Example for Loop-Component Synthesis 337 6.8 Optimum PLL Design for Low-Phase-Noise Performance 341

6.8.1 PLL Phase-Noise Equations 341 6.8.2 Damping-Factor Effect 343 6.8.3 PLL Bandwidth Effect 344 6.8.4 Equations to Compute Optimum PLL Bandwidth 346

6.9 Summary 349 Questions 350 References 352

CHAPTER 7

Test and Measurement 353

7.1 Hold-In Range, Lock Range, and Spurious Signals 354 7.2 Switching Time 356 7.3 Closed-Loop Bandwidth 358 7.4 Measurement of Phase Noise 359

7.4.1 Direct-Spectrum Measurements 360 7.4.2 Carrier-Suppression Measurements 364 7.4.3 Mixer as a Phase Detector in a Measurement System 364 7.4.4 Carrier-Suppression Measurement Model 367 7.4.5 Generating a Calibration Signal 370

Contents XI

7.4.6 Phase-Noise Measurement Equipment 371 7.4.7 Phase-Noise Measurements with the HP3048 372 7.4.8 Variations of the Carrier-Suppression Technique 373

7.5 Testing for Jitter 377 7.5.1 Oscilloscope Jitter Measurements 378 7.5.2 TIA and Spectrum Analyzer Jitter Measurements 380 7.5.3 Minimum Noise-Floor Measurements of TIA, Oscilloscope,

and Digital Time Scope 382 7.5.4 Isolation Measurements Between PLLs in Silicon 384 7.5.5 Time-Jitter Test Setups 386

7.6 Noise Immunity to Injected Signals 388 7.6.1 Injected Signals into the Reference Input 388 7.6.2 Injected Signals on Supply 389

7.7 Power-On Switching Time 390 7.8 Oscillator Open-Loop Test 391 7.9 Test Equipment 393 7.10 Troubleshooting PLLs 397

7.10.1 Integrated Circuit 398 7.10.2 Functional Check 398 7.10.3 Requirement Compliance Checks 399 7.10.4 Simulation 400 Questions 401 References 403

CHAPTER 8

Simulation 405

8.1 Transistor Level 405 8.2 Behavioral Modeling of PLL with PSPICE 412

8.2.1 Example Behavioral Model of the 270-MHz PLL 414 8.2.2 Model for Error Tracking 418 8.2.3 Identifying Numerical Errors 419

8.3 Difference-Equation Modeling of PLLs 421 8.3.1 Review of Difference-Equation Derivation 422 8.3.2 Extending the Difference Equations for Computer Simulation 424 8.3.3 Example PLL 425 8.3.4 Unique Nonlinear Conditions Simulated by the Difference

Equation 431 Questions 443 References 444

CHAPTER 9

Applications and Extensions 445

9.1 Design Trade-Offs in Frequency Generation with PLLs 445 9.1.1 Classification 446 9.1.2 Direct Synthesis 447 9.1.3 Indirect Synthesis 450

Contents

9.1.4 Direct-Indirect Hybrids 453 9.1.5 Application of Topologies 458 9.1.6 Design Trade-Offs 460 9.1.7 Architecture Design Example 463 9.1.8 Monolithic Synthesizer Example 465

9.2 Clock Recovery 475 9.2.1 Properties of NRZ and RZ Data 477 9.2.2 Edge Detection 479 9.2.3 Clock-Recovery Architectures 481 9.2.4 Phase Detectors for Clock Recovery 486 9.2.5 Clock-Recovery Tests 500

9.3 Effect of Phase Noise on A/D Converters 506 9.3.1 Conversion of Phase Noise to Jitter 507 9.3.2 Relationship of Time Jitter to Dynamic Range 510 9.3.3 Phase Noise Versus Effective Bits 512 9.3.4 Effective Bits at High Frequencies 513 9.3.5 Effect of FM Sideband on Effective Bits 515

9.4 All-Digital PLLs 516 9.4.1 Operation of a Simple ADPLL 516 9.4.2 Sampling and Stability 518 9.4.3 ADPLL by Pulse Addition and Removal 522

9.5 Summary 526 Questions 527 References 527

APPENDIX A

Letter Symbols 529

APPENDIX B

Glossary 533

About the Author 541

Index 543