PETRA Platform for SOI photonic Integrated Circuitssoiconsortium.eu › ... › uploads › 2018 ›...

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PETRA Platform for SOI photonic Integrated Circuits Tsuyoshi Horikawa, and Tohru Mogami** 1 Photonics Electronics Technology Research Association (PETRA) ** Mogami is currently with the National Institute of Advanced Industrial Science and Technology (AIST) October 26th, 2018 Tokyo Japan SOI Design Workshop

Transcript of PETRA Platform for SOI photonic Integrated Circuitssoiconsortium.eu › ... › uploads › 2018 ›...

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PETRA Platform for SOI photonic Integrated Circuits

Tsuyoshi Horikawa, and Tohru Mogami**

1

Photonics Electronics Technology Research Association (PETRA)** Mogami is currently with the National Institute of Advanced Industrial Science and Technology (AIST)

October 26th, 2018 Tokyo Japan SOI Design Workshop

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Acknowledgements

This paper is based on results obtained from a project

commissioned by the New Energy and Industrial

Technology Development Organization (NEDO).

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Outline

➢ Si-PIC, PETRA & New Venture

➢ PETRA Platform

➢ Process Control Monitoring

➢ AIO Core Co. Ltd.

➢ Summary

3October 26th, 2018 Tokyo Japan SOI Design Workshop

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Data Traffic in the World

Cloud Computing

Data Center

Sensor

Tablet

2016 2018 20202014

20,000

10,000

0

Zett

abyt

es /

Yea

r

CAGR = 27%

CAGR = 24%

[Forecast by Cisco]

Big Data Analysis

High-Growth Data Traffic in Internet & Data Center;

➢ Drive bandwidth demand

➢ Need high-speed, low-cost, small-size interconnect

Si-PICSilicon-based Photonic Integrated Circuit

CPU with 1.2 Tbps Si-PIC

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Why Si Waveguides & SOI are

Glass Fiber

Dn ~0.1 %

Silicon WaveguideDn ~200 %

1 mm

III-V SemiconductorDn ~10 %

Index Contrast Waveguide Cross-section

Strong light confinement in Si enables Chip-scale optical integration

16-ch. Optical Interposer[Urino, JLT 2015]

Laser Diode Array

Modulator Array

DetectorArray

Waveguide Array

5 mm

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➢ Establishment: 2009

➢ Current Project: Integrated Photonics-Electronics Convergence System Technology [ IPECST ]

➢ Objective: Develop photonics electronics convergence key technology based on Si photonics

➢ Term: FY 2012~2021➢ Sponsor: METI, NEDO➢ Members: NEC, Fujitsu, OKI, Toshiba, Furukawa Electric, NEL,

NTT, AIST, OITDA [www.petra-jp.org]

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Outline

➢ Si-PIC, PETRA & New Venture

➢ PETRA Platform

➢ Validation Flow & Process Control Monitoring (PCM)

➢ AIO Core Co. Ltd.

➢ Summary

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Fabrication300mm SOI

40-nm CMOS ProcessOptical PCM

DesignPhotonic Device Library

Unified library for C/O-band PSM & WDM

Compact Models, Circuit Level Sim.

ValidationWafer-Level TestingVariation Modeling

Grating Coupler Ge Photodetector Waveguide & Heater Modulator

DFV Building Blocks

O-band Wavegide loss

Wavelength (nm)

Tran

smit

tan

ce (

dB

)

Modulator

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Process of F Block

Fiber

Process Spec.

Substrate 300-mm SOI

LithographyArF immersion for waveguideDry excimer for the others

Waveguide formation

Full etching for wire-waveguideShallow etching for GCDeep etching for modulator

Implantation P-/P+/N-/N+ for modulator, detector

CMP & Wiring 2-level metal wiring on planarized Clad

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Device Parameter C-band O-band

Waveguide Propagation loss 0.4dB/cm 1.4dB/cm

Grating Coupler Coupling loss 3.5dB 2.5dB

PN Modulator 3dB Bandwidth >25Gbps >25Gbps

Ge Detector 3dB Bandwidth >25Gbps >25Gbps

4-l CWDM FilterCross talk

Insertion loss>15dB

1dB>10dB

1dB

Device Performance

0.1

1

10

2000 2005 2010 2015C-ba

nd

wav

egu

ide lo

ss(d

B/cm

)

Year

EBKrFArFArF-Immersion

G-Line100

100 Gbps (25G x 4ch.)PSM TRX Chip

PETRA

[Kurata, IEDM 2017][Horikawa, JSTQE 2018]

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Outline

➢ Silicon-based Photonic Integrated Circuit (Si-PIC)

➢ PETRA Platform

➢ Validation Flow & Process Control Monitoring (PCM)

➢ AIO Core Co. Ltd.

➢ Summary

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Automatic optical measurement unit added on electrical full-auto prober.✓ Small alignment accuracy < 0.3 mm by optical active alignment.✓ Reproducibility of optical fiber coupling <0.2 dB

Field image in GC-fiber coupling

Reproducibility in the automatic search of coupling position

From DUT XY

Fiber probe head

Optical Coupling between Wafer and Probe[Horikawa, NANOTS 2015]

Wafer-Level Testing of V Block

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Light Propagation Through Si Waveguide

Lowest TE Mode Fieldin Si Waveguide

180 200 2202

4

4.6

460 480 500

Width (nm) Height (nm)

Re

fra

ctive

in

dic

es

Re

fra

ctive

in

dic

es

𝑛𝑔𝑛𝑔

𝑛𝑒𝑛𝑒

2.2

2.4

2.6

4.2

4.4

2

4

4.6

2.2

2.4

2.6

4.2

4.4

Si Core

Clad SiO2

500 nm

✓ Mode Field Extends to Clad Area.✓ Effective Index 𝑛𝑒 Determines Light Propagation.

Width and Height -> Confinement -> 𝑛𝑒✓ Group Index 𝑛𝑔 Determines Wavelength Dispersion.

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Optical PCM

Microring resonator

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➢Microring PCMInput port

Through port

Drop port

1500 1510 1520 1530 1540

0

-10

-15

-20

Tran

smit

tan

ce (

dB

)

Wavelength (nm)

Free spectral Range (FSR)

lm lm-1lm+1

Typical drop-port spectrum for MRR

Resonant Condition for MRR

𝑛𝑒 ∙ 𝐿 = m ∙ 𝜆

𝑛𝑔 ∙ 𝐿 ∙ 𝐹𝑆𝑅 = 𝜆2

[𝐿: ring perimeter, m: integer]

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4.23

4.24

4.25

4.26

1510 1520 1530 1540

ng

Resonant wavelength (nm)

4.50

4.51

4.52

4.53

4.54

4.55

1300 1310 1320 1330 1340

ng

Resonant wavelength (nm)

4.50

4.51

4.52

4.53

4.54

4.55

1300 1310 1320 1330 1340

ng

Dng/Dl = − 0.0030 nm-1

Resonant wavelength (nm)

Resonant wavelength (nm)

4.23

4.24

4.25

4.26

1510 1520 1530 1540 1550

ng

C-band R=6 mm

Dng/Dl = − 0.0027 nm-1

C-band R=10 mm

O-band R=4 mm O-band R=6 mm

Wafer-scale Variation

[Horikawa, ECOC 2017]

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1.6

0.8

0.0

-0.8

-1.6

6.0

3.0

0.0

-3.0

-6.0

Extracted and Measured Deviations

Extracted Measured

Extracted Experimental

Height deviation, 3sH 0.75 nm 0.72 nm

Width deviation, 3sW 4.3 nm 3.9 nm

-0.21 -0.20 -0.10 0.13

-0.38 -0.24 -0.25 -0.01 0.13 0.23 0.29 0.33

-0.36 -0.26 -0.20 -0.26 -0.16 0.10 0.27 0.27 0.54 0.46

-0.29 -0.17 -0.17 -0.23 -0.14 0.03 0.23 0.38 0.58 0.27

-0.36 -0.07 -0.25 -0.22 0.01 -0.01 0.03 0.49 0.54 0.48

-0.29 0.11 0.07 -0.23 -0.08 -0.16 0.04 0.22 0.48 0.53

-0.35 -0.04 -0.06 -0.17 -0.27 0.02 0.12 0.11

-0.46 -0.47 -0.25 -0.13

-0.15 -0.08 0.02 -0.11

-0.26 -0.30 -0.20 -0.06 0.03 -0.01 -0.03 0.09

-0.29 -0.38 -0.24 -0.07 0.06 0.13 0.14 0.07 0.15 0.26

-0.33 -0.29 -0.17 -0.02 0.08 0.18 0.22 0.26 0.37 0.43

-0.31 -0.24 -0.19 -0.07 0.02 0.10 0.19 0.34 0.52 0.54

-0.23 -0.34 -0.31 -0.14 -0.05 0.03 0.12 0.25 0.45 0.47

-0.30 -0.31 -0.22 -0.13 -0.06 0.01 0.10 0.24

-0.31 -0.36 -0.23 -0.12

1.14 1.01 1.37 0.12

-0.05 0.75 -0.98 -0.67 -0.65 -0.65 0.58 1.57

-0.09 1.20 0.00 -1.37 -1.85 -2.46 -1.65 -0.74 0.34 1.29

1.23 0.85 -0.15 -2.66 -2.93 -1.73 -2.55 -1.61 0.00 2.38

0.56 1.06 0.15 -1.91 -2.37 -1.99 -1.90 -1.04 -0.02 1.40

-2.93 -0.05 0.50 -0.74 -0.51 0.05 -0.24 1.20 1.84 1.46

-0.44 1.56 0.68 1.71 2.60 1.76 2.81 1.45

-0.98 1.15 0.97 1.14

-1.23 0.04 -0.35 -1.63

-1.23 1.85 0.83 0.82 0.30 2.09 -0.44 -0.13

-1.16 2.13 0.26 0.73 -1.48 -0.77 -0.08 1.11 1.76 -0.06

1.87 0.23 0.33 -0.90 -1.15 -1.63 -0.53 -2.37 0.66 0.16

0.44 0.85 -0.81 0.14 -3.45 -3.44 -1.85 -1.58 -0.54 1.40

0.53 -1.74 -0.21 -0.19 -0.03 -1.08 0.33 -0.75 -0.10 -0.44

1.59 0.77 0.47 0.15 -0.25 -0.70 1.24 2.03

1.80 1.20 1.84 2.43

[Horikawa, JSTQE 2017]

𝛥𝐻𝐸𝑥𝑡𝑟𝑎𝑐𝑡𝑒𝑑(nm) 𝛥𝐻𝐸𝑙𝑖𝑝𝑠𝑜, 𝑖𝑛𝑖𝑡𝑖𝑎𝑙(nm)

𝛥𝑊𝐸𝑥𝑡𝑟𝑎𝑐𝑡𝑒𝑑(nm) 𝛥𝑊𝑆𝐸𝑀 (nm)

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Outline

➢ Si-PIC, PETRA & New Venture

➢ PETRA Platform

➢ Process Control Monitoring

➢ AIO Core Co. Ltd.

➢ Summary

17October 26th, 2018 Tokyo Japan SOI Design Workshop

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➢ Location:(Headquarter) Bunkyo-ku, Tokyo

➢ Capital Stock:270M yen (≒2.5M US$)

➢ Asset (Beginning): Succession of IP from PETRA

➢ Business:Production & Sales of Optical I/O Core

➢ CEO : Tomoyuki Fujita.

➢ Date of Establishment:April 17th, 2017

AIO Core Co. Ltd.

October 26th, 2018 Tokyo Japan SOI Design Workshop 18

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Summary

◆ Silicon-based PIC is promising for high-speed datatransmission.

◆ PETRA platform consists of design, fabrication, andvalidation. PETRA platform using 300-mm SOI wafersrealizes low loss waveguide devices suitable for largescale Si-PIC.

◆ Process control monitoring using microringresonators has been examined for monitoringwaveguide deviations. It is successfully demonstratedthat extracted deviations agree with that of physicalmeasurement within sub-nanometer.

October 26th, 2018 Tokyo Japan SOI Design Workshop 19

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Thank you !

October 26th, 2018 Tokyo Japan SOI Design Workshop 20