Tim Bannon Product Manager, EMEA RoHS & WEEE Compliance Programme Update.
Peter Bannon VP of Architecture and Verification September 20, 2007
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Transcript of Peter Bannon VP of Architecture and Verification September 20, 2007
September 2007 1
Peter Bannon
VP of Architecture and Verification
September 20, 2007
Announcing PWRficient Processors from PA Semi, the Most Power Efficient, High Performance Processors Available
September 2007 2
250nm 180nm 130nm 90nm 65nm 45nm
The Escalating Power Problem
Shrinking device geometries provides
Faster gates Increased density
BUT
Moore’s Law means more power
EXCESSIVE POWER DISSIPATION LIMITS USABLE GATE CAPACITY
Power Density
CapacityGap
Process Technology
Area/Gate
September 2007 3
Choosing Power Over Ultimate Performance
Look for the exponential opportunities in power/performanceGive up some performance for substantial power decrease
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Performance
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Old design point
New design point
September 2007 4
Design Choices for Low Power
Design choices at several levels favor low power CMOS process target Circuit design style and sizing Micro-architecture features
Integration Saves interface power
Management Voltage/frequency scaling Multiple power planes for optimal voltage selection per region Clock gating to reduce power of idle circuits Active and pre-charge standby modes in DRAM array PCIe power saving modes Nap and Sleep modes for CPU
September 2007 5
Fine-Grained Clock Gating Reduces Dynamic Power
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Normal OperationWorst Case
Time
Coarse-Grained Clock Gating
September 2007 6
PWRficient PA6T-1682M Block Diagram
*Transaction trace memory †Peripheral trace memory
OffloadEnginesOffloadEngines
64KB I-Cache
64KBD-Cache
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R2
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2MB L2 Cache
2MB L2 Cache
I/O Cache
I/O Cache
SMBus (3)
UART (2)
Boot Bus
Power Control
System Control
Interrupt/GPIO
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ConfigurableSERDES (24)ConfigurableSERDES (24)
Quad GbESGMII
Quad GbESGMII
Dual 10GbEXAUI
Dual 10GbEXAUI
BridgeBridge DMADMA
TTM*TTM*
Octal PCI Express
Octal PCI Express
PTM†PTM†
64KB I-Cache
64KBD-Cache
PA6T 2GHz Core
CONEXIUM™ Interchange
PA6T 2GHz Core
ENVOI™Intelligent I/O
September 2007 7
Voltage/Frequency Scaling
Max Freq
Typ Max
PA6T-1682M-FCN
2.0GHz 17W 25W
PA6T-1682M-FCG
1.5GHz 8W 15W
PA6T-1682M-FCD
1.0GHz 6W 10W
I/O coherent nap 2W*
PA6T CorePA6T Core
PA6T CorePA6T Core
SoCSoC VRMVRM
VRMVRM
VRMVRM
VDD_SoC
VID_SoC
VDD_CP0
VID_CP0
Multiple power planes for maximum control
VID regulators for cores, SoCAbility to scale both Vdd and
frequency on demand results in highly optimized total power
PA6T-1682M
*PA6T-1682M-FCN nap power may be higher
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VDD_CP1
VID_CP16
September 2007 8
Summary – The Green Computing Advantage
PWRficient processors set the bar for ultimate energy conservation at full performance
Lowest total energy for a computation or transaction
PWRficient processors are designed to reduce system power
Optional use of power standby mode in DDR2 memories
Only minimal performance compromises to meet power-efficiency goals
Significant operating-cost savings for cluster-based computing
Power conservation a key initiative from architectural concept though design