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Pertemuan 7

Bahasa Rakitan: III

Matakuliah : T0324 / Arsitektur dan Organisasi Komputer

Tahun : 2005

Versi : 1

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Learning Outcomes

Pada akhir pertemuan ini, diharapkan mahasiswaakan mampu :

Mendemonstrasikan penggunaan bahasa

rakitan dalam instruksi mesin ( C3 ) ( NoTIK : 3 )

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Chapter 2.

Assembly Language: III

(OFC1)

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Move #AVEC,R1 R1pointstovectorA.Move #BVEC,R2 R2pointstovectorB.Move N,R3 R3servesasacounter.Clear R0 R0accumulatesthedotproduct.

LOOP Move (R1)+,R4 ComputetheproductofMultiply (R2)+,R4 nextcomponents.

Add R4,R0 Add toprevioussum.Decrement R3 Decrement thecounter.Branch>0 LOOP Loopagainif notdone.Move R0,DOTPROD Storedotproductinmemory.

Figure 2.33. A program for computing the dot product of two vectors.

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for (j = n 1;j > 0;j = j 1){ for ( k = j 1; k > = 0; k = k 1 )

{ if (LIST[ k] > LIST[ j]){ TEMP = LIST[ k];

LIST[ k] = LIST[ j];LIST[ j] = TEMP;

}}

}

Mo ve #LIST,R0 Load LIST into base register R0.

Mo ve N,R1 Initialize outer loop indexSubtract #1,R1 register R1 to j = n 1.OUTER Mo ve R1,R2 Initialize inner loop index

Subtract #1,R1 register R2 to k = j 1.Mo veByte (R0,R1),R3 Load LIST( j) into R3, whic h holds

current maxim um in sublist.INNER CompareByte R3,(R0,R2) If LIST( k) [R3],

Branc h 0 NEXT do not exhange.Mo veByte (R0,R2),R4 Otherwise, exchange LIST( k)Mo veByte R3,(R0,R2) with LIST( j ) and loadMo veByte R4,(R0,R1) new maxim um into R3.Mo veByte R4,R3 Register R4 serves as TEMP .

NEXT Decremen t R2 Decremen t index registers R2 andBranc h 0 INNER R1, whic h also serveDecremen t R1 as loop coun ters, and branc hBranc h> 0 OUTER back if loops not finished.

(b) Assembly language program for sorting

Figure 2.34. A byte-sorting program using a straight-selection sort.

(a) C-language program for sorting

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Record 1

(a) Linking structure

Record 2 Recordk

Link address

Head Tail

0

Record 2Record 1

New record

(b) Inserting a new record between Record 1 and Record 2

Figure 2.35. Linked-list data structure.

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Record 1

(a) Linking structure

Record 2 Recordk

Link address

Head Tail

0

Record 2Record 1

New record

(b) Inserting a new record between Record 1 and Record 2

Figure 2.35. Linked-list data structure.

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Figure 2.36. A list of student test scores organized as a linked list in memory.

First

28106 12001040

1 word 1 word 3 words

Head

(ID) (Test scores)

Memory

address

Key

field

Link

field

Data

field

record 27243 10402320

40632 12802720

28370 28801200

47871 01280

Secondrecord

Thirdrecord

Second last

Lastrecord

record

Tail

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DELETION Compare (RHEAD), RIDNUM

Branch>0 SEARCH

Move 4(RHEAD), RHEAD

Return

Move RHEAD, RCURRENT

Move 4(RCURRENT), RNEXT

Compare (RNEXT), RIDNUM

Branch=0 DELETE

Move RNEXT, RCURRENT

Branch

Move 4(RNEXT), RTEMP

RTEMP, 4(RCURRENT)

Return

LOOP

Move

not the head record

SEARCH

LOOP

DELETE

Figure 2.38. A subroutine for deleting a record from a linked list.

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OP code

Figure 2.39. Encoding instructions into 32-bit words.

Source Dest Other info

8 7 7 10

(b) Two-word instruction

Memory address/Immediate operand

OP code

(c) Three-operand instruction

Ri Rj Other infoRk

OP code Source Dest Other info

(a) One-word instruction

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Table 2.1Generic addressing modes

Name Assem bler syntax Addressing function

Immediate #Value Operand = Value

Register R i EA = RiAbsolute (Direct) LOC EA = LOC

Indirect (R i) EA = [R i](LOC) EA = [LOC]

Index X(R i) EA = [R i] + XBase with index (R i ,Rj ) EA = [R i] + [Rj]Base with index X(R i,Rj ) EA = [R i] + [Rj] + X

and offset

Relative X(PC) EA = [PC] + X

Autoincremen t (R i)+ EA = [R i] ;Incremen t R i

Autodecrement (R i) Decremen t R i ;EA = [R i]

EA = effectiv e addressValue = a signed number

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Pertemuan 8

Bahasa Rakitan: IV

Matakuliah : T0324 / Arsitektur dan Organisasi Komputer

Tahun : 2005

Versi : 1

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Learning Outcomes

Pada akhir pertemuan ini, diharapkan mahasiswaakan mampu :

Mendemonstrasikan penggunaan bahasa

rakitan dalam instruksi mesin ( C3 ) ( NoTIK : 3 )

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Chapter 2.

Assembly Language: IV(OFC2)

/ /

/

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. . .

/

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# include

void main(void)

{

long NUM1[5];long SUM;long N;

NUM1[0] = 17;NUM1[1] = 3;NUM1[2] = 51;NUM1[3] = 242;NUM1[4] = 113;SUM = 0;

N = 5;asm {

LEA EBX,NUM1MO V ECX,NMO V EAX,0MO V EDI,0

STAR TADD: ADD EAX,[EBX + EDI*4]INC EDIDEC ECXJG STAR TADDMO V SUM,EAX

}

printf ("The sum of the list values is %ld \n", SUM );}

Figure D.2. IA-32 Program in Figure 3.40aencapsulated in a C/C++ program.

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Machine instructions Assembly language instructions(hexadecimal)

03 04 BB STARTADD: ADD EAX,[EBX + EDI*4]47 INC EDI49 DEC ECX7F F9 JG STAR TADD

(a) Loop body encoding

OP code ModR/M byte SIB byte

03 04 BB00000011 00 000 100 10 111 011

ADD (see Table D.2) (see Figure D.1c )(doubleword

(b) ADD instruction

OP code Offset

7F F9

01111111 111111001JG 7(short offset)

(c) JG instruction

Figure D.3. Encoding of the loop body in Figure D.2.

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TABLE D.1Register field encodingin IA-32 instructions

Reg/Base/Index* Registerfield

0 0 0 EAX0 0 1 ECX0 1 0 EDX0 1 1 EBX1 0 0 ESP1 0 1 EBP1 1 0 ESI1 1 1 EDI

*ESP (100) cannot be used as an

index register.

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TABLE D.2IA-32 addressing modes selected by the ModR/M and SIB bytes

ModR/M byte Addressing mode

Mod R/Mfield fieldb7 b6 b2 b1 b0

0 0 Reg Register indirectEA = [Reg]

0 1 Reg Base with 8-bit displacementEA = [Reg] + Disp8

1 0 Reg Base with 32-bit displacementEA = [Reg] + Disp32

1 1 Reg RegisterEA = Reg

Exceptions

0 0 1 0 1 DirectEA = Disp32

0 0 1 0 0 Base with index (uses SIB byte)EA = [Base] + [Index] Scale

When Base = EBP the addressing mode is:Index with 32-bit displacement

EA = [Index] Scale + Disp32

0 1 1 0 0 Base with index and 8-bit displacement (uses SIB byte)EA = [Base] + [Index] Scale + Disp8

1 0 1 0 0 Base with index and 32-bit displacemet (uses SIB byte)EA = [Base] + [Index] Scale + Disp32

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TABLE D.3Scale field encodingin IA-32 SIB byte

Scale field Scale

0 0 10 1 21 0 41 1 8

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TABLE D.4IA-32 instructions

Mnemonic Size Operands Operation CC flags(Name) performed affected

dst src S Z O C

ADC B,D reg reg dst [dst] + [src] + [CF] x x x x(Add with reg memcarry) mem reg

reg immmem imm

ADD B,D reg reg dst [dst] + [src] x x x x(Add) reg mem

mem regreg imm

mem imm

AND B,D reg reg dst [dst] ^ [src] x x 0 0(Logical reg memAND) mem reg

reg immmem imm

BT D reg reg bit# = [src]; x(Bit test) reg imm8 CF bit# of [dst]

mem regmem imm8

BTC D reg reg bit# = [src]; x(Bit test and reg imm8 CF bit# of [dst];complement mem reg complement bit#

mem imm8 of [dst]

BTR D reg reg bit# = [src]; x(Bit test reg imm8 CF bit# of [dst];and reset) mem reg clear bit# of [dst] to 0

mem imm8

Table D.4page 1

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TABLE D.4(Continued )


dst src S Z O C

BTS D reg reg bit# = [src]; x(Bit test reg imm8 CF bit# of [dst];and set) mem reg set bit# of [dst] to 1

mem imm8

CALL D reg ESP [ESP] 4;(Subroutine mem [ESP] [EIP];call) EIP EA of dst

CLC CF 0 0(Clear carry)

CLI IF 0(Clear int. flag)

CMC CF [CF] x(Compl. carry)

CMP B,D reg reg [dst] [src] x x x x(Compare) reg mem

mem regreg immmem imm

DEC B,D reg dst [dst] 1 x x x(Decrement) mem

DIV B,D reg for B: ? ? ? ?(Unsigned mem [AL]/[src];divide) AL quotient;

AH remainderfor D:

[EAX]/[src];EAX quotient;ED X remainder

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TABLE D.4(Continued )


dst src S Z O C

HLT Halts execution un til

(Halt) reset or externalinterrupt occurs

IDIV B,D reg for B: ? ? ? ?(Signed mem [AL]/[src];divide) AL quotient;

AH remainderfor D:

[EAX]/[src];EAX quotient;ED X remainder

IMUL B,D reg (double-length product) ? ? x x(Signed mem for B:multiplication) AX [AL] [src]

for D:ED X,EAX [EAX]

[src]

D reg reg (single-length pro duct) ? ? x xreg mem reg [reg] [src]

IN B,D dst = AL AL or EAX [src](Isolated or EAX

input) src = imm8or [DX]

INC B,D reg dst [dst] + 1 x x x(Increment ) mem

INT D imm8 Push EFLA GS;(Software Push EIP;interrupt) EIP address

(determined by imm8)

Table D.4page 3

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TABLE D.4(Continued)


dst src S Z O C

IRET D Pop EIP; x x x x(Return from Pop EFLA GSinterrupt)

LEA D reg mem reg EA of src(Load effectiv eaddress)

LOOP D target ECX [ECX] 1;(Lo op) If ( [ECX] 0 )

EIP target

LOOPE D target ECX [ECX] 1;(Lo op on If ( [ECX] 0equal/zero) ^ [Z] = 1 )EIP target

LOOPNE D target ECX [ECX] 1;(Lo op on If ( [ECX] 0not equal/ ^ [Z] 1 )not zero) EIP target

MO V B,D reg reg dst [src](Mo ve) reg memmem regreg immmem imm

MO VSX B reg reg reg sign extend [src](Sign extend reg membyte intoregister)

Table D.4page 4

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dst src S Z O C

MO VZX B reg reg reg zero extend [src](Zero extend reg membyte intoregister)

MUL B,D reg (double-length pro duct) ? ? x x(Unsigned mem for B:multiplication) AX [AL] [src]

for D:ED X,EAX [EAX]

[src]

NEG B,D reg dst 2's-complement x x x x(Negate) mem [dst]

NOP alias for:(No operation) XCHG EAX,EAX

NOT B,D reg dst [dst ](Logical memcomplement)

OR B,D reg reg dst [dst]

[src] x x 0 0(Logical OR) reg mem


OUT B,D dst = imm8 dst [AL] or [EAX](Isolated or [DX]output) src = AL

or EAX

Table D.4page 5

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dst src S Z O C

POP D reg dst [[ESP]];(Pop off mem ESP [ESP] + 4stack)

POPAD D Pop eight doublewords(Pop off off stack intostack into EDI, ESI, EBP , discard,all registers EBX, EDX, ECX, EAX;except ESP) ESP [ESP] + 32

PUSH D reg ESP [ESP] 4;(Push onto mem [ESP] [src]

stack) imm

PUSHAD D Push contents of(Push all EAX, ECX, EDX, EBX,registers ESP , EBP , ESI, EDIonto stack) onto stack;

ESP [ESP] 32

RCL B,D reg imm8 See Figure 2.32 b; ? x(Rotate left reg CL src operand iswith C flag) mem imm8 rotation count

mem CL

RCR B,D reg imm8 See Figure 2.32 d; ? x(Rotate righ t reg CL src operand iswith C flag) mem imm8 rotation count

mem CL

RET EIP [[ESP]];(Return from ESP [ESP] + 4subroutine)

Table D.4

page 6

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dst src S Z O C

ROL B,D reg imm8 See Figure 2.32a; ? x(Rotate left) reg CL src operand is

mem imm8 rotation countmem CL

ROR B,D reg imm8 See Figure 2.32c; ? x(Rotate righ t) reg CL src operand is

mem imm8 rotation countmem CL

SAL B,D reg imm8 See Figure 2.30a; x x ? x(Shift reg CL src operand is

arithmetic mem imm8 shift countleft) mem CLsame as SHL

SAR B,D reg imm8 See Figure 2.30c; x x ? x(Shift reg CL src operand isarithmetic mem imm8 shift countright) mem CL

SBB B,D reg reg dst [dst] [src] x x x x(Subtract reg mem [CF]with borrow) mem reg

reg immmem imm

SHL B,D reg imm8 See Figure 2.30a; x x ? x(Shift reg CL src operand isleft) mem imm8 shift countsame as SAL mem CL

Table D.4

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dst src S Z O C

SHR B,D reg imm8 See Figure 2.30b; x x ? x(Shift reg CL src operand isrigh t) mem imm8 shift coun t

mem CL

STC CF 1 1(Set carryflag)

STI IF 1(Set interrupt

flag)

SUB B,D reg reg dst [dst] [src] x x x x(Subtract) reg mem


TEST B,D reg reg [dst] ^ [src]; x x 0 0(Test) mem reg set flags based

reg imm on result

mem immXCHG B,D reg reg [reg] [src](Exchange) reg mem

XOR B,D reg reg dst [dst] [src] x x 0 0(Exclusive reg memOR) mem reg

reg immmem imm

Table D.4page 8

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TABLE D.5IA-32 conditional jump instructions

Mnemonic Condition Condition codename test

JS Sign (negative) SF = 1JNS No sign (positive or zero) SF = 0

JE/JZ Equal/Zero ZF = 1JNE/JNZ Not equal/Not zero ZF = 0JO Overflow OF = 1JNO No overflow OF = 0JC/JB Carry/Unsigned below CF = 1JNC/JAE No carry/Unsigned above or equal CF = 0JA Unsigned above CF ZF = 0JBE Unsigned below or equal CF ZF = 1JGE Signed greater than or equal SF OF = 0JL Signed less than SF OF = 1

JG Signed greater than ZF (SF OF) = 0JLE Signed less than or equal ZF (SF OF) = 1

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