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Pertemuan 7

Bahasa Rakitan: III

Matakuliah : T0324 / Arsitektur dan Organisasi Komputer

Tahun : 2005

Versi : 1

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Learning Outcomes

Pada akhir pertemuan ini, diharapkan mahasiswaakan mampu :

Mendemonstrasikan penggunaan bahasa

rakitan dalam instruksi mesin ( C3 ) ( NoTIK : 3 )

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Chapter 2.

Assembly Language: III

(OFC1)

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Move #AVEC,R1 R1pointstovectorA.Move #BVEC,R2 R2pointstovectorB.Move N,R3 R3servesasacounter.Clear R0 R0accumulatesthedotproduct.

LOOP Move (R1)+,R4 ComputetheproductofMultiply (R2)+,R4 nextcomponents.

Add R4,R0 Add toprevioussum.Decrement R3 Decrement thecounter.Branch>0 LOOP Loopagainif notdone.Move R0,DOTPROD Storedotproductinmemory.

Figure 2.33. A program for computing the dot product of two vectors.

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for (j = n 1;j > 0;j = j 1){ for ( k = j 1; k > = 0; k = k 1 )

{ if (LIST[ k] > LIST[ j]){ TEMP = LIST[ k];

LIST[ k] = LIST[ j];LIST[ j] = TEMP;

}}

}

Mo ve #LIST,R0 Load LIST into base register R0.

Mo ve N,R1 Initialize outer loop indexSubtract #1,R1 register R1 to j = n 1.OUTER Mo ve R1,R2 Initialize inner loop index

Subtract #1,R1 register R2 to k = j 1.Mo veByte (R0,R1),R3 Load LIST( j) into R3, whic h holds

current maxim um in sublist.INNER CompareByte R3,(R0,R2) If LIST( k) [R3],

Branc h 0 NEXT do not exhange.Mo veByte (R0,R2),R4 Otherwise, exchange LIST( k)Mo veByte R3,(R0,R2) with LIST( j ) and loadMo veByte R4,(R0,R1) new maxim um into R3.Mo veByte R4,R3 Register R4 serves as TEMP .

NEXT Decremen t R2 Decremen t index registers R2 andBranc h 0 INNER R1, whic h also serveDecremen t R1 as loop coun ters, and branc hBranc h> 0 OUTER back if loops not finished.

(b) Assembly language program for sorting

Figure 2.34. A byte-sorting program using a straight-selection sort.

(a) C-language program for sorting

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Record 1

Record 2 Recordk

0

Record 2Record 1

New record

(b) Inserting a new record between Record 1 and Record 2

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Record 1

Record 2 Recordk

0

Record 2Record 1

New record

(b) Inserting a new record between Record 1 and Record 2

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Figure 2.36. A list of student test scores organized as a linked list in memory.

First

28106 12001040

1 word 1 word 3 words

(ID) (Test scores)

Memory

Key

field

field

Data

field

record 27243 10402320

40632 12802720

28370 28801200

47871 01280

Secondrecord

Thirdrecord

Second last

Lastrecord

record

Tail

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Branch>0 SEARCH

Return

Move 4(RCURRENT), RNEXT

Compare (RNEXT), RIDNUM

Branch=0 DELETE

Move RNEXT, RCURRENT

Branch

Move 4(RNEXT), RTEMP

RTEMP, 4(RCURRENT)

Return

LOOP

Move

SEARCH

LOOP

DELETE

Figure 2.38. A subroutine for deleting a record from a linked list.

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OP code

Figure 2.39. Encoding instructions into 32-bit words.

Source Dest Other info

8 7 7 10

(b) Two-word instruction

OP code

(c) Three-operand instruction

Ri Rj Other infoRk

OP code Source Dest Other info

(a) One-word instruction

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Name Assem bler syntax Addressing function

Immediate #Value Operand = Value

Register R i EA = RiAbsolute (Direct) LOC EA = LOC

Indirect (R i) EA = [R i](LOC) EA = [LOC]

Index X(R i) EA = [R i] + XBase with index (R i ,Rj ) EA = [R i] + [Rj]Base with index X(R i,Rj ) EA = [R i] + [Rj] + X

and offset

Relative X(PC) EA = [PC] + X

Autoincremen t (R i)+ EA = [R i] ;Incremen t R i

Autodecrement (R i) Decremen t R i ;EA = [R i]

EA = effectiv e addressValue = a signed number

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Pertemuan 8

Bahasa Rakitan: IV

Matakuliah : T0324 / Arsitektur dan Organisasi Komputer

Tahun : 2005

Versi : 1

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Learning Outcomes

Pada akhir pertemuan ini, diharapkan mahasiswaakan mampu :

Mendemonstrasikan penggunaan bahasa

rakitan dalam instruksi mesin ( C3 ) ( NoTIK : 3 )

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Chapter 2.

Assembly Language: IV(OFC2)

/ /

/

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. . .

/

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# include

void main(void)

{

long NUM1[5];long SUM;long N;

NUM1[0] = 17;NUM1[1] = 3;NUM1[2] = 51;NUM1[3] = 242;NUM1[4] = 113;SUM = 0;

N = 5;asm {

LEA EBX,NUM1MO V ECX,NMO V EAX,0MO V EDI,0

}

printf ("The sum of the list values is %ld \n", SUM );}

Figure D.2. IA-32 Program in Figure 3.40aencapsulated in a C/C++ program.

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(a) Loop body encoding

OP code ModR/M byte SIB byte

03 04 BB00000011 00 000 100 10 111 011

ADD (see Table D.2) (see Figure D.1c )(doubleword

OP code Offset

7F F9

01111111 111111001JG 7(short offset)

(c) JG instruction

Figure D.3. Encoding of the loop body in Figure D.2.

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TABLE D.1Register field encodingin IA-32 instructions

Reg/Base/Index* Registerfield

0 0 0 EAX0 0 1 ECX0 1 0 EDX0 1 1 EBX1 0 0 ESP1 0 1 EBP1 1 0 ESI1 1 1 EDI

*ESP (100) cannot be used as an

index register.

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TABLE D.2IA-32 addressing modes selected by the ModR/M and SIB bytes

Mod R/Mfield fieldb7 b6 b2 b1 b0

0 0 Reg Register indirectEA = [Reg]

0 1 Reg Base with 8-bit displacementEA = [Reg] + Disp8

1 0 Reg Base with 32-bit displacementEA = [Reg] + Disp32

1 1 Reg RegisterEA = Reg

Exceptions

0 0 1 0 1 DirectEA = Disp32

0 0 1 0 0 Base with index (uses SIB byte)EA = [Base] + [Index] Scale

When Base = EBP the addressing mode is:Index with 32-bit displacement

EA = [Index] Scale + Disp32

0 1 1 0 0 Base with index and 8-bit displacement (uses SIB byte)EA = [Base] + [Index] Scale + Disp8

1 0 1 0 0 Base with index and 32-bit displacemet (uses SIB byte)EA = [Base] + [Index] Scale + Disp32

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TABLE D.3Scale field encodingin IA-32 SIB byte

Scale field Scale

0 0 10 1 21 0 41 1 8

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TABLE D.4IA-32 instructions

Mnemonic Size Operands Operation CC flags(Name) performed affected

dst src S Z O C

ADC B,D reg reg dst [dst] + [src] + [CF] x x x x(Add with reg memcarry) mem reg

reg immmem imm

ADD B,D reg reg dst [dst] + [src] x x x x(Add) reg mem

mem regreg imm

mem imm

AND B,D reg reg dst [dst] ^ [src] x x 0 0(Logical reg memAND) mem reg

reg immmem imm

BT D reg reg bit# = [src]; x(Bit test) reg imm8 CF bit# of [dst]

mem regmem imm8

BTC D reg reg bit# = [src]; x(Bit test and reg imm8 CF bit# of [dst];complement mem reg complement bit#

mem imm8 of [dst]

BTR D reg reg bit# = [src]; x(Bit test reg imm8 CF bit# of [dst];and reset) mem reg clear bit# of [dst] to 0

mem imm8

Table D.4page 1

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TABLE D.4(Continued )

Mnemonic Size Operands Operation CC flags(Name) performed affected

dst src S Z O C

BTS D reg reg bit# = [src]; x(Bit test reg imm8 CF bit# of [dst];and set) mem reg set bit# of [dst] to 1

mem imm8

CALL D reg ESP [ESP] 4;(Subroutine mem [ESP] [EIP];call) EIP EA of dst

CLC CF 0 0(Clear carry)

CLI IF 0(Clear int. flag)

CMC CF [CF] x(Compl. carry)

CMP B,D reg reg [dst] [src] x x x x(Compare) reg mem

mem regreg immmem imm

DEC B,D reg dst [dst] 1 x x x(Decrement) mem

DIV B,D reg for B: ? ? ? ?(Unsigned mem [AL]/[src];divide) AL quotient;

AH remainderfor D:

[EAX]/[src];EAX quotient;ED X remainder

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TABLE D.4(Continued )

Mnemonic Size Operands Operation CC flags(Name) performed affected

dst src S Z O C

HLT Halts execution un til

(Halt) reset or externalinterrupt occurs

I