Performed by: Roi Sherman Eyal Wilamowski Instructor: Mr. Michael Itzkovich

Performed by: Roi ShermanEyal Wilamowski

Instructor: Mr. Michael Itzkovich

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

דו”ח סיכום פרויקט )חלק א’(Subject:

Generic Daughter Board For 5510 EVM

סמסטר חורף תשס"ב

AbstractHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

The project aim is to implement a general purpose daughter board for the TI 5510 EVM prototype board. The card could be used for connecting of up to 4 DSP’s through the McBSP for Parallel Computation and system resources sharing.

The card would have the ability to operate as master in a standalone mode, or even connect to an expansion board of it’s own.

The implemented card is generic as possible yielding maximum use of pins, connectors etc. High percent of all resources are not purpose and controlled by the main control unit.

System descriptionHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

• 5v power supply

• 8MBytes Address Space

• 32 Bit Data Bus

• 3.3v operation for all components

• FPGA Control Unit

• JTAG programming interface

Control Unit)Altera(

RS232

GPIO

2MBSRAM

1MBFlash

MB

Interface

Peripheral Interface

EMIF

McBSP

• General Purpose discrete interface

System description (cont.)High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

• 2 x RS232 serial channels

• 3 x McBSP channels

• Led Indicators

• 1MB Flash Memory

• 2MB Asynchronous SRAM


RS232

GPIO

2MBSRAM

1MBFlash

MB

Interface

Peripheral Interface

EMIF

McBSP

Hardware SpecificationHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

• Altera’s EPF10K100ARC-1 FPGA

• Altera’s EPC2TC32

• 2 x AMD 4Mb Flash Memory AM29LV400BT-70

• 4 x Alliance 4Mb Async SRAM AS7C34098-10TC

• 16-Bit Bus Transceivers SN74LVTH16245

• National’s LM1085 Voltage Regulator

• 2 x RS-232 MAX3238 Transceivers

Hardware Specification (cont.)High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

• 40MHz Oscillator

• 1.8432MHz Oscillator

• 2 x TL16C550CPT Single UART with FIFO

• SN74LVC08A AND gates

• MAX821TUS-T Voltage Monitor

http://www.amd.com/us-en

EV

M 5510

Flash MemoryHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות


Data

Address

MB Control

DB

Control

4MbFlash4Mb

Flash

MAIN PROPERTIES

2 X 4Mb AMD Flash memory.

PN: AM29LV400-70. Package TSOP 48 pin .

Could be replaced by larger sized ICs with same pinout. Up to total of 4MBytes.

Conclusion:

Fast , Reliable Manufacturer, Upgradeable.

IC Arrangement 16*256M .


X_D22

X_D19

X_A20

X_D16

X_D13

X_A[2..21]

3.3V

X_D31

X_A10

FLASH0_RDY

X_A2

X_D28

X_A19

X_A13

X_A6

FLASH1_CE

FLASH0_CE

X_D6

FLASH_BYTE_NOT

X_A14

3.3V

X_OE_NOT

X_A10

X_A5

X_D29

X_A3

X_A9

FLASH_BYTE_NOT

X_D25

X_RESET_NOT

U5

AM29LV400/SO48

37

29313335384042443032343639414345

15

2524232221201918

87654321

4817

4728121126

169

VCC

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14

DQ15/A-1

RY/BY

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17

BYTEOERSTWECE

NCNC

X_A3

X_A19

X_D8

X_A4

FLASH0_CE

X_A[2..21]

X_A12

X_D30

X_D3

X_D7

X_D1

X_D5

X_D11

X_A15

X_D23X_A8

X_D21

X_A12

X_A16

X_D26

X_D12

X_A11

X_A18

X_D20

X_A13

X_A7X_D4

X_A8

R2910K

X_D[0:31]

X_D9

X_D27

X_A20 FLASH1_RDY

X_A17

X_A5

X_A14

X_RESET_NOT

X_D14

X_A7

X_A9

X_A21

U4

AM29LV400/SO48

37

29313335384042443032343639414345

15

2524232221201918

87654321

4817

4728121126

169

VCC

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14

DQ15/A-1

RY/BY


BYTEOERSTWECE

NCNC

X_WE_NOT

X_D24

X_A17

X_D10

X_A15

X_A18

C14

100nF

3.3V

X_OE_NOT

X_A6

X_A11

X_WE_NOT

X_A4

FLASH1_CE

X_D15

R2810K

3.3V

X_D17X_D0 X_A2

X_A21

X_D2 X_D18

X_A16

C13

100nFFLASH CEPULL UP

FLASH

EV

M 5510

SRAMHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות


Data

Address

MB Control

DB

Control

4MbFlash4Mb

SRAM

MAIN PROPERTIES

4 X 4Mb Alliance Semiconductor Async SRAM.

Conclusion:

Large, Fast, available.

CS for each IC controlled by FPGA only.

4MbSRAM4Mb

SRAM

10nSec Access Time.

IC Arrangement 16*256M .

Why asynchronous ?

TI’s daughter board specification.


3.3V

X_D15

X_D27

3.3V

X_D4

X_D21

3.3V

X_A6

X_D30

C70

100nF

X_WE_NOT

X_D8

3.3V3.3V

X_D12

X_D26

C62

10uF

X_A15X_D28

X_BE3_NOT

X_D23X_A8

X_A16

X_A6

X_D24

X_D18

X_D1

X_A18

X_A2

X_A11

X_A2

X_A9

X_D19

X_D2

X_A[2:19]

X_D4

X_OE_NOT

X_BE2_NOT

X_D27

X_A3

X_A[2:19]

X_A19

X_A12

X_D8

X_D13

X_A8

X_A5

U16

AS7C34098-10TC

6

12

17

34

3940

41

78910131415

12345

18192021222324252627424344

162930313235363738

1133

CS

GND

WE

GND

LBUB

OE

I/O1I/O2I/O3I/O4I/O5I/O6I/O7


I/O8I/O9


VCCVCC

X_D12

X_A13

X_OE_NOT

X_A14

X_D14

X_D0

X_D3

X_A15

X_D31

X_D22

SRAM1_CS

X_A7

X_D11

U17

AS7C34098-10TC

6

12

17

34

3940

41

78910131415

12345

18192021222324252627424344

162930313235363738

1133

CS

GND

WE

GND

LBUB

OE



I/O8I/O9


VCCVCC

X_A[2:19]

X_A13

SRAM0_CS

X_D1

X_A12X_D9

X_D20

X_A10

C66

100nF

X_A17

X_A11X_A10

X_D19

X_D[0:31]

X_BE0_NOT

X_D0

X_A14X_D13

X_D11

X_A15

X_A18

X_D25

X_D16

X_D10

X_D7

X_A9

X_A4

R6810K

X_D28

X_D9

SRAM2_CS

X_A3

X_BE0_NOT

X_A5

X_A14

X_D17

X_A16

X_WE_NOT

X_D16

X_A7

X_A3

X_A8X_D5

X_D3

X_D63.3V

C67

100nF

3.3V

X_BE1_NOT

X_A17X_D14

SRAM0_CS

X_A[2:19]

X_A4

X_D29X_D29

R6910K

X_D20

X_A19

X_A11

X_D31

X_D2

C65

10uF

X_A8X_D7X_A9

R6610K

X_BE3_NOT

X_A12

X_A18

X_D25

R6710K

X_A4

X_A6X_A5

X_D10

X_D17

X_A10

X_A7

U15

AS7C34098-10TC

6

12

17

34

3940

41

78910131415

12345

18192021222324252627424344

162930313235363738

1133

CS

GND

WE

GND

LBUB

OE



I/O8I/O9


VCCVCC

SRAM1_CS

X_A4

X_A16

X_A5

X_WE_NOT

X_D22

X_A19

X_A9

X_A2

SRAM3_CS

C68

100nF

X_D5

X_A16

X_A19

C63

100nF

X_A12

X_OE_NOT

SRAM2_CS

X_D18

X_D15

X_A13

X_A3

X_A14X_A15

X_BE1_NOT

X_A13

X_WE_NOT

X_A10

U18

AS7C34098-10TC

6

12

17

34

3940

41

78910131415

12345

18192021222324252627424344

162930313235363738

1133

CS

GND

WE

GND

LBUB

OE



I/O8I/O9


VCCVCC

SRAM CS PULL UP

X_D21

X_D23

X_A18

X_A11

X_D26

X_A6

3.3V

X_D6

X_D[0:31]

X_BE2_NOT

X_D30

C64

100nF

X_A17

X_D24

C71

100nF

X_A17

SRAM3_CS

X_A7

X_OE_NOT

X_A2

C69

100nF

SRAM

RS232 ChannelsHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Control Unit )Altera( MAIN PROPERTIES

2 configurable standard RS232 serial channels.

TI TL16C550CPT single UART’s with 16 Byte FIFO.

MAX3238 RS232 Transceivers.

Standard DB9 connectors.

Memory Mapped.

Asynchronous operation, using interrupts.

UART

RS232 Transceiver

DB9addr

data

Ctrl

UART

RS232 Transceiver

DB9

addr

data

Ctrl

1.8432Mhz Oscillator.

RS232 Channels (cont.)High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Control Unit )Altera(

Conclusion:

Industry standard UART.

Reliable & Available Transceiver.

Standard RS232 Connectors.

UART

RS232 Transceiver

DB9addr

data

Ctrl

UART

RS232 Transceiver

DB9

addr

data

Ctrl

UART: IC or ALTERA CORE ?

Reduce FPGA resources.

Academic - more HW substance.


U13

TL16C550C/FP

7

8

42

12

14

15

5

282726

19

2024

38

40

39

35

41

16

17

910

11

22

33

30

32

2923

4344454647

234

34

31

SDI

SDO

VCC

BAUDOUT

XIN

XOUT

RCLK

A0A1A2

RD1

RD2ADS

CTS

DCD

DSR

MR

RI

W R1

W R2

CS0CS1

CS2

DDIS

DTR

INTRPT

RTS

RXRDYTXRDY

D0D1D2D3D4D5D6D7

OUT1

OUT2

3.3V

R641K

R6210K

P_RI2

C54100nF

U_D5

U_D3

3.3V

P_DTR1

U_A2

P_CTS1

C490.22uF

U_D1

P_TXD2

U_D6

R5510K

P_DSR1

U_D2

U_D0

C560.22uF

U12

MAX3238/SO

26

16

15

2825

13

274

1314

2423221917

119821

2018

5671012

VCC

R1OUTB

INVALID

C1+C1-C2+C2-V+V-

FORCEONFORCEOFF

T1INT2INT3INT4INT5IN

R3INR2INR1INR1OUT

R2OUTR3OUT

T1OUTT2OUTT3OUTT4OUTT5OUT

U14

MAX3238/SO

26

16

15

2825

13

274

1314

2423221917

119821

2018

5671012

VCC

R1OUTB

INVALID

C1+C1-C2+C2-V+V-

FORCEONFORCEOFF

T1INT2INT3INT4INT5IN

R3INR2INR1INR1OUT

R2OUTR3OUT

T1OUTT2OUTT3OUTT4OUTT5OUT

U_RD

U_D7

C59100nF

U2_CS

3.3V

R631K

P_DCD1

U2_CS

U_A[0..2]

U_D1

U_D4

UART CS PULL UP

U_RD

U1_CS

P_RXD2

U_W R

U1_INT

U_D5

3.3V

C55100nF

3.3V

RS2_FRC_OFF

P_RTS2

U11

TL16C550C/FP

7

8

42

12

14

15

5

282726

19

2024

38

40

39

35

41

16

17

910

11

22

33

30

32

2923

4344454647

234

34

31

SDI

SDO

VCC

BAUDOUT

XIN

XOUT

RCLK

A0A1A2

RD1

RD2ADS

CTS

DCD

DSR

MR

RI

W R1

W R2

CS0CS1

CS2

DDIS

DTR

INTRPT

RTS

RXRDYTXRDY

D0D1D2D3D4D5D6D7

OUT1

OUT2

P_RTS1

P_DCD2

U_W R

U_D2

C600.22uF

R581K

P_RXD1

C52100nF

U_CLK

Y2

OSC-1.8432MHz/SM

43 1

VCCOUT EN

U_RST

C510.22uF

R591K

U_D7

RS1_INV

RS2_INV

3.3V

U_D3

U_D[0..7]

U_D6

RS2_FRC_ON

C530.22uF

3.3VU_D4

P_TXD1

P_DSR2

U_A0

U_A1

C570.22uF

U_D0

P_RI1

3.3V

U_D[0..7]

U_A1

R601K

C500.22uF

R651K

R5410K

3.3V

U_A0

C61100nF

C580.22uF

RS1_FRC_OFF

U1_CS

R5610K

RS1_FRC_ONU_RST

R571K

U_A[0..2]

P_DTR2

U_A2

P_CTS2

R6110K

U2_INT

R5310K

UART

CLK 1.8432MHz

RS232 TRANSCEIVER

UART CS PUPs

GPIOHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

MAIN PROPERTIES 3 X 16 bit wide buses.

10 X 2 connectors. Suitable for logic analyzer 100KΩ Termination Adapter.

Busses are buffered for FPGA protection & for Current driving.

Transceivers direction controlled by FPGA.


Header 10 X 2Header

10 X 2Header 10 X 2

40MHz/1.8432MHz clock signals.

UART data bus connected to a gpio bus.

1 bus could be realized as open/gnd or open/vcc.

Bi-directional TI’s SN74LVTH16245 bus transceivers )Standard & Availability(.


GPC_1DIR

U_D2

3.3V

GPB1

GPB_1DIR

P_GPB11

P_GPB6

R5 0

GPB5GPB6

R8 10K

P_GPB14

GPA2

C3100nF

R210K

P_GPA6

P_GPB10GPB11

P_GPB6

P_GPB13

P_GPA1

P_GPA14

U_D5

GPA13

GPB_2OE

R12 10K

P_GPA4

GPC7

P_GPB12

GPA_1OE

GPC_2DIR

U_D1

GPB8

P_GPB[0..15]

U3

74LVTH16245/SO

2356891112

4746444341403837

3635333230292726

1314161719202223

124

4825

718 31

42

1B11B21B31B41B51B61B71B8

1A11A21A31A41A51A61A71A8

2A12A22A32A42A52A62A72A8

2B12B22B32B42B52B62B72B8

1DIR2DIR

1OE2OE

VCCVCC VCC

VCC

3.3V

GPA_2DIR

GPB13

P_GPB8

U_D4

P_GPB3

GPA8

R11 10K

NA

GPB4

U_D0

U_D6

P_GPA3

GPC[0..7]

R240

C1100nF

GPA15

P_UD[0..7]

P_GPB9

P_GPA12GPA12

P_UD7

GPC5

R14 10K

GPB3

P_GPB15

GPA9

P_UD4

P_GPA7

R7 10K

C7100nF

GPB15

P_GPB5

P_GPB5

P_GPB13

P_GPA0

P_GPB7

P_GPB14GPA14

3.3V

P_GPB2P_GPC3

GPA4

GPB9

P_GPC0

P_GPC2

GPB0

P_GPC4

GPA_1DIR

P_GPB10

P_GPA15

R310K

P_GPB4

R410K

U1

74LVTH16245/SO

2356891112

4746444341403837

3635333230292726

1314161719202223

124

4825

718 31

42

1B11B21B31B41B51B61B71B8

1A11A21A31A41A51A61A71A8

2A12A22A32A42A52A62A72A8

2B12B22B32B42B52B62B72B8

1DIR2DIR

1OE2OE

VCCVCC VCC

VCC

GPB_1OE

P_GPB1

P_GPA9

GPB7

GPC4

P_GPB11

NA

P_GPA[0..15]

P_GPB9

R21 10K

P_UD1

P_GPA11

GPA6

3.3V

P_GPB7

GPA11

3.3V

C4100nF

U_D3

P_GPB15

P_GPC1

R19 10K

3.3V

P_UD3

GPC_2OE

R2210K

3.3V

GPA7

U2

74LVTH16245/SO

2356891112

4746444341403837

3635333230292726

1314161719202223

124

4825

718 31

42

1B11B21B31B41B51B61B71B8

1A11A21A31A41A51A61A71A8

2A12A22A32A42A52A62A72A8

2B12B22B32B42B52B62B72B8

1DIR2DIR

1OE2OE

VCCVCC VCC

VCC

C6100nF

R17 10K

GPB_2DIR

GPB10

GPA[0..15]

GPB12

P_GPB3

R2310K

3.3V

R10 10K

3.3V

R6 10K

R15 10K

R110K

C11100nF

C12100nF

NA

P_GPC[0..7]

P_GPB1

P_GPC5GPC6

P_GPA13

GPC_1OE

P_GPA2

P_GPC6

R9 10K

GPA10

R13 10K

P_UD5

C9100nF

NA

P_GPB0GPC1

GPC3

P_GPC7

GPA5 P_GPA5

R16 10K

C5100nF

P_GPB0

P_GPA8

GPB[0..15]

P_GPB[0..15]

GPA1

GPC2

U_D[0..7]

GPB14

P_GPB8

U_D7

C8100nF

GPA0

GPA_2OE

GPA3

P_GPB4

P_UD2

P_GPB12

P_UD0

R18 10K

3.3V

GPB2

GPC0

P_GPA10

C2100nF

C10100nF

R20 10K

P_GPB2

P_UD6

BUFFERS

EV

M 5510

McBSPHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות


MAIN PROPERTIES

3 McBSP channels

Channel 2 is connected to the FPGA through spare pines in the McBSP connector.

Use of Channel 2 requires alteration of the MB.

Full duplex serial communication.

Double buffered.

Header 4 X 2 Header

4 X 2 Header 4 X 2

Main purpose – connecting DSP’s for parallel operation.

FPGAHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Altera’s EPF10K100ARC-1 FPGA.

189 IO pins, all used.

RQFP 240 pin package.

Programmed by EPC2 E2PROM.

Size 1,200,000 bits.

EPC2TC32 size : 1,695,680 bits.

JTAG interface for EPC2 programming.


X_SP5

RS1_INV

RS

1_IN

V

TCK

GPC_2DIR

X_D

28

3.3V

PIN 189

X_A

7

X_CNTL1

3.3V

X_D

27

R441K

3.3V

GPA

0

X_S

P18

X_A

20

A_LED2

GPB_1OE

C16100nF

A_L

ED

3

X_A

13

GPA

3

U_W

R

U_WRGP

C3

X_T

OU

T1

U_D

1D4

LED

FLASH1_RDY

C24 100nF

X_OE_NOTX

_D1

A_CLK

X_A

8

X_ARDY

X_INT1_NOT

GP

B4

GP

B_2

OE

PIN 224

X_TIN0

A_T

MS

U_A

2

GP

B12

X_BE3_NOTX_BE2_NOT

X_TOUT1

PIN 16

X_A

15

GP

B15

R38150

C31 10uF

3.3V

GP

B14

U2_INT

X_O

E_N

OT

C38 100nF

A_C

ON

FIG

X_B

E0_

NO

T

X_D[0..31]

GP

B0

FLA

SH

_BY

TE_N

OT

X_SP11

X_S

P16

SRAM3_CS

RS

2_FR

C_O

N

C21 100nF

C27 100nF

PIN 5PIN 122

X_D[0..31]

X_SP1

X_S

P8

X_D

20

U_D

7

X_B

E1_

NO

T

A_LED4

GPB[0..15]

RS

2_FR

C_O

FF

X_D

15

X_D

25

A_LED1

X_CLKOUT

C36 100nF

U1_CS

TDI

X_S

P2

X_D

2

X_S

P10

U_R

ST

X_I

NT0

_NO

T

X_S

P1

GPA_2OE

GP

C_1

OE

X_D

17

GPA

10

X_D

16

SR

AM

0_C

S

PIN 37

forMcBSP2use

A_L

ED

4

X_C

NTL

0

GPA

8

A_L

ED

2

X_S

TAT0

U1_INT

X_SP7

X_S

P9

X_R

E_N

OT

X_INT0_NOT

R421K

U_D

3

GP

C_2

OE

SR

AM

3_C

S

X_INT3_NOT

GP

B9

X_D

24

X_D

19

X_SP3

X_SP18

GPA

_1O

E

R311K

U2_

CS

R39150

GPA

13

GP

C_2

DIR

X_B

E2_

NO

T

X_D

23

X_D

31

R37150

GPB_2OE

GPA

_2D

IR

X_SP8

PIN 205

R351K

X_WE_NOT

X_C

E2_

NO

T

RS1_FRC_ON

X_A

17

X_D

11

GPA

2

U_D

4

X_A

16

C32 100nF

X_A

14

X_D

0

PIN 77

FLASH_BYTE_NOT

R451K

X_A

6

X_SP16

RS

2_IN

V

GPA

11

U6

EP

F10K

100A

RC

/PFP

240

6789121314151718 19 2021 24 25 2829 30313334 35

36

38 4039 43414445

46

4849505153 54 55 56 61 62 63 64 65 66 67 68 70 71 72 73 74 75 76 78 79 80 81 82 8384 86 87 88 94 95 97 98 99 100

101

102

194

146

206

207

208

214

215

217

218

219

220

221

222

223

225

226

227

228

177

3

4

26 2390 92

210

212

180

91 211

179

1

236

238

121

124

123

58 59

178

108

103

105

107

106

109

111

110

120

119

118

117

116

115

114

113

196

195

193

192

191

190

188

187

186

185

184

154

183

182

181

175

174

173

172

171

169

168

167

166

164

163

162

161

159

158

157

156

153

152

151

149

148

147

144

139

133

132

131

129

128

127

126

198

201

199

200

202

203

204

229

230

231

233

234

235

237

11239

240

209

213

51627374757778996

112122130140150160170189205224

260143

142

141

138

137

136

134

XS

P20

XS

P19

XS

P18

XS

P17

XS

P16

XS

P15

XS

P14

XS

P13

XS

P12

XS

P11

XTO

UT0

XTI

N0

XIN

T0

XIN

T2

XTO

UT1

XTI

N1

XIN

T1

XIA

CK

XS

P10

XS

P9

XS

P8

XD

BIN

T

XR

ST

XS

P7

XC

NTL

1X

CN

TL0

XS

TAT1

XS

TAT0

XIN

T3

XS

P6

XC

E2

XS

P5

XS

P4

XS

P3

XS

P2

XS

P1

GP

B0

GP

B1

GP

B2

GP

B3

GP

B4

GP

B5

GP

B6

GP

B7

GP

B8

GP

B9

GP

B10

GP

B11

GP

B12

GP

B13

GP

B14

GP

B15

GP

B1O

EG

PB

1DIR

GP

B2O

EG

PB

2DIR

U2C

SU

1CS

UW

RU

RD

UD

7U

D6

UD

5U

D4

UD

3U

D2

UD

1U

D0

UA

2U

A1

UA

0

U2I

NT

D2 A5

GPA

4G

PA5

GPA

6

GPA

9G

PA10

GPA

11G

PA12

GPA

13G

PA14

GPA

15G

PA1O

EG

PA1D

IRG

PA2O

EG

PA2D

IR

GP

C0

GP

C1

TDI

CE

O

TDO

I/O/IN

IT_D

ON

E

I/O/R

DY

/BS

Y

RS

2IN

VR

S1I

NV

F0R

DY

F1R

DY

DAT

A0

XC

LKC

LK

DC

LKTCK

GP

C1O

E

GP

C2O

E

CO

NFI

G

MS

EL0

MS

EL1

TMS

TRS

T

CE

FRC

ON

1

U1I

NT

UR

ST

FRC

OFF

2FR

CO

N2

FRC

OFF

1

S1C

SS

0CS

XW

EX

RE

XR

DY

XO

E

XC

E1

XS

P0

S3C

SS

2CS D0

D1

D3

D4

D5

D6

D7

D8

D9

D10

D11

BE

0

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

BE

1B

E2

BE

3 A2

A3

A4

A6

A10

A15

A16

A17

A18

A19

A20

A21

F0C

E

GPA

0

FBY

TEF1

CE

GPA

1G

PA2

GPA

3

GP

C2

GP

C3

GP

C4

GP

C5

GP

C6

GP

C7

GP

C1D

IR

I/O/C

LKU

SR

GP

C2D

IR

I/O/C

S

GPA

7G

PA8

VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC C

ON

F_D

ON

ES

TATU

S

A7

A8

A9

A11

A12

A13

A14

3.3V

GPA

14

GP

B5

X_A

2

ALTERA EPF10K100ARC

X_S

P17

U_D[0..7]

3.3V

GP

C4

X_DBINT_NOT

A_DATA0

X_I

NT3

_NO

T

X_S

P4

C37 100nF

U7

EPC2

312

107

27

3

13

15

16

17

23

2528

32

DATADCLK

CSOE

VC

C

VCCSEL

TDI

CASC

INIT_CONF

VPPSEL

VP

P

TMSTDO

TCKTDO

A_C

ON

F_D

ON

E

X_T

IN1

U_A

1

C35 100nF

GPC_1DIR

D2LED

X_BE1_NOT

C39 100nF

PIN 27

X_D

21

X_BE0_NOT X_A

RD

Y

U2_

INT

GPA[0..15]

X_A

19

PIN 47

PIN 112

A_T

RS

T

X_CLKOUT_R

X_C

LKO

UT_

R

X_A[2..21]

C23 100nF

C40 100nF

U1_

CS

GP

B_2

DIR

A_L

ED

1

GP

B8

X_CNTL0

GPA_2DIR

X_TIN1

GPA

15

R461K

X_A

12

SRAM1_CS

D_CLK

GPA

6

GPA

12

3.3V

X_CE1_NOT

SR

AM

2_C

S

X_STAT0

R411K

Y1

OSC-40MHz/SM

43 1

VCCOUT EN

X_S

P20

X_A

11

U_D

5

3.3V

X_S

P5

C34 10uF

R40150

3.3V

GPA

9

GP

C_1

DIR

PIN 96

A_CONF_DONE

3.3V

X_A

4

FLA

SH

1_C

E

X_SP10

X_SP14

A_T

CK

RS2_FRC_OFF

A_LED3

PIN 140

X_D

18

X_D

14

GP

B_1

DIR

X_S

P12

U_RD

D_C

LK

GP

B11

GP

B2

GPC_2OE

C17100nF

R34

0

X_D

6

X_A

3

RS2_INV

PIN 130

TMS

R471K

GP

B7

GP

C7

C22 100nF

A_D

ATA

0

GP

B13

X_S

P0

X_C

E1_

NO

T

X_STAT1

GPB_2DIR

3.3V

U1_

INT

X_S

TAT1

X_SP4

GPB_1DIR

U_D

6

SR

AM

1_C

S

U_RST

X_SP6

X_S

P3

C19 100nF

GPA_1OE

X_SP20

X_S

P11

PIN 150

3.3V

X_CE2_NOT

X_SP15

X_INT2_NOT

X_D

BIN

T_N

OT

X_D

4

R301K

X_A

18

X_A

9

A_C

LK

R321K

U_D

0

GP

B_1

OE

X_TOUT0

FLASH0_CE

C15100nF

X_A

21

X_IACK_NOT

A_STATUS

RS1_FRC_OFF

GPA[0..15]

X_A[2..21]

X_SP12

X_D

5X

_SP

19

X_SP17

C18 100nF

FLASH1_CE

U_A[0..2]

X_D

7

X_D

13

X_RE_NOT

X_S

P7

X_D

3

C30 100nF

GPC[0..7]

A_RST_NOT

U2_CS

X_A

5

R36

0

X_I

AC

K_N

OT

X_T

IN0

GPA

4

FLA

SH

0_R

DY

X_D

9X_SP0

GP

C2

X_W

E_N

OT

C33 100nF

X_A

10

X_S

P15

C28 10uF

GPA

7

A_R

ST_

NO

T

SRAM0_CS

A_S

TATU

S

GPB[0..15]

GP

B6

C26 100nF

SRAM2_CS

FLA

SH

0_C

E

X_D

29

GPA

5PIN 160

3.3V

R431K

A_T

DI

X_D

12X

_IN

T2_N

OT

X_I

NT1

_NO

T

D1LED

X_SP19

RS

1_FR

C_O

FF

GP

C5

X_B

E3_

NO

T

FLASH0_RDY

A_CONFIG

GPA

_2O

E

FLA

SH

1_R

DY

GP

C6

GP

B10

X_D

30

PIN 89

GPC_1OE

U_R

D

R331K

U_A

0

X_D

22

U_D[0..7]

X_SP9

X_S

P6

C20 100nF

X_D

8

C25 10uF

PIN 57

X_SP2

X_S

P13

GPA_1DIR

X_C

NTL

1

X_D

10

3.3V

GP

C0

GP

C1

X_T

OU

T0X_SP13

PIN 170

GP

B1

U_D

2

RS2_FRC_ON

GPA

_1D

IR

GP

B3

X_D

26

D3LED

X_S

P14

C29 100nF

U_A[0..2]

RS

1_FR

C_O

N

GPA

1

GPC[0..7]

ALTERA EPF10K100ARC

CLK 1.8432MHz

EPC2

LEDS

IndicatorsInterface

FPGA Block DiagramHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Memory Interface

SpareMB Signals

Interface

UART Interface

addr

data

ctrl

data

ctrl

addr

GPIOInterface

ctrl

MainControl

Power SupplyHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

3.3V

5V_SUPPLY

D7

LED

+ C41

22uF

R49150

C46

100nF

place 10nF cap& zenner close

C45

10nFD6

DIODE

D5

ZENER

+C42

22uF

U8 LM1085

3 2

1

IN OUT

GND

C44

100nF

C43

10nF

J10

CONN PWR 4-H

1234

4 pin standard PS connector

5v External Power Supply

Power Indicator

Reverse Power protect

OVP

3.3v Layer Power Regulator

6A Trace

System ResetHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

res connected - 20msres not connected - 100ms

3.3V

R500

X_RESET_NOT

normally closed

3.3V

R5110K

reset delay:

3.3V

C48100nF

A_RST_NOTU10

MAX821/SOT143

23

4

RSTSRT

VCC

R5210K

SW1

SW PUSHBUTTON-SPDT

3.3V

U9A

SN74LVC08A/PW

1

23

14

C47100nF

Active Low Reset

Manual Reset

MB Reset

Set Delay

To FPGA

MAX821 Voltage Monitor

Design IssuesHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Timing:

DB System Clock 40MHz.

MB Supplies configurable Clock 20MHz ÷ 160MHz.

DSP DB CS Delay ~23nSec )before simulation(.

DSP DB Memory Addr/Data ~9nSec

Fanout :

Borderline )capacity( for most memory signals. Single Buffer drives 7 outputs.

Layout GuidelinesHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Place Memory IC close to Memory connector

Information Flow

Altera’s Pins same as connected IC’s pins as possible

Lines as simple as possible

Critical lines : Clocks

Easy Access to Connectors/Switch/Leds

By The Numbers: 6 Layers

430 Nets~1200 Pads

Size: 191mm X 76.2mm

LayoutHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Flash

EMIF Connector

Peripheral Connector

S R A M

McBSP Headers

BU

FF

ER

S

BU

FF

ERFPGA

FLASH

UA

RT

S

OVP

Reverse

REGULATOR

EPC2

RS

232

JTAG Header

RESET

Power Connector

On The AgendaHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Final Preparation for production.

Finish FPGA Code & Simulation.

Learning the Code Composer environment.

Writing test programs.

Electrical wiring test of the board after production.

Components assembly & Functional Debug.

Parallel Operation of 3 DSP’s.

The End


Performed by: Roi Sherman Eyal Wilamowski Instructor: Mr. Michael Itzkovich

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Transcript of Performed by: Roi Sherman Eyal Wilamowski Instructor: Mr. Michael Itzkovich