Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for...
-
Upload
john-manning -
Category
Documents
-
view
214 -
download
0
description
Transcript of Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for...
![Page 1: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/1.jpg)
Penn ESE370 Fall 2012 -- Townley & DeHon
ESE370:Circuit-Level
Modeling, Design, and Optimization for Digital Systems
Day 13: October 3, 2012Layout and Area
![Page 2: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/2.jpg)
2
Today
• Coping with Variation (from last time)• Layout
– Transistors– Gates
• Design rules• Standard cells
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 3: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/3.jpg)
Penn ESE370 Fall2012 -- DeHon3
Variation• Margin for expected variation• Must assume Vth can be any value in range
– Speed assume Vth slowest value
Pro
babi
lity
Dis
tribu
tion
VTH
Ion,min=Ion(Vth,max) Id,sat (Vgs-Vth)2
![Page 4: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/4.jpg)
Variation
• See a range of parameters– L: Lmin – Lmax
– Vth: Vth,min – Vth,max
• Validate design at extremes– Work for both Vth,min and Vth,max ?– Design for worst-case scenario
Penn ESE370 Fall2012 -- DeHon4
![Page 5: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/5.jpg)
Margining
• Also margin for– Temperature– Voltage– Aging: end-of-life
Penn ESE370 Fall2012 -- DeHon5
![Page 6: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/6.jpg)
Process Corners• Many effects independent• Many parameters• With N parameters,
– Look only at extreme ends (low, high)– How many cases?
• Try to identify the {worst,best} set of parameters– Slow corner of design space, fast corner
• Use corners to bracket behavior
Penn ESE370 Fall2012 -- DeHon6
![Page 7: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/7.jpg)
Simple Corner Example
Penn ESE370 Fall2012 -- DeHon7
Vthp
Vthn150mV
150mV
350mV
350mV
What happens at various corners?
![Page 8: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/8.jpg)
Process Corners• Many effects independent• Many parameters• Try to identify the {worst,best} set of
parameters– E.g. Lump together things that make slow
• Vthn, Vthp, temperature, Voltage• Try to reduce number of unique corners
– Slow corner of design space• Use corners to bracket behavior
Penn ESE370 Fall2012 -- DeHon8
![Page 9: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/9.jpg)
Range of Behavior
• Still get range of performances• Any way to exploit the fact some are faster?
Penn ESE370 Fall2012 -- DeHon9
Pro
babi
lity
Dis
tribu
tion
Delay
![Page 10: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/10.jpg)
Penn ESE370 Fall2012 -- DeHon10
Speed BinningP
roba
bilit
y D
istri
butio
n
Delay
DiscardSellPremium
Sellnominal
Sellcheap
![Page 11: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/11.jpg)
Layout
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 12: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/12.jpg)
12
Transistor
Side viewPerspective view
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 13: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/13.jpg)
13
Layout
• Sizing & positioning of transistors
• Designer controls W,L
• tox fixed for process– Sometimes
thick/thin oxide “flavors”
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 14: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/14.jpg)
14
NMOS Geometry
Top view Perspective view
L
W
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 15: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/15.jpg)
15
NMOS Geometry
Top view
L
W
• Color scheme– Red: gate– Green: source and drain
areas (n type diffusion)S DG
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 16: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/16.jpg)
16
tox
• Transistors built by depositing materials– Constant rate of deposition (nm/min)– Time controls tox
• Oxides across entire chip deposited at same time– Same time interval– thickness is (roughly) constant– Process engineer sets value to:
• Assure yield• What does tox control?
– Field strength Vth, current– Achieve Performance, minimize leakage
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 17: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/17.jpg)
17
NMOS vs PMOS
Rabaey text, Fig 2.1Penn ESE370 Fall 2012 -- Townley & DeHon
• Mostly talked about NMOS so far– PMOS: “opposite” in some sense– NMOS built on p substrate, PMOS built on n
substrate– Name refers to bias/carriers when channel is
inverted
![Page 18: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/18.jpg)
18
PMOS Geometry
n well
L
W
• Color scheme– Red: gate– Orange: source and drain
areas (p type)– Green: n well
• NMOS built on p wafer– Must add n material to
build PMOS
S DG
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 19: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/19.jpg)
19
Body Contact
• “Fourth terminal”• Needed to set
voltage around device– PMOS: Vb = Vdd
– NMOS: Vb = GND• At right: PMOS
(orange) with body contact (dark green)
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 20: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/20.jpg)
Penn ESE370 Fall 2012 -- Townley & DeHon
Rotate All butPMOS Transistor90 degrees
![Page 21: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/21.jpg)
21
Interconnect• How to connect transistors
– Different layers of metal Intermediate layers
• “Contact” - metal to transistor• “Via” - metal to metal
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 22: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/22.jpg)
22
Interconnect• How to connect transistors
– Different layers of metal Intermediate layers
• “Contact” - metal to transistor• “Via” - metal to metal
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 23: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/23.jpg)
23
Interconnect Cross Section
ITRS 2007Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 24: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/24.jpg)
24
Masks
• Define areas want to see in layer– Think of “stencil” for material deposition
• Use photoresist (PR) to form the “stencil”– Expose PR through mask– PR dissolves in exposed area– Material is deposited
• Only “sticks” in area w/ dissolved PR
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 25: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/25.jpg)
25
Masking Process
• Goal: draw a shape on the substrate– Simplest example: draw a rectangle
Silicon wafer
Mask
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 26: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/26.jpg)
26
Masking Process
• First: deposit photoresist
photoresist
Mask
Silicon wafer
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 27: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/27.jpg)
27
Masking Process
• Expose through mask– UV light
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 28: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/28.jpg)
28
Masking Process• Remove mask and
develop PR– Exposed area
dissolves– This is “positive
photoresist”
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 29: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/29.jpg)
29
Masking Process• Deposit metal through PR
window– Then dissolve remaining PR
• Why not just use mask?– Masks are expensive– Shine light through mask to
etch PR– Can reuse mask
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 30: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/30.jpg)
30
Logic Gates
• How to build complete inverter?– Connect NMOS,
PMOS using metal
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 31: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/31.jpg)
31
Inverter Layout Example
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 32: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/32.jpg)
32
Inverter Layout Example
• Start with PMOS, NMOS transistors
• Space for interconnect
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 33: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/33.jpg)
33
Inverter Layout Example
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 34: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/34.jpg)
34
Inverter Layout Example
• Add body contacts
• Connect gates of transistors
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 35: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/35.jpg)
35
Inverter Layout Example
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 36: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/36.jpg)
36
Inverter Layout Example
• Add contacts to source, drain, gate, body
• Connect using metal (blue)
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 37: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/37.jpg)
37
Design Rules• Why not adjacent
transistors?– Plenty of empty
space– If area is money,
pack in as much as possible
• Recall: processing imprecise– Margin of error for
process variation
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 38: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/38.jpg)
38
Design Rules• Contract between process engineer &
designer– Minimum width/spacing– Can be (often are) process specific
• Lambda rules: scalable design rules– In terms of = 0.5 Lmin (Ldrawn)– Can migrate designs from similar process– Limited scope: 45nm process != 1m
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 39: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/39.jpg)
Design Rules: Some Examples
Penn ESE370 Fall 2012 -- Townley & DeHon
2
66
3
2
2
1.5
n doping
p doping
gate
contact
metal 1
metal 2
via
Legend
![Page 40: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/40.jpg)
40
Layout Revisited
• How to “decode” circuit from layout?
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 41: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/41.jpg)
Penn ESE370 Fall2010 -- DeHon41
Layout to Circuit
• 1. Identify transistors
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 42: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/42.jpg)
42
Layout to Circuit
• 2. Add wires
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 43: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/43.jpg)
43
Layout to Circuit
• 2. Add wires
Penn ESE370 Fall 2010 -- Townley (DeHon)Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 44: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/44.jpg)
44
Layout to Circuit
• 2. Add wires
Penn ESE370 Fall 2010 -- Townley (DeHon)Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 45: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/45.jpg)
45
Layout to Circuit
• 2. Add wires
Penn ESE370 Fall 2010 -- Townley (DeHon)Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 46: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/46.jpg)
46
Layout #2 (practice)
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 47: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/47.jpg)
47
Layout #2 (practice)
• How many transistors?– PMOS?– NMOS?
• How connected?– PMOS, NMOS?
• Inputs connected?• Outputs?• What is it?
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 48: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/48.jpg)
48
Standard Cells• Lay out gates so that heights match
– Rows of adjacent cells– Standardized sizes
• Motivation: automated place and route– EDA tools convert HDL to layout
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 49: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/49.jpg)
Penn ESE370 Fall 2012 -- Townley & DeHon
Standard Cell Area
inv nand3
All cellsuniformheight
Width ofchanneldeterminedby routing
Cell area
Identify the full custom and standard cell regions on 386DX diehttp://microscope.fsu.edu/chipshots/intel/386dxlarge.html
![Page 50: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/50.jpg)
Admin
• HW4 due Thursday• Lecture on Friday• Review on Sunday at 6pm• Exam on Monday
– No class at noon that day
Penn ESE370 Fall 2012 -- Townley & DeHon
![Page 51: Penn ESE370 Fall 2012 -- Townley DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.](https://reader035.fdocuments.net/reader035/viewer/2022070607/5a4d1b8a7f8b9ab0599be3e0/html5/thumbnails/51.jpg)
51
Big Idea
• Layouts are physical realization of circuit– Geometry tradeoff
• Can decrease spacing at the cost of yield• Design rules
• Can go from circuit to layout or layout to circuit by inspection
Penn ESE370 Fall 2012 -- Townley & DeHon