ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring &...

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Job Number: 1278; Posted: Mar 23 2001 ELECTRICAL DESIGN ENGINEER Your Mission: Design and develop digital and analog circuitry for hi-volume electronic systems. What You'll Do: Define and develop specification and architecture through schematic capture, PCB layout and software / hardware integration; Collaborate with engineering team to manage end-to-end system performance requirements; Optimize cost / size for volume production. Your Skills: Experience with Microprocessor-based system design; Extensive knowledge of digital and analog circuit design; FPGA / ASIC design using VHDL; Familiarity with low-power systems and high density surface mount packaging; Prior experience taking a design through high volume production; Experience with PC-based CAD tools; Hands-on debugging and prototyping; Software experience a plus; Superior communication and interpersonal skills. Your Nature: Creative, hands-on problem solver; Precision minded approach and eye for detail; Independent proactive thinker; Performance enthusiast with an appreciation for elegant design; Very focused on results. Your Track Record: BS / MS in electrical engineering or equivalent experience; 3+ years experience with analog and digital design. www.pcbjn.com

Transcript of ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring &...

Page 1: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

Job Number: 1278; Posted: Mar 23 2001

ELECTRICAL DESIGN ENGINEER

Your Mission: Design and develop digital and analog circuitry for hi-volume electronic systems.

What You'll Do: Define and develop specification and architecture through schematic capture, PCB layout and software / hardware integration; Collaborate with engineering team to manage end-to-end system performance requirements; Optimize cost / size for volume production.

Your Skills: Experience with Microprocessor-based system design; Extensive knowledge of digital and analog circuit design; FPGA / ASIC design using VHDL; Familiarity with low-power systems and high density surface mount packaging; Prior experience taking a design through high volume production; Experience with PC-based CAD tools; Hands-on debugging and prototyping; Software experience a plus; Superior communication and interpersonal skills.

Your Nature: Creative, hands-on problem solver; Precision minded approach and eye for detail; Independent proactive thinker; Performance enthusiast with an appreciation for elegant design; Very focused on results.

Your Track Record: BS / MS in electrical engineering or equivalent experience; 3+ years experience with analog and digital design.

www.pcbjn.com

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June 02 © Fred Heep, SFU Eng. Science 2

ENSC 204

Project Documentation

for

Electronics Design

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June 02 © Fred Heep, SFU Eng. Science 3

OVERVIEW OF TOPICS

• Electrical drawing types

• Schematics symbols

• Conventional drawing styles

• Analog & Digital differences

• Netlists

• Bill of Materials

• ECAD Software

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June 02 © Fred Heep, SFU Eng. Science 4

Schematics - Class 1

• Assignment expectations

• Types of electrical drawings

• Standards organizations

• Overview of schematic diagrams

• Elements of a drawing sheet

• Schematic symbol set

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June 02 © Fred Heep, SFU Eng. Science 5

Assignment Expectations

• Attention to detail– engineering demands unrelenting attention to detail

– in industry, small errors cost big $

– before starting work, read assignments and associated support instructions very carefully

– double check everything with multiple sets of eyes. Trust nothing and nobody. Use checklistsUse checklists.

– minute errors will propagate & create big headaches

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June 02 © Fred Heep, SFU Eng. Science 6

• Assessment

– During marking, instructors seek weaknesses & inconsistencies with assignment expectations;

no comments = good work

– Mistakes are expected and are useful learning tools but will need to be rectified at every stage

– Use instructors as a resource when you’re stuck. Don’t expect them to do your work for you.

– Group leaders will manage task division & ensure all members develop adequate skills in each area.

– Individual work = NO GROUP COLLABORATION

–– You must have your own Lab Handbook!!!You must have your own Lab Handbook!!!

–– Use the project documentation checklistsUse the project documentation checklists

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June 02 © Fred Heep, SFU Eng. Science 7

Types of Electrical Drawings

• Four main types– Schematics

– Logic diagrams

– Wiring & interconnection diagrams

– Block diagrams

Page 8: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 8

What is a Schematicdrawing?

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June 02 © Fred Heep, SFU Eng. Science 9

A form of communicationusing graphical symbols to

show the electrical connections of circuit

components, their values and their functions.

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June 02 © Fred Heep, SFU Eng. Science 10

A02

A13

A24

A35

A46

A57

A68

A79

B0 18

B1 17

B216

B315

B4 14

B513

B612

B7 11

E19

DIR1

U274LS245

>1

>2

>3

>4

>5

>6

>7

>8

>9

>10

>11

>12

>13

>14

>15

>16

P1HDR8X2-M

CLK6

BUSACK23

BUSREQ25

RESET26

NMI17

INT16

WAIT24

HALT18

RFSH28

WR22

RD21

IORQ20

MREQ19

M127

D713

D6 10D5

9D47

D3 8D2

12D115D014

A15 5A14

4A133

A12 2A11 1A10

40A939

A8 38A7

37A636

A5 35A4 34A3

33A232

A1 31A0

30

U3Z80ACPU

12

U1A74LS04

34

U1B

56

U1C

74LS04C1

100n

Y14.0MHz

R1

330R

R2

330R

R74K7

>1

>2

>3

>4

>5

>6

>7

>8

>9

>10

>11

>12

>13

>14

>15

>16

P2HDR8X2-M

8 9

U1D 74LS04 R3330R

A0A1A2A3A4A5A6A7

D0D1D2D3D4D5D6D7

REFRESH

VCC

CPUCLK

INT

M1

IORQ

WRRD

MREQA15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0

D7D6D5D4D3D2D1D0

RESET

Data Bus

Address BusDUM

VCC

Logic Schematic Diagram Example

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June 02 © Fred Heep, SFU Eng. Science 11

• Schematic diagrams are masterdrawings from which many other project assembly documents are derived

– bill of materials– wiring & interconnection diagrams– mechanical layouts

• enclosure• printed wiring board (PWB)• computer simulation• N.C. production equipment• automated testing (ATE)

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June 02 © Fred Heep, SFU Eng. Science 12

PWB - Printed Wiring Board (populated)

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June 02 © Fred Heep, SFU Eng. Science 13

Standards Organizations

• Compile industry accepted & proven standards for

• construction aspects

• identification markings

• size

• performance

• testing

• component parameters

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June 02 © Fred Heep, SFU Eng. Science 14

Some Standards Organizations ...

• ANSI (American National Standards Institute)

• ISO (International Standards Org.)

• IEC (Int’l Electrotechnical Commission)

• EIA(J) (Electronic Industries Alliance)(Japan)

• IEEE (Instit. Of Electrical & Electronics Eng’s)

• MIL (U.S. Military/Gov’t)

• JEDEC (Solid State Technology Assn.)

• IPC (Assn. Connecting Electronics Industries)

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June 02 © Fred Heep, SFU Eng. Science 15

IEC

Copyright (c)Ikeda Lab., Chiba University, 1993 - 1998.

http://w3.hike.te.chiba-u.ac.jp/iec417/ver2.0/html/index.html

(http://w3.hike.te.chiba-u.ac.jp/iec417/html/index)

• Graphical Symbols (IEC-417)• Int’l standards & conformity for all electrotechnical fields• European based

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June 02 © Fred Heep, SFU Eng. Science 16

IPC

• Research, development & standardization of interconnection schemes for manufacturing & reliability.

• Strongly linked to ANSI & PWB industry.

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June 02 © Fred Heep, SFU Eng. Science 17

EIA

• Standards forum for components, consumer electronics, telecom, electronic information

• Accredited by ANSI

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June 02 © Fred Heep, SFU Eng. Science 18

ISO

• Covers anything from Math & Natural Sciences, Healthcare, Railways, Food Technology, Paint, Electronics, etc.

• Quality Assurance (ISO9000, ISO9002)

• Document management practices

• Standards Council of Canada (SCC)

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June 02 © Fred Heep, SFU Eng. Science 19

IEEE• Information & service institute for electrical &

electronics engineers

• Most standards are linked with ANSI

• Develop standards for• symbols

• testing methodology & rating systems

• user documentation

• wiring practices

• communications protocols

• computer bus structures ...

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June 02 © Fred Heep, SFU Eng. Science 20

Schematic Symbols Represent Physical Components

Resistor Capacitor Inductor

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June 02 © Fred Heep, SFU Eng. Science 21

Schematic Symbol Set

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June 02 © Fred Heep, SFU Eng. Science 22

* See Lab Handbook - Appendix I

Page 23: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 23

Schematic Symbol Modifiers

Mechanically Linked

ThemperatureDependent

ForceSensitive

OptoEmitter

OptoDetector

Variable Trimmer

Iron Ferrite(Powder)

Adjustable

INDUCTOR CORES

Page 24: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 24

ANSI REFERENCE DESIGNATIONS

PART DESCRIPTIONANSIDES.

PART DESCRIPTIONANSIDES.

Accelerometer A Diode, breakdown VR (ZD)Alarm (visual or audible) DS Diode (capacitive - varactor) CRAntenna E (ANT) Diode (photo) CR (D)Arrestor, lightning E Diode (tunnel) CRAttenuator (fixed or variable) AT Electron tube VAutotransformer T Equalizer (& equalizing network) EQBallast RT Fan BBattery BT Ferrite bead rings E (FB)Bell DS Filter FLBlower B Flasher DSBuzzer DS Fuse FCable (coaxial, assembly) W Fusible link SQ (F)Capacitor C Gauge, meter MCircuit breaker CB Generator GCoil L Hardware (common fasteners) HConnector, receptacle J (SK) Head, (recording or erasing) PUConnector, plug P Headphones (HP)Contact, rotating SR Heater HR (HTR)Contactor (magnetically operated) K Horn LSCoupler, directional DC Hybrid (circuit, network, coil) HYCrystal (oscillator, piezo or quartz) Y Hydrophone MKCrystal detector or rectifier CR Inductor LDelay line or function DL Instrument, meter M

* A partial listing extracted from the ENSC Lab Handbook

Page 25: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 25

1 2 3 4

A

B

C

D

4321

D

C

B

ATitle

Number RevisionSize

A

Date: 6-Jul-1995 Sheet of File: H:\FRED\103\LEC-NOTE\103XMPL.S01Drawn By:

RCA-J2

+12

-12

C2u1

C1u1 R4

680R

LED2GRN

LED1RED

RV110K

R31K

R21K

R14K7RCA-J1

3

26

7

4

U1741

GAIN

INPUTAMPLIFIER

OUTPUTAMPLIFIER

Page 26: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 26

What Makes a Good Schematic?Elements of a well drawn schematic

• easy to read, understand & troubleshoot from

• functions of components are clear

• components and drawing elements are arranged intodistinct functional groups

• potentially ambiguous items are clearly labeled oridentified in Notes Section

• parts, values, pin numbers, polarities, nets, etc. are labeled clearly

• white-space, balance & eye pleasing

• consistency

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June 02 © Fred Heep, SFU Eng. Science 27

Elements of a Schematic Drawing Sheet

J1-2

J1-1R1

1K

R2 10K

3

26

7 14 5

U1LM741

C2

100n

C1100n

J2-1

J2-2

VCC

VEE

DC OutputDC Input

Part Value

Reference Designator

Component Symbols

NOTES:1) All resistors are 1/4W 5%2) All capacitors are monoceramic

Notes to ReaderCompany

Documented/Created By:

Revision Level

Sheet #

Drawn/Created By

Title

Company Info/Logo(optional)

File Name

Date

Other Reference Info

Border(Optional)

Net Connections

OutIn

Net Label

Annotations

3) Ext. power connections not shownfor simplicity.

Sheet ofModification date:

Size: Document Number: Rev.#:

Sheet Title:

Sheet File Name:

Sheet Creation date:DWG-SHT1a.sch A

Page 28: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 28

Elements of a Schematic Drawing Sheet

• Page layout, border & sheet size

• Circuit element arrangement

• Input - left // output - right

• White space & balance

• Title block info

• Notes to reader

• Annotations, function & net labels

• Circuit element arrangement* See checklist in Lab Handbook Rev.7+

Page 29: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 29

Mind Your Revision Levels

Page 30: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 30

Labeling & Notation Conventions

• ANSI reference designations• Lab Handbook (Appendix I)

• Values & Units• µF, K, R, M, V•• Avoid decimalsAvoid decimals (6K8 = 6.8K, 0R82 = 0.82Ω)

• Tolerance• Label near symbol for special parts (10R 1%)• Notes - All resistors 1/4W 5% carbon film unless …

• Component type/construction• Capacitors - film, tantalum, electrolytic, ceramic …• Resistors - carbon film, metal film, wirewound ...

Page 31: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 31

Conventional Writing Style

SchematicSchematic

citamehcS

Schematic

Page 32: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 32

Conventional Drawing Styles

+

-Ein1Eout

Ein2

+-

Ein1

Ein2

Eout

Conventional Unconventional

“Conventional Drawing Style” refers to the standardized arrangement of component symbols in an electronic circuit or

subcircuit.

Page 33: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

Net Routing Management

Poor Better

Page 34: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 34

Poor method of net management

Page 35: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 35

Page 36: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 36

Ein1Eout

Ein2 +

-

Not required

Required

Junctions confirm the electrical connection of two intersecting wires (lines).Junction symbols are not used as circuit nodes in schematic diagrams.

Appropriate Use of Junctions

Page 37: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 37

Notation Forms for Wire Interconnection

OK BETTER BETTER

JOINED CONNECTIONS

NOT JOINEDECAD SKETCH

Page 38: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 38

Separate Vs Bussed Interconnects

U1 U2

A1

A2

A3

A4

A5

A6

A0

A1

A2

A3

A4

A5

A6

A0

A1

A2

A3

A4

A5

A6

A0

U3

U2U1

A1

A2

A3

A4

A5

A6

A0

A1

A2

A3

A4

A5

A6

A0

A1

A2

A3

A4

A5

A6

A0

U3

Note: Pin sequencemay be rearrangedto suit.

Separate Connection Scheme Bus Interconnection Scheme(shown w/o net labels for simplicity)

Page 39: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 39

Using Busses

• Advantages of using of busses– significantly improves readability– Less chance of interpretation errors– Faster to draw and modify– Much easier management on multi-sheet drawings

• Other comments– Excellent for logic drawings– Rarely used for analog circuits

Page 40: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 40

Effective use of Busses

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June 02 © Fred Heep, SFU Eng. Science 41

Busses – General Notes

• Busses generally carry signals belonging to a related set; i.e. Address bus, Data bus

• Most logic schematics use many different busses

• Signal busses don’t distribute power

• All bus & net branch transitions = 4545°°

• Heavy bus line ends at last net branch

• Net labels are placed aboveabove and clearclear of the net & aligned between the branch point & destination

Page 42: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 42

Managing Connectors

P1-1

P1-2

+

-

P1-4

P1-3

P1-5

Poor Better

+

-

P1-4

P1-3

P1-1

P1-2

P1-5

+15V

-15V

P2-1

P2-2

P2-3

-15V

+15V

INV InputNON-INV InputInput GroundOutput GroundOutput

+15V SupplySupply Common

P1-1P1-2P1-3P1-4P1-5

P2-1P2-2P2-3 -15V Supply

Connector Signal

Page 43: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 43

To avoid $$ confusion, orientate connector symbols so that the pins and their numbering sequence is shown the same way they would

be viewed & arranged in the actual part or assembly.

If otherwise, make the reader clearly aware of the difference(s).

Actual Component Correct Avoid

Page 44: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 44

Using Net Connections

-15V Net

GND Net

Single Node Net

Net Label

Page 45: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 45

The Wiring Diagram

NGL

PP1ACPLUG SW1 T1F1

GND2

RECTIFIERFILTER

TRACKINGREGULATOR

TRI-SINECONVERTER

POWER

DRIVER

+ G - + G - + G -

+

G

-

AC

COM

AC -

G

+

-

G

+W

BK

W

BK

BK

R

BK

W

R

BK

W

R BK W WBKR WBKR

R Y BK O V GNBLGY

GNY

GNY O

O

SHIC

IC

SHSH

IC

SHIC

BKOGNWBKR

FREQ SYM MULT TTLOUT

DCOFFSET

OUTLEVEL

MAINOUT

WFSEL

W

SW

GYBK

ICSH

IC

VFOSINOUT

TTLOUT

TRISQ

TRIGND

TRIIN

WFIN

Page 46: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 46

The Block Diagram

• Arrows illustrate (process) flow as well as I/O’s.

• In electronics, each block may represent a group of components (R/C/L’s, IC’s, etc.) performing a dedicated function.

• B.D.’s explain what a group of parts does, not how it does it.

• Useful for fault finding & debugging.

A method of simplifying and explaining a complex system using labeled block symbols

logically arranged and joined by lines.

Page 47: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 47

Block Diagram Example

Input

+20dB+

-30dB

+ OTA

OutputLevelTrim

+

Unity GainBuffer

LPFfc~750Hz

Output

Release

S&H

ThresholdPrecision

FW Rectifier

-+40dB

Audio Signal Processor - Noise Gate

Page 48: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 48

Digital System Block Diagram

Glucose Monitor - (Texas Instruments)

Page 49: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 49

1. A block symbol which best represents each signal processing stage or sub-stage in the circuit or system.

2. Left to right flow, organized with inputs - leftmost and outputs - rightmost.

3. Standardized schematic symbols may be used (sparingly) for user controls, indicators, or simple circuitry performing noteworthy functions.

4. Function labels for each stage, component and input or output connections.

Block Diagrams should include:

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June 02 © Fred Heep, SFU Eng. Science 50

Block Diagrams Should Include:

5. Important signal levels.

6. Symbols such as (-) or (+) to indicate inverting or non-inverting inputs/stages.

7. Standardized signal waveform shapes, signal processing modifiers (esp. for filters or passbandcontrol), or annotation symbols.

8. A title (and other appropriate credits or annotations).

Page 51: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 51

Some Useful Block Diagram Function Symbols

Hysteresis Bandpass Low Pass High PassEdge Pulses

Falling Rising SignalArrow

Direction

Page 52: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 52

88 MHz FM Stereo Wireless Transmitter

Page 53: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 53

Small Cable Distribution System Diagram

Page 54: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 54

Schematic -> Block DiagramANT

C1

C3

C4

C6 C7

C2L1

R2

R1

R3 R4

R5

R6

3

21

8

4

U1A5

67

U1B

D1

RV1

BT1SW1

C8

LS1

Loud Speaker

ANTGND

+

Volume

+

9V BAT108-140MHz

Detector

PWR SW

x30x30

U1A U1B

Tuner

C5

Aircraft Receiver

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June 02 © Fred Heep, SFU Eng. Science 55

Aircraft Receiver Netlist - Generic Format[ANT

ANTENNA

][C1TAJ-ACAP_NP

][C2TAJ-ACAP_VAR

][C3TAJ-ACAP_NP

][C7RAD-197CAP_POL

] [L1

INDUCTOR

] [R2RC05R

] [R1RC05

R

][U18DIP300LM358

][D1DO-7DIODE

][RV13059YR_POT

][BT1

BATTERY

][LS1

SPEAKER

](N00000ANT-1C1-1)(N00010C1-2C2-1L1-1D1-2)(N00001C3-1C2-2L1-2R1-1)

(N00011C4-1R2-2U1-3D1-1)(N00012C6-2R3-2)(N00007C7-2R4-2)(N00005R2-1U1-8SW1-COMMC5-2)(N00002R3-1U1-2RV1-2)

(Edited example only - not a complete listing)

Page 56: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 56

Netlists

• Used to create or verify a link between a schematic and a PWB design.

• ASCII text file

• Many formats for compatibility with different PWB design software packages.

• EDIF, Cadstar, Protel, Tango ...

Listing of the namesnames & parts symbolsparts symbols used in an ECAD circuit drawing as well as their connection pointsconnection points on each netnet.

Page 57: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 57

What is a BOM

• BOM = Bill of Material(s)

• A BOM details all the individual items needed to complete an assembly– Part number– Part value– Description (in detail)– Quantity– Manufacturer– Comments to the buyer

• Substitution options• Critical characteristics, etc.

– Supplier, price … (optional)

Page 58: ELECTRICAL DESIGN ENGINEER - Simon Fraser … DESIGN ENGINEER ... – Logic diagrams – Wiring & interconnection diagrams – Block diagrams. ... Logic Schematic Diagram Example.

June 02 © Fred Heep, SFU Eng. Science 58

Bill of Materials for VCHIP3 REV2 - Jerrold19 April, 2001 09:24 Page : 1/1

# DESCRIPTION VALUE/PN MAKE QTY DESIGNATION

1 Capacitor, 10pF/50V (pref NPO or min 10%), ceramic,radial, 0.2"ls

C322C100M5U5CA Kemet 1 C20

2 Capacitor, 100nF/50V, Z5U, 20%, monoceramic, radial,0.2" ls

C322C104M5U5CA Kemet 9 C1, C2, C3, C5, C7, C11, C12,C15, C16

3 Connector, 4 pin locking straight header 640456-4 Amp 3 J1, J2, J4

4 Crystal, 14.31818MHz, HC49, parallel res. 14.318MHz-HC4920/50/10S

IQD (Farnell) 0 Y2 (not required)

5 Crystal, 20.0000MHz, HC49S (short), parallel res. A-20.000000-18-FUND Raltron 1 Y1

6 Diode, signal 1N4148/1N914A any 0 D1 (not required))

7 IC, EEPROM, serial, CMOS, DIP8, plastic 24C01-10PC Atmel 1 U7

8 IC, CMOS multiplexer, DIP16, plastic 4053 any 1 U3

9 IC, voltage controller, TO-92 MC34064P Motorola 1 U6

10 IC, microcontroller, OTP, DIP18, plastic PIC16C56-20 HS/P uCHIP 1 U4

11 Inductor, RF choke, 47uH, radial,0.3 or 0.4, or 0.5" ls

AL03-47K RCD 1 L1

12 PWB, VCHIP3 Rev2, BHE-02-0795 1

13 Resistor, 1K, 1/4W, 5% 1K, 1/4W, 5% 2 R7, R15 (not required), R22

14 Resistor, 820R, 1/4W, 5% 820R, 1/4W, 5% 1 R20

15 Socket, IC, DIP8, solder 640463 Amp 2 U1, U7

16 Spacer, 0.625", polyamide 115-0260-009MSPM-4-01

JohnsonRichco/Intek

2

17 Standoff, PWB, SS, #6-32 threaded, press-fit KF(S)E-632-12 PEM,Interfast

1

18 Transistor, NPN, TO-92 2N3904 any 1 Q1

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June 02 © Fred Heep, SFU Eng. Science 59

ECAD & the BOM

• Generated from your ECAD software– Basic column headings, parts values, reference designators, etc.– Information output is typically limited

• Its format and complexity varies with ECAD program

• Newer, up-to-date software permits a higher degree of integration, flexibility and customization

• Commonly exported to a spreadsheet; eg. MS Excel– Easier to send by email to parts suppliers/buyers– Anyone can read them easily in this format– Columns can be added, hidden or sorted to suit needs of user– Once built and accurate, other project BOMs can be built quickly

cutting and pasting info from one sheet to another

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June 02 © Fred Heep, SFU Eng. Science 60

How to Build a BOM• From your ECAD software, generate your BOM output

–– do this after all ECAD details are finalizeddo this after all ECAD details are finalized

• BOMs are generally highly developed - manually.–– research, specify and check each lineresearch, specify and check each line--item carefully for accuracy item carefully for accuracy

(g(get a datasheet for each semiconductor & special part)et a datasheet for each semiconductor & special part)–– DonDon’’t forget all the misc. stufft forget all the misc. stuff……(screws, nuts, washers,(screws, nuts, washers, heatsinksheatsinks, ,

standoffs,standoffs, PWBsPWBs, enclosures, etc.), enclosures, etc.)

• Be certain that your BOM matches your revision level–– Ensure that both BOM and related drawings reflect the same Rev. Ensure that both BOM and related drawings reflect the same Rev. ##–– Ensure data between ECAD & BOM correlate after each changeEnsure data between ECAD & BOM correlate after each change

• REF column is sequential; sort others on the DescriptionDescription column

• Use Lab Handbook examples or ‘Project Documentation’ info

• Most companies have set practices for managing documents