Cyclone Device Handbook, Volume 1 - Intel FPGA and SoC Altera Corporation Preliminary Cyclone...

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Transcript of Cyclone Device Handbook, Volume 1 - Intel FPGA and SoC Altera Corporation Preliminary Cyclone...

  • Preliminary Information101 Innovation DriveSan Jose, CA 95134www.altera.com

    Cyclone Device Handbook, Volume 1

    C5V1-2.4

    http://www.altera.com

  • Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks andservice marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-plication or use of any information, product, or service described herein except as expressly agreed to in writing by AlteraCorporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-formation and before placing orders for products or services.

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    Contents

    Chapter Revision Dates ........................................................................... xi

    About this Handbook ............................................................................. xiiiHow to Find Information ..................................................................................................................... xiiiHow to Contact Altera .......................................................................................................................... xiiiTypographic Conventions .................................................................................................................... xiv

    Section I. Cyclone FPGA Family Data SheetRevision History .................................................................................................................................... 21

    Chapter 1. IntroductionIntroduction ............................................................................................................................................ 11Features ................................................................................................................................................... 11Document Revision History ................................................................................................................. 13

    Chapter 2. Cyclone ArchitectureFunctional Description .......................................................................................................................... 21Logic Array Blocks ................................................................................................................................ 23

    LAB Interconnects ............................................................................................................................ 23LAB Control Signals ......................................................................................................................... 24

    Logic Elements ....................................................................................................................................... 25LUT Chain and Register Chain ...................................................................................................... 27addnsub Signal ................................................................................................................................. 27LE Operating Modes ........................................................................................................................ 27

    MultiTrack Interconnect ..................................................................................................................... 212Embedded Memory ............................................................................................................................. 218

    Memory Modes ............................................................................................................................... 218Parity Bit Support ........................................................................................................................... 220Shift Register Support .................................................................................................................... 220Memory Configuration Sizes ........................................................................................................ 221Byte Enables .................................................................................................................................... 223Control Signals and M4K Interface .............................................................................................. 223Independent Clock Mode .............................................................................................................. 225Input/Output Clock Mode ........................................................................................................... 225Read/Write Clock Mode ............................................................................................................... 228Single-Port Mode ............................................................................................................................ 229

    Global Clock Network and Phase-Locked Loops ........................................................................... 229Global Clock Network ................................................................................................................... 229

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    Cyclone Device Handbook, Volume 1

    Dual-Purpose Clock Pins .............................................................................................................. 231Combined Resources ..................................................................................................................... 231PLLs .................................................................................................................................................. 232Clock Multiplication and Division .............................................................................................. 235External Clock Inputs .................................................................................................................... 236External Clock Outputs ................................................................................................................. 236Clock Feedback ............................................................................................................................... 237Phase Shifting ................................................................................................................................. 237Lock Detect Signal .......................................................................................................................... 237Programmable Duty Cycle ........................................................................................................... 238Control Signals ................................................................................................................................ 238

    I/O Structure ........................................................................................................................................ 239External RAM Interfacing ............................................................................................................. 246DDR SDRAM and FCRAM ........................................................................................................... 246Programmable Drive Strength ..................................................................................................... 249Open-Drain Output ........................................................................................................................ 250Slew-Rate Control .......................................................................................................................... 251Bus Hold .......................................................................................................................................... 251Programmable Pull-Up Resistor .................................................................................................. 251Advanced I/O Standard Support ................................................................................................ 252LVDS I/O Pins ................................................................................................................................ 254MultiVolt I/O Interface ................................................................................................................. 254

    Power Sequencing and Hot Socketing ............................................................................................. 255Referenced Documents ....................................................................................................................... 256Document Revision History ............................................................................................................... 256

    Chapter 3. Configuration and TestingIEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 31SignalTap II Embedded Logic Analyzer ............................................................................................ 35Configuration ..........................................