A Fully Synthesized Fractional-N Matsuzawa & Okada Lab. Matsuzawa & Okada Lab. A Fully Synthesized...
Transcript of A Fully Synthesized Fractional-N Matsuzawa & Okada Lab. Matsuzawa & Okada Lab. A Fully Synthesized...
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Matsuzawa& Okada Lab.
Matsuzawa& Okada Lab.
A Fully Synthesized Fractional-NIL-PLL Using Only Digital Library
Dongsheng Yang, Wei Deng, Kengo Nakata,Teerachot Siriburanon, Kenichi Okada, and Akira Matsuzawa
Tokyo Institute of Technology, JapanIEICE General Conference 2016
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Matsuzawa& Okada Lab.
Outline
• Motivation• Concept of Injection Locking• Fractional-N Implementations• Performance Comparison• Conclusion
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Motivation
[1] W. Deng, et al., ISSCC2014
• Why High Performance PLL– Clock generation/distribution
• Key Specifications for SoC Clocking– Small area– Low power consumption– Low jitter– Insensitive over environment variations– Scalable with technology advancement
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Injection Locking Technique
JitterTDC-PLL=6.4ps JitterIL-PLL=1.5ps
Frequency Offset [Hz]
Phas
e N
oise
[dB
c/Hz
]
10M 100M1M100k
-70
-90
-110
-130IL-PLL
TDC-PLL
Free-running oscillator
BW=2MHz
BW=40MHz
𝒇𝒇𝐢𝐢𝐢𝐢𝐢𝐢 =⁄𝟔𝟔 (𝑵𝑵(𝑵𝑵− 𝟏𝟏))
𝟐𝟐𝝅𝝅· 𝒇𝒇𝐫𝐫𝐫𝐫𝐫𝐫
REF Injection locked
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Sub-Integer-N Operation
[P. Park, et al., ISSCC 2012]
Reference
D D D D...
...
P0 P1 P2
e.g. N=3+(1/M)
Reference
VCO
P0
P1
P2...
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Time Domain (Fractional-N)
• Injection at the same phase two times
Reference
VCOP1
P2
... ...
[2] W. Deng, et al., ISSCC2015
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Phase Domain (Fractional-N)
P0 P0 P1 P1 P2 P2 P3 …
fPLL=(N+0.5/M)·fref
N·2π
2·Tref 3·TrefTref 4·Tref 5·Tref
φPLL
t
(2·N+1/M)·2π
(3·N+1/M)·2π
(4·N+2/M)·2π
P0
P1
P1
P2
P0
[2] W. Deng, et al., ISSCC2015
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Fractional-N Controller
DSM
FCW
Deglitching
Mapping
SubIntegerDither
MDLL
Retimer
REFGating Array
[2] W. Deng, et al., ISSCC2015
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Design Procedure
Verilog netlist(gate-level)
Verilog RTL
Verilog netlist(gate-level)
DCO DAC
Logic
Logic
Logic Synt. Tool
GDSII
P&R Tool
Netlist
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Comp. of State-of-art PLLs
This work [1] [4] [5]
CMOS 65nm 65nm 65nm 65nm
TopologySoft
Injectionlocking
Injection locking
DTC-basedMDLL
Injection locking
Type Frac-N Int-N Frac-N Sub-Int-NFrequency
[GHz] 0.8-1.7 0.39-1.41 1.6-1.9 0.25-1.65
Power[mW]
FoM[dB] -224.2 -236.5 -232 -221.9
Synthesizable ? Yes No
*FOM is calculated based on RMS jitter.
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Conclusion
• A fully synthesizable fractional-N IL-PLL is presented.
• Only digital library is used in the whole design.