PCI Express Hard IP Quick Start Guide with SOPC Builder

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© 2009 Altera Corporation—Confidential PCI Express Hard IP Quick Start Guide with SOPC Builder

description

PCI Express Hard IP Quick Start Guide with SOPC Builder. Objectives. Implement a PCI Express system from design to working model in under 45 minutes using an Arria ® II GX* device & SOPC Builder You will see - PowerPoint PPT Presentation

Transcript of PCI Express Hard IP Quick Start Guide with SOPC Builder

Page 1: PCI Express Hard IP Quick Start Guide with SOPC Builder

© 2009 Altera Corporation—Confidential

PCI Express Hard IP Quick Start Guide with SOPC Builder

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Objectives

Implement a PCI Express system from design to working model in under 45 minutes using an Arria® II GX* device & SOPC Builder

You will see How easy it is to create PCI Express designs using Arria II GX

device Hard IP blocks and transceivers How SOPC Builder simplifies complex systems like PCI Express

* Procedures presented may be similarly performed on Stratix IV GX devices

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© 2009 Altera Corporation—Confidential

PCI Express Hard IP Quick Start Guide with SOPC BuilderAltera PCI Express Solutions

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Altera PCI Express Solutions

Arria II GX FPGAs Arria II GX embedded transceivers Arria II GX PCIe Hard IP blocks

SOPC Builder PCI Express Compiler

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Introducing Arria II GX FPGAs Increased system integration on a low-cost FPGA

Up to 256k equivalent logic elements Up to 8.5Mbits of on-chip RAM and 736 18x18 multipliers Up to 16 full-duplex transceivers up to 3.75Gbps

Lower power 40nm process with 0.9V core voltage <100mW per transceiver channel (@ 3.125Gbps)

Transceiver FPGA design made easy Built-in PCI Express hard IP Single design environment Protocol IP packs, design examples, and reference designs

Low Power, Low Cost, Easy to Use

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Arria II GX FPGA Architecture

Transceivers• Up to 3.75 Gbps• 4 to 16 channels• 100 mW per channel

Logic• 16K to 256K LEs

Hard PCI Express IP• Gen1.1 x1, x4, x8

Configurable I/O• Up to 612 I/O• 1-Gbps LVDS• 600-Mbps DDR2

and DDR3

Internal memory• 0.7 to 9 Mbits of

block memory• Up to 5 Mbits of

LAB memory

DSP• 56 to 736 multipliers

Up to 6 PLLs

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Transceiver Block Architecture Easily configured using Quartus® II

MegaWizard® plug-ins

Arria II GX device with 8 transceiver channels (2

transceiver blocks)

PIPE to FPG

A

Central Control Unit (CCU)

Clock Management Unit 1

Clock Management Unit 0

Transceiver Channel 3

TX3 & RX3

Transceiver Channel 2

TX2 & RX2

Transceiver Channel 1

TX1 & RX1

Transceiver Channel 0

TX0 & RX0

PCIe

Link

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Performs transaction, data link, and PHYMAC layer functionality Supports

PCI Express Gen 1.1 x1, x4 & x8 lane configurations Root port and endpoint applications

Connects directly to embedded transceivers using internal PIPE interface Shared by two adjacent transceiver blocks

Enabled through the PCI Express Compiler Wizard

PCI Express Hard IP Block

Arria II GX FPGA

PCI Express Hard IP Block

Transaction Layer

Data Link Layer

PHYMAC Layer

Transceiver Block 0

Transceiver Block 1

Transceiver Block 2

Embedded Transceiver BlockTransceiver Block nPIPE

To / fromSlot or cable

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

PCI Express Hard IP Diagram Configurable maximum

payload size 128, 256, or 512 bytes

1 Virtual Channel 4-Kbyte receive buffer 2-Kbyte transmit retry

buffer 64-bit application datapath

width Interrupt support (legacy,

MSI & MSI-X) Advanced error reporting

(AER) support Power management

support Local management

interface (LMI) to access configuration registers

Status & debug interface

PCI Express Protocol Stack

Adapter Application Layer

Clock & Reset Selection

PLD FabricPCI Express Hard IP BlockTransceiver Block

PCSPMA

Transceiver Block

PCSPMARetryBuffer

VC RXBuffer

TLInterface

Local Mgmt IF

(LMI)

PIPE

FPG

A In

terf

ace

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Example PCIe Hard IP Location

Arria II GX Device with 12 channels & 1 hard IP block

Channel3

Channel2

Channel1

Channel0

Channel3

Channel2

Channel1

Channel0

GXBL1 (Slave)

GXBL0 (Master)

PCIe Hard IP Block

PCIe Lane 6

PCIe Lane 7

PCIe Lane 4

PCIe Lane 5

PCIe Lane 2

PCIe Lane 3

PCIe Lane 0

PCIe Lane 1

Channel3

Channel2

Channel1

Channel0

GXBL2

PCIe

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

SOPC Builder System design tool enabling designers to describe their

system in design blocks Automates IP Block connectivity Supports both Memory-mapped and Streaming systems

Reduce Development Time by Weeks!

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

PCI Express Compiler Configures PCIe

MegaCore® IP function Includes all PCIe Hard

IP settings Includes embedded

transceiver blocks Output files

Verilog HDL or VHDL wrapper files

Tcl constraint file SDC file for TimeQuest

timing analysis Application layer design

example & testbench to verify chosen settings

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

PCI Express / SOPC Builder Design Flow

2. PCI Express Compiler gets called from SOPC Builder to configure PCIe MegaCore block and add to embedded system

3. SOPC Builder generates HDL that is added to Quartus II project for compilation into Arria II GX device

1. Open SOPC Builder from the Quartus II software to build embedded system

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© 2009 Altera Corporation—Confidential

PCI Express Hard IP Quick Start Guide with SOPC BuilderPCI Express Endpoint using SOPC Builder Demonstration

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Example PCIe-SOPC Builder System

DMA DMAMemory DMA

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

PCIe Endpoint Design Example

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Design Example Simulation

Modelsim™ simulation directory generated at <sopc_builder_system>_sim Scripts to simplify setting up & running ModelSim

Testbench files located in directory <pcie_component_name>_examples Uses an auto-generated bus functional model (BFM) to emulate

the other end of the PCIe link Performs link initialization and generates verification messages Modify files altpcietb_bfm_driver.v or .vhd to perform additional

transactions

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PCI Express Compiler / SOPC BuilderDemonstration

Click here if demo does not open

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© 2009 Altera Corporation—Confidential

PCI Express Hard IP Quick Start Guide with SOPC BuilderSummary

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Summary

SOPC Builder makes designing complex PCI Express systems straightforward and simple

Arria II GX Hard IP block provides a low-cost and easy-to-use way to implement your PCI Express solution

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Additional Materials Arria II GX FPGA Overview Arria II GX Getting Started Arria II GX Design Resources Altera PCI Express Solutions webpage Altera PCI Express Hard IP webpage Altera Online training

PCI Express online training for Altera 40 nm devices Using SOPC Builder

Altera Documentation Arria II GX Device Handbook PCI Express Compiler User Guide

PCI Express protocol resources Download PCIe Specification at PCI-SIG (www.pcisig.com) Training and reference materials available from Mindshare Inc. (

www.mindshare.com)

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© 2009 Altera Corporation—ConfidentialALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

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