PCF8578 LCD row/column driver for dot matrix graphic displays · 1. General description The PCF8578...
Transcript of PCF8578 LCD row/column driver for dot matrix graphic displays · 1. General description The PCF8578...
1. General description
The PCF8578 is a low power CMOS1 LCD row and column driver, designed to drive dotmatrix graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has40 outputs, of which 24 are programmable and configurable for the following ratios ofrows/columns: 32⁄8, 24⁄16, 16⁄24 or 8⁄32. The PCF8578 can function as a stand-alone LCDcontroller and driver for use in small systems. For larger systems it can be used inconjunction with up to 32 PCF8579s for which it has been optimized. Together these twodevices form a general purpose LCD dot matrix driver chip set, capable of driving displaysof up to 40960 dots. The PCF8578 is compatible with most microcontrollers andcommunicates via a two-line bidirectional bus (I2C-bus). Communication overhead isminimized by a display RAM with auto-incremented addressing and display bankswitching.
2. Features
n Single chip LCD controller and driver
n Stand-alone or may be used with up to 32 PCF8579s (40960 dots possible)
n 40 driver outputs, configurable for several ratios of rows/columns: 32⁄8, 24⁄16, 16⁄24 or 8⁄32
n Selectable multiplex rates: 1:8, 1:16, 1:24 or 1:32
n Externally selectable bias configuration, 5 or 6 levels
n 1280-bit RAM for display data storage and scratch pad
n Display memory bank switching
n Auto-incremented data loading across hardware subaddress boundaries (withPCF8579)
n Provides display synchronization for PCF8579
n On-chip oscillator, requires only 1 external resistor
n Power-On Reset (POR) blanks display
n Logic voltage supply range 2.5 V to 6 V
n Maximum LCD supply voltage 9 V
n Low power consumption
n I2C-bus interface
n Compatible with most microcontrollers
n Optimized pinning for single plane wiring in multiple device applications (withPCF8579)
n Space saving 56-lead small outline package and 64 pin quad flat pack
PCF8578LCD row/column driver for dot matrix graphic displaysRev. 06 — 5 May 2009 Product data sheet
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 15.
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
3. Applications
n Automotive information systems
n Telecommunication systems
n Point-of-sale terminals
n Industrial computer terminals
n Instrumentation
4. Ordering information
[1] Should not be used for new designs.
5. Marking
Table 1. Ordering information
Type number Package
Name Description Version
PCF8578T/1 VSO56 plastic very small outline package; 56 leads SOT190-1
PCF8578H/1 LQFP64 plastic low profile quad flat package; 64 leads; body10 × 10 × 1.4 mm[1]
SOT314-2
PCF8578HT/1 TQFP64 plastic thin quad flat package; 64 leads;body 10 × 10 × 1.0 mm
SOT357-1
Table 2. Marking codes
Type number Marking code
PCF8578T/1 PCF8578T
PCF8578H/1 PCF8578H
PCF8578HT/1 PCF8578HT
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 2 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
6. Block diagram
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
Fig 1. Block diagram
VSS
C39 - C32R31/C31 - R8/C8
R7 - R0
msa842
PCF8578
OUTPUTCONTROLLER
ROW/COLUMN(1)
DRIVERS
DISPLAYMODE
CONTROLLER
Y DECODERAND SENSING
AMPLIFIERS
32 × 40-BITDISPLAY RAM
X DECODER
DISPLAYDECODER
RAM DATA POINTERSUBADDRESSCOUNTER
TIMINGGENERATOR
I2C-BUSCONTROLLER
INPUTFILTERS
COMMANDDECODER
POWER-ONRESET
OSCILLATOR
TEST
SCL
SDA
n.c. n.c. SA0
Rext(OSC)
OSC
CLK
SYNC
Y X
VDD
V2
V3
V4
V5
VLCD
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 3 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
7. Pinning information
7.1 Pinning
Top view. For mechanical details, see Figure 29.
Fig 2. Pinning diagram of PCF8578T/1 (VSO56)
PCF8578T
SDA R0
SCL R1
SYNC R2
CLK R3
VSS R4
TEST R5
SA0 R6
OSC R7
VDD R8/C8
V2 R9/C9
V3 R10/C10
V4 R11/C11
V5 R12/C12
VLCD R13/C13
n.c. R14/C14
n.c. R15/C15
C39 R16/C16
C38 R17/C17
C37 R18/C18
C36 R19/C19
C35 R20/C20
C34 R21/C21
C33 R22/C22
C32 R23/C23
R31/C31 R24/C24
R30/C30 R25/C25
R29/C29 R26/C26
R28/C28 R27/C27
001aaj842
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 4 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Top view. For mechanical details, see Figure 30.
Fig 3. Pinning diagram of PCF8578H/1 (LQFP64)
PCF8578H
R5 R22/C22
R4 n.c.
R3 R23/C23
R2 R24/C24
R1 R25/C25
R0 R26/C26
SDA R27/C27
SCL R28/C28
SYNC R29/C29
CLK R30/C30
VSS R31/C31
TEST C32
SA0 n.c.
n.c. C33
n.c. C34
OSC C35
n.c.
R6
n.c.
R7
n.c.
R8/
C8
VD
DR
9/C
9
V2
R10
/C10
V3
R11
/C11
V4
R12
/C12
V5
R13
/C13
VLC
DR
14/C
14
n.c.
R15
/C15
n.c.
R16
/C16
n.c.
R17
/C17
C39
R18
/C18
C38
R19
/C19
C37
R20
/C20
C36
R21
/C21
001aaj840
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 5 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Top view. For mechanical details, see Figure 31.
Fig 4. Pinning diagram of PCF8578HT/1 (TQFP64)
PCF8576HT
R5 R22/C22
R4 n.c.
R3 R23/C23
R2 R24/C24
R1 R25/C25
R0 R26/C26
SDA R27/C27
SCL R28/C28
SYNC R29/C29
CLK R30/C30
VSS R31/C31
TEST C32
SA0 n.c.
n.c. C33
n.c. C34
OSC C35
n.c.
R6
n.c.
R7
n.c.
R8/
C8
VD
DR
9/C
9
V2
R10
/C10
V3
R11
/C11
V4
R12
/C12
V5
R13
/C13
VLC
DR
14/C
14
n.c.
R15
/C15
n.c.
R16
/C16
n.c.
R17
/C17
C39
R18
/C18
C38
R19
/C19
C37
R20
/C20
C36
R21
/C21
001aaj911
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 6 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
7.2 Pin description
[1] The TEST pin must be connected to VSS.
Table 3. Pin description
Symbol Pin Description
VSO56 LQFP64,TQFP64
SDA 1 7 I2C-bus serial data input/output
SCL 2 8 I2C-bus serial clock input
SYNC 3 9 cascade synchronization output
CLK 4 10 external clock input/output
VSS 5 11 ground
TEST[1] 6 12 test pin
SA0 7 13 I2C-bus slave address input (bit 0)
OSC 8 16 oscillator input
VDD 9 20 supply voltage
V2 to V5 10 to 13 21 to 24 LCD bias voltage inputs
VLCD 14 25 LCD supply voltage
n.c. 15, 16 14, 15,17 to 19,26 to 28, 36,47
not connected
C39 to C32 17 to 24 29 to 35, 37 LCD column driver outputs
R31/C31 to R8/C8 25 to 48 38 to 46,48 to 62
LCD row and column driver outputs
R7 to R0 49 to 56 63, 64, 1 to 6 LCD row driver outputs
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 7 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
8. Functional description
8.1 Display configurationsThe PCF8578 row and column driver is designed for use in one of three ways:
• Stand-alone row and column driver for small displays (mixed mode)
• Row and column driver with cascaded PCF8579s (mixed mode)
• Row driver with cascaded PCF8579s (mixed mode and row mode)
[1] Using 15 PCF8579s.
[2] Using 16 PCF8579s.
In mixed mode, the device functions as both a row and column driver. It can be used insmall stand-alone applications, or for larger displays with up to 15 PCF8579s(31 PCF8579s when two slave addresses are used). See Table 4 for common displayconfigurations.
In row mode, the device functions as a row driver with up to 32 row outputs and providesthe clock and synchronization signals for the PCF8579. Up to 16 PCF8579s can normallybe cascaded (32 when two slave addresses are used).
Timing signals are derived from the on-chip oscillator, whose frequency is determined bythe value of the resistor connected between pin OSC and pin VSS.
Five commands are available to configure and control the operation of the device.Communication is made via a two-line bidirectional I2C-bus. The device may have one oftwo slave addresses. The only difference between these slave addresses is the leastsignificant bit, which is set by the logic level applied to SA0. The PCF8578 and PCF8579have different subaddresses. The subaddress of the PCF8578 is only defined in mixedmode and is fixed at 0111 100 (see Section 8.8.7 on page 19). The RAM may only beaccessed in mixed mode and data is loaded as described for the PCF8579.
Bias levels may be generated by an external potential divider with appropriate decouplingcapacitors. For large displays, bias sources with high drive capability should be used. Atypical mixed mode system operating with up to 15 PCF8579s is shown in Figure 5 (astand-alone system would be identical but without the PCF8579).
Table 4. Possible display configurations
Application
Multiplex rate Mixed mode Row mode Typical applications
Rows Columns Rows Columns
stand alone 1:8 8 32 - - small digital oralphanumeric displays1:16 16 24 - -
1:24 24 16 - -
1:32 32 8 - -
withPCF8579
1:8 8[1] 632[1] 8 × 4[2] 640[2] alphanumeric displaysand dot matrix graphicdisplays
1:16 16[1] 624[1] 16 × 2[2] 640[2]
1:24 24[1] 616[1] 24[2] 640[2]
1:32 32[1] 608[1] 32[2] 640[2]
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 8 of 46
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PC
F8578_6
Product data shee
NX
P S
emiconductors
PC
F8578
LCD
row/colum
n driver for dot matrix graphic displays
LK SYNC
A0
A1
A2
A3
CF8579
40columns
subaddress 1VSS/VDD
msa843
V4 V3
© N
XP
B.V. 2009. A
ll rights reserved.
tR
ev. 06 — 5 M
ay 20099 of 46 Fig 5. Typical mixed mode configuration
Rext(OSC)OSC
SDA
SA0
C
P
SCL
SCLSDA
SA0
CLK SYNC
PCF8578
VLCD
VLCD
VLCD VLCD
VDD
VSS/VDD
VSS/VDD
VSS
VSS
VSS VSS
LCD DISPLAY
R1C
R2C
R3C
R2C
R1C
40 ncolumns
nrows
HOSTMICROCONTROLLER
SCL
SDAV5
V4
V3
V2
VDD
VDD VDD
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Table 5 shows the relative values of the resistors required in the configuration of Figure 5to produce the standard multiplex rates.
8.2 Power-on resetAt power-on the PCF8578 resets to a defined starting condition as follows:
1. Display blank
2. 1:32 multiplex rate, row mode
3. Start bank 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I2C-bus interface is initialized
Remark: Do not transfer data on the I2C-bus for at least 1 ms after power-on to allow thereset action to complete.
8.3 Multiplexed LCD bias generationThe bias levels required to produce maximum contrast depend on the multiplex rate andthe LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which theLCD exhibits 10 % contrast. Table 6 shows the optimum voltage bias levels and Table 7the discrimination ratios (D) for the different multiplex rates as functions of Voper.
(1)
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
(2)
and the RMS off-state voltage (Voff(RMS)) with the equation
(3)
Table 5. Multiplex rates and resistor values for Figure 5
Resistors Multiplex rate (1:n)
n = 8 n = 16, 24, 32
R1 R R
R2 R
R3
n 2–( )R3 n–( )R n 3–( )R
Voper VDD VLCD–=
Von RMS( )1n---
n 1–
n n 1+( )------------------------+Voper=
Voff RMS( )2 n 1–( )n n 1+( )2
-------------------------------Voper=
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 10 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
where the values for n are determined by the multiplex rate (1:n). Valid values for n are:
n = 8 for 1:8 multiplex
n = 16 for 1:16 multiplex
n = 24 for 1:24 multiplex
n = 32 for 1:32 multiplex
Figure 6 shows the values of Table 6 as graphs.
Table 6. Optimum LCD voltages
Bias ratios Multiplex rate
1:8 1:16 1:24 1:32
0.739 0.800 0.830 0.850
0.522 0.600 0.661 0.700
0.478 0.400 0.339 0.300
0.261 0.200 0.170 0.150
Table 7. Discrimination ratios
Discriminationratios
Multiplex rate
1:8 1:16 1:24 1:32
0.297 0.245 0.214 0.193
0.430 0.316 0.263 0.230
1.447 1.291 1.230 1.196
3.370 4.080 4.680 5.190
V2
Voper--------------
V3
Voper--------------
V4
Voper--------------
V5
Voper--------------
Voff RMS( )Voper
-------------------------
Von RMS( )Voper
-----------------------
DVon RMS( )Voff RMS( )-------------------------=
Voper
Vth--------------
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 11 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Vbias = V2, V3, V4, V5; see Table 6.
Fig 6. Vbias /Voper as a function of the multiplex rate
1:8 1:16 1:32
1.0
0
0.8
msa838
1:24
0.6
0.4
0.2
multiplex rate
Vbias
Voper V2/Voper
V3/Voper
V4/Voper
V5/Voper
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 12 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
8.4 LCD drive mode waveforms
Fig 7. LCD row and column waveforms
msa841
Tfr
COLUMN
SYNC
ROW 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SYNC
COLUMN
ROW 0
23222120191817161514131211109876543210
SYNC
COLUMN
ROW 0
15
SYNC
14131211109876543210
COLUMN
ROW 0
0 1 2 3 4 5 6 7
ON
OFF
1:8
1:16
1:24
1:32
columndisplay
VDD
V2
V3
V4
V5
VLCD
VDD
V2
V3
V4
V5
VLCD
VDD
V2
V3
V4
V5
VLCD
VDDV2
V3
V4V5VLCD
VDDV2
V3V4V5VLCD
VDDV2
V3V4V5VLCD
VDDV2
V3V4V5VLCD
VDDV2
V3V4V5VLCD
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 13 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Vstate1(t) = C1(t) − R1(t).
Vstate2(t) = C2(t) − R2(t).
Fig 8. LCD drive mode waveforms for 1:8 multiplex rate
msa840
ROW 1R1 (t)
ROW 2R2 (t)
COL 1C1 (t)
COL 2C2 (t)
dot matrix1:8 multiplex rate
0.261 Voper
0.261 Voper
0 V
0.261 Voper
0.261 Voper
0 V
Voper
0.478 Voper
0.478 Voper
state 1 (OFF)state 2 (ON)VDD
V2V3V4V5VLCD
VDDV2V3V4V5VLCD
VDDV2V3V4V5VLCD
VDDV2V3V4V5VLCD
Tfr
Voper
Voper
Voper
Vstate 1(t)
Vstate 2(t)
Von RMS( )Voper
-----------------------18---
8 1–
8 8 1+( )------------------------+ 0.430==
Voff RMS( )Voper
------------------------2 8 1–( )8 8 1+( )2
------------------------------- 0.297= =
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 14 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Vstate1(t) = C1(t) − R1(t).
Vstate2(t) = C2(t) − R2(t).
Fig 9. LCD drive mode waveform for 1:16 multiplex rate
msa836
VDDV2V3V4V5VLCD
VDDV2V3V4V5VLCD
VDDV2V3V4V5VLCD
VDDV2V3V4V5VLCD
Tfr
ROW 1R1 (t)
ROW 2R2 (t)
COL 1C1 (t)
COL 2C2 (t)
dot matrix1:16 multiplex rate
state 1 (OFF)state 2 (ON)
0.2 Voper
0.2 Voper
0 V
Voper
Voper
Vstate 1(t)
Vstate 2(t)
0.2 Voper
0.2 Voper
0 V
Voper
Voper
0.6 Voper
0.6 Voper
Von RMS( )Voper
-----------------------116------
16 1–
16 16 1+( )------------------------------+ 0.316==
Voff RMS( )Voper
------------------------2 16 1–( )16 16 1+( )2
------------------------------------- 0.254= =
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 15 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
8.5 Oscillator
8.5.1 Internal clock
The clock signal for the system may be generated by the internal oscillator and prescaler.The frequency is determined by the value of the resistor Rext(OSC), see Figure 10. Fornormal use a value of 330 kΩ is recommended. The clock signal, for cascadedPCF8579s, is output at CLK and has a frequency of 1⁄6 (multiplex rate 1:8, 1:16 and 1:32)or 1⁄8 (multiplex rate 1:24) of the oscillator frequency.
8.5.2 External clock
If an external clock is used, OSC must be connected to VDD and the external clock signalto CLK. Table 8 summarizes the nominal CLK and SYNC frequencies.
[1] A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
[2] Rext(OSC) = 330 kΩ.
8.6 Timing generatorThe timing generator of the PCF8578 organizes the internal data flow of the device andgenerates the LCD frame synchronization pulse SYNC, whose period is an integermultiple of the clock period. In cascaded applications, this signal maintains the correcttiming relationship between the PCF8578 and PCF8579s in the system.
To avoid capacitive coupling, which could adversely affect oscillator stability, Rext(OSC) should beplaced as closely as possible to the OSC pin. If this proves to be a problem, a filtering capacitormay be connected in parallel to Rext(OSC).
Fig 10. Oscillator frequency as a function of external oscillator resistor, R ext(OSC)
10
msa837
1
103
102
102 103 104
10
fosc(kHz)
Rext(OSC) (kΩ)
Table 8. Signal frequencies required for nominal 64 Hz frame frequency [1]
Oscillator frequency,fosc (Hz)[2]
Frame frequency,ffr (Hz)
Multiplex rate,(1:n)
Division ratio Clock frequency,fclk (Hz)
12288 64 1:8, 1:16, 1:32 6 2048
12288 64 1:24 8 1536
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 16 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
8.7 Row and column driversOutputs R0 to R7 and C32 to C39 are fixed as row and column drivers respectively. Theremaining 24 outputs R8/C8 to R31/C31 are programmable and may be configured (inblocks of 8) to be either row or column drivers. The row select signal is producedsequentially at each output from R0 up to the number defined by the multiplex rate (seeTable 4). In mixed mode the remaining outputs are configured as columns. In row mode allprogrammable outputs (R8/C8 to R31/C31) are defined as row drivers and the outputsC32 to C39 should be left open-circuit.
Using a 1:16 multiplex rate, two sets of row outputs are driven, thus facilitating split-screenconfigurations, i.e. a row select pulse appears simultaneously at R0 and R16/C16, R1 andR17/C17 etc. Similarly, using a multiplex rate of 1:8, four sets of row outputs are drivensimultaneously. Driver outputs must be connected directly to the LCD. Unused outputsshould be left open circuit.
Depending on the multiplex rate the following outputs are rows:
• In MUX 1:8 R0 to R7
• In MUX 1:16 R0 to R15/C15
• In MUX 1:24 R0 to R23/C23
• In MUX 1:32 R0 to R31/C31
The configuration of the outputs (row or column) and the selection of the appropriatedriver waveforms are controlled by the display mode controller.
8.8 Characteristics of the I 2C-busThe I2C-bus is for bidirectional, two-line communication between different ICs or modules.The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL) which must beconnected to a positive supply via a pull-up resistor. Data transfer may be initiated onlywhen the bus is not busy.
8.8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remainstable during the HIGH period of the clock pulse as changes in the data line at thismoment will be interpreted as control signals.
8.8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOWtransition of the data line, while the clock is HIGH, is defined as the START condition (S).A LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the STOPcondition (P).
8.8.3 System configuration
A device transmitting a message is a transmitter, a device receiving a message is thereceiver. The device that controls the message flow is the master and the devices whichare controlled by the master are the slaves.
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 17 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
8.8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions fromtransmitter to receiver is unlimited. Each data byte of eight bits is followed by oneacknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,whereas the master generates an extra acknowledge related clock pulse. A slave receiverwhich is addressed must generate an acknowledge after the reception of each byte. Alsoa master must generate an acknowledge after the reception of each byte that has beenclocked out of the slave transmitter. The device that acknowledges must pull down theSDA line during the acknowledge clock pulse, so that the SDA line is stable LOW duringthe HIGH period of the acknowledge related clock pulse (set-up and hold times must betaken into consideration). A master receiver must signal the end of a data transmission tothe transmitter by not generating an acknowledge on the last byte that has been clockedout of the slave. In this event the transmitter must leave the data line HIGH to enable themaster to generate a STOP condition.
Fig 11. Bit transfer
Fig 12. Definition of START and STOP condition
mba607
data linestable;
data valid
changeof dataallowed
SDA
SCL
mba608
SDA
SCLP
STOP condition
S
START condition
Fig 13. System configuration
mba605
MASTERTRANSMITTER /
RECEIVER
SLAVERECEIVER
SLAVETRANSMITTER /
RECEIVER
MASTERTRANSMITTER
MASTERTRANSMITTER /
RECEIVER
SDA
SCL
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 18 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
8.8.5 I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave address, commands and displaydata bytes. It performs the conversion of the data input (serial-to-parallel) and the dataoutput (parallel-to-serial). The PCF8578 acts as an I2C-bus slave transmitter/receiver inmixed mode, and as a slave receiver in row mode. A slave device cannot control buscommunication.
8.8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters areprovided on the SDA and SCL lines.
8.8.7 I2C-bus protocol
Two 7-bit slave addresses (0111 100 and 0111 101) are reserved for both the PCF8578and PCF8579. The least significant bit of the slave address is set by connecting input SA0to either logic 0 (VSS) or logic 1 (VDD). Therefore, two types of PCF8578 or PCF8579 canbe distinguished on the same I2C-bus which allows:
1. One PCF8578 to operate with up to 32 PCF8579s on the same I2C-bus for very largeapplications.
2. The use of two types of LCD multiplex schemes on the same I2C-bus.
In most applications the PCF8578 will have the same slave address as the PCF8579.
The I2C-bus protocol is shown in Figure 15. All communications are initiated with a STARTcondition (S) from the I2C-bus master, which is followed by the desired slave address andread/write bit. All devices with this slave address acknowledge in parallel. All other devicesignore the bus transfer.
In WRITE mode (indicated by setting the read/write bit LOW) one or more commandsfollow the slave address acknowledgement. The commands are also acknowledged by alladdressed devices on the bus. The last command must clear the continuation bit C.After the last command a series of data bytes may follow. The acknowledgement aftereach byte is made only by the (A0, A1, A2 and A3) addressed PCF8579 or PCF8578 withits implicit subaddress 0. After the last data byte has been acknowledged, the I2C-busmaster issues a STOP condition (P).
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig 14. Acknowledgement on the I 2C-bus
mba606
STARTcondition
S
SCL FROMMASTER
DATA OUTPUTBY TRANSMITTER
DATA OUTPUTBY RECEIVER
clock pulse foracknowledgement
1 2 8 9
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 19 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read fromthe RAM following the slave address acknowledgement. After this acknowledgement themaster transmitter becomes a master receiver and the PCF8578 becomes a slavetransmitter. The master receiver must acknowledge the reception of each byte in turn. The
a. Master transmits to slave receiver (WRITE mode)
b. Master reads after sending command string (write commands; read data)
c. Master reads slave immediately after sending slave address (READ mode)
Fig 15. I2C-bus protocol
msa830
SA0
S 0 1 1 1 1 0 0 A C COMMAND A PADISPLAY DATA
slave address
/R W
acknowledge byall addressed
PCF8578s / PCF8579s
acknowledgeby A0, A1, A2 and A3 selected PCF8578s /
PCF8579s only
n ≥ 0 byte(s)n ≥ 0 byte(s)1 byte
update data pointersand if necessary,
subaddress counter(a)
msa832
SA0
S 0 1 1 1 1 0 0 A C COMMAND A
slave address
/R W
acknowledge byall addressed
PCF8578s / PCF8579s
n ≥ 1 byte
(b)
ADATASA0
S 0 1 1 1 1 0 1 A
slave address
/R W
P1DATA
n bytes last byte
update data pointersand if necessary
subaddress counter
acknowledgefrom master
no acknowledgefrom master
at this moment mastertransmitter becomes amaster receiver andPCF8578/PCF8579 slavereceiver becomes aslave transmitter
msa831
SA0
S 0 1 1 1 1 0 1 A DATA A P1DATA
slave address
/R W
acknowledge byall addressed
PCF8578s / PCF8579s
last byten bytes
update data pointersand if necessary,
subaddress counter(c)
acknowledgefrom master
no acknowledgefrom master
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 20 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
master receiver must signal an end of data to the slave transmitter, by not generating anacknowledge on the last byte clocked out of the slave. The slave transmitter then leavesthe data line HIGH, enabling the master to generate a STOP condition (P).
Display bytes are written into, or read from the RAM at the address specified by the datapointer and subaddress counter. Both the data pointer and subaddress counter areautomatically incremented, enabling a stream of data to be transferred either to, or fromthe intended devices.
In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3)are connected to VSS or VDD to represent the desired hardware subaddress code. If two ormore devices share the same slave address, then each device must be allocated to aunique hardware subaddress.
8.9 Display RAMThe PCF8578 contains a 32 × 40-bit static RAM which stores the display data. The RAMis divided into 4 banks of 40 bytes (4 × 8 × 40 bits). During RAM access, data istransferred to and from the RAM via the I2C-bus. The first eight columns of data (0 to 7)cannot be displayed but are available for general data storage and provide compatibilitywith the PCF8579. There is a direct correspondence between X-address and columnoutput number.
8.9.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. Thisallows an individual data byte or a series of data bytes to be written into, or read from, thedisplay RAM, controlled by commands sent on the I2C-bus.
8.9.2 Subaddress counter
The storage and retrieval of display data is dependent on the content of the subaddresscounter. Storage takes place only when the contents of the subaddress counter matchwith the hardware subaddress. The hardware subaddress of the PCF8578, valid in mixedmode only, is fixed at 0000.
8.10 Command decoderThe command decoder identifies command bytes that arrive on the I2C-bus.
The five commands available to the PCF8578 are defined in Table 9.
The most-significant bit of a command is the continuation bit C (see Table 10 andFigure 16). Commands are transferred in WRITE mode only.
Table 9. Definition of PCF8578 commands
Command Operation code Reference
Bit 7 6 5 4 3 2 1 0
set-mode C 1 0 T E[1:0] M[1:0] Table 11
set-start-bank C 1 1 1 1 1 B[1:0] Table 12
device-select C 1 1 0 A[3:0] Table 13
RAM-access C 1 1 1 G[1:0] Y[1:0] Table 14
load-X-address C 0 X[5:0] Table 15
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 21 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Table 10. C bit description
Bit Symbol Value Description
7 C continue bit
0 last control byte in the transfer; next byte will be regardedas display data
1 control bytes continue; next byte will be a command too
C = 0; last command.
C = 1; commands continue.
Fig 16. General information of command byte
Table 11. Set-mode - command bit description
Bit Symbol Value Description
7 C 0, 1 see Table 10
6, 5 - 10 fixed value
4 T display mode
0 row mode
1 mixed mode
3, 2 E[1:0] display status
00 blank
01 normal
10 all segments on
11 inverse video
1, 0 M[1:0] LCD drive mode
01 1:8 MUX (8 rows)
10 1:16 MUX (16 rows)
11 1:24 MUX (24 rows)
00 1:32 MUX (32 rows)
msa833
REST OF OPCODEC
MSB LSB
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 22 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
[1] Useful for scrolling, pseudo-motion and background preparation of new display content.
[1] Values shown in decimal.
[1] See operation code for set-start-bank in Table 12.
[2] Values shown in decimal.
Table 12. Set-start-bank - command bit description
Bit Symbol Value Description
7 C 0, 1 see Table 10
6 to 2 - 11111 fixed value
1, 0 B[1:0] start bank pointer (see Figure 20)[1]
00 bank 0
01 bank 1
10 bank 2
11 bank 3
Table 13. Device-select - command bit description
Bit Symbol Value Description
7 C 0, 1 see Table 10
6 to 4 - 110 fixed value
3 to 0 A[3:0] 0 to 15[1] hardware subaddress;
4 bit binary value; transferred to the subaddresscounter to define one of sixteen hardwaresubaddresses
Table 14. RAM-access - command bit description
Bit Symbol Value Description
7 C 0, 1 see Table 10
6 to 4 - 111 fixed value
3, 2 G[1:0] RAM access mode;
defines the auto-increment behavior of theaddress for RAM access (see Figure 18)
00 character
01 half-graphic
10 full-graphic
11 not allowed[1]
1, 0 Y[1:0] 0 to 3[2] RAM row address;
two bits of immediate data, transferred to theY-address pointer to define one of four displayRAM rows (see Figure 17)
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 23 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
[1] Values shown in decimal.
8.11 RAM access
RAM operations are only possible when the PCF8578 is in mixed mode. In this event itshardware subaddress is internally fixed at 0000 and the hardware subaddresses of anyPCF8579 used in conjunction with the PCF8578 must start at 0001.
There are three RAM-access modes:
• Character
• Half-graphic
• Full-graphic
These modes are specified by the bits G[1:0] of the RAM-access command. TheRAM-access command controls the order in which data is written to or read from the RAM(see Figure 18).
To store RAM data, the user specifies the location into which the first byte will be loaded(see Figure 19):
• Device subaddress (specified by the device-select command)
• RAM X-address (specified by the bits X[5:0] of the load-X-address command)
• RAM bank (specified by the bits Y[1:0] of the RAM-access command)
Subsequent data bytes will be written or read according to the chosen RAM-access mode.Device subaddresses are automatically incremented between devices until the last deviceis reached. If the last device has subaddress 15, further display data transfers will lead toa wrap-around of the subaddress to 0.
Table 15. Load-X-address - command bit description
Bit Symbol Value Description
7 C 0, 1 see Table 10
6 - 0 fixed value
5 to 0 X[5:0] 0 to 39[1] RAM column address;
six bits of immediate data, transferred to theX-address pointer to define one of forty displayRAM columns (see Figure 17)
Fig 17. RAM addressing scheme
001aaj920
LSB
1 byte
0 X address X max
0
Y max
Y address
MSB
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 24 of 46
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PC
F8578_6
Product data shee
NX
P S
emiconductors
PC
F8578
LCD
row/colum
n driver for dot matrix graphic displays
a849
LSB
MSB
bank 0
bank 1
bank 2
bank 3
PCF8578/PCF8579 PCF8579
© N
XP
B.V. 2009. A
ll rights reserved.
tR
ev. 06 — 5 M
ay 200925 of 46 Fig 18. RAM access mode
ms
0 1 2 3 4 5 6 7 8 9 10 11
0 2 4 6 8 10 12 14 16 18 20 22
1 3 5 7 9 11 13 15 17 19 21 23
0 4 8 12 16 20 24 28 32 36 40 44
1 5 9 13 17 21 25 29 33 37 41 45
2 6 10 14 18 22 26 30 34 38 42 46
3 7 11 15 19 23 27 31 35 39 43 47
RAM data bytes arewritten or read asindicated above
full-graphic mode
PCF8578/PCF8579 system RAM1 ≤ k ≤ 16
half-graphic mode
character mode
1 byte
4 bytesRAM
2 bytes
4 bytes
40-bits
driver 1 driver 2 driver k
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PC
F8578_6
Product data shee
NX
P S
emiconductors
PC
F8578
LCD
row/colum
n driver for dot matrix graphic displays
msa835
SA0
0 1 A
ress
/R W
DATA A
A DATA A
© N
XP
B.V. 2009. A
ll rights reserved.
tR
ev. 06 — 5 M
ay 200926 of 46 Fig 19. Example of commands specifying initial data byte RAM locations
SA0
S 0 1 1 1 1 0 0 A
slave address
/R W
01 1 0 1 1 0 A
DEVICE SELECT
1 00 0 0 1 0 0 A
LOAD X-ADDRESS
1 11 1 1 0 0 0 A
RAM ACCESS
0
last command
S 0 1 1 1 1
slave add
READ
WRITEDATA
DEVICE SELECT:subaddress 12
RAM ACCESS:
character modebank 1
LOAD X-ADDRESS: X-address = 8
RAM
bank 0
bank 1
bank 2
bank 3
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
8.12 Display controlThe display is generated by continuously shifting rows of RAM data to the dot matrix LCDvia the column outputs. The number of rows scanned depends on the multiplex rate set bybits M[1:0] of the set-mode command.
1:32 multiplex rate and start bank = 2.
Fig 20. Relationship between display and set-start-bank
msa851
bank 0
top of LCD
bank 1
bank 2
bank 3
LCD
RAM
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 27 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
The display status (all dots on or off and normal or inverse video) is set by the bits E[1:0]of the set-mode command. For bank switching, the RAM bank corresponding to the top ofthe display is set by the bits B[1:0] of the set-start-bank command. This is shown inFigure 20. This feature is useful when scrolling in alphanumeric applications.
9. Limiting values
[1] According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to bestored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.
Table 16. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.5 +8.0 V
VLCD LCD supply voltage VDD − 11 +8.0 V
VI input voltage VDD related;
on pins SDA, SCL,CLK, TEST, SA0and OSC
−0.5 +8.0 V
VLCD related;
V2 to V5
VDD − 11 +8.0 V
VO output voltage VDD related;
SYNC and CLK
−0.5 +8.0 V
VLCD related;
R0 to R7, R8/C8 toR31/C31 and C32to C39
VDD − 11 +8.0 V
II input current −10 +10 mA
IO output current −10 +10 mA
IDD supply current −50 +50 mA
IDD(LCD) LCD supply current −50 +50 mA
ISS ground supply current −50 +50 mA
Ptot total power dissipation per package - 400 mW
Po output power - 100 mW
Tstg storage temperature [1] −65 +150 °C
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 28 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
10. Static characteristics
[1] Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50 % duty factor.
[2] Resets all logic when VDD < VPOR.
[3] Periodically sampled; not 100 % tested.
[4] Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input (V2 to V5, VDD and VLCD)when the specified current flows through one output under the following conditions (see Table 6 on page 11):
a) Voper = VDD − VLCD = 9 V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2 − VLCD ≥ 6.65 V; V5 − VLCD ≤ 2.35 V; Iload = 150 µA.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; Iload = 100 µA.
Table 17. Static characteristicsVDD = 2.5 V to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 2.5 - 6.0 V
VLCD LCD supply voltage VDD − 9 - VDD − 3.5 V
IDD supply current external clock;
fclk = 2 kHz
[1] - 6 15 µA
internal clock;
Rext(OSC) = 330 kΩ- 20 50 µA
VPOR power-on reset voltage [2] 0.8 1.3 1.8 V
Logic
VIL LOW-level input voltage VSS - 0.3VDD V
VIH HIGH-level input voltage 0.7VDD - VDD V
IOL LOW-level output current at pins SYNC and CLK;VOL = 1 V; VDD = 5 V
1 - - mA
at pin SDA;
VOL = 0.4 V; VDD = 5 V
3 - - mA
IOH HIGH-level output current at pins SYNC and CLK;VOH = 4 V; VDD = 5 V;
- - −1 mA
IL leakage current at pins SDA, SCL, SYNC,CLK, TEST and SA0;Vi = VDD or VSS
−1 - +1 mA
at pin OSC;Vi = VDD
−1 - +1 µA
Ci capacitance for each I/O pin [3] - - 5 pF
LCD outputs
IL leakage current at pins V2 to V5;Vi = VDD or VLCD
−2 - +2 µA
Voffset(DC) DC offset voltage on pins R0 to R7, R8/C8 toR31/C31 and C32 to C39
- ±20 - mV
RO output resistance on row output pins: R0 toR7 and R8/C8 to R31/C31
[4] - 1.5 3 kΩ
on column output pins:R8/C8 to R31/C31 and C32to C39
[4] - 3 6 kΩ
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 29 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
11. Dynamic characteristics
Table 18. Dynamic characteristicsAll timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 V to 6 V; VSS = 0 V;VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fclk clock frequency at multiplex rate 1:8, 1:16and 1:32;Rext(OSC) = 330 kΩ;VDD = 6 V
1.2 2.1 3.3 kHz
at multiplex rate 1:24;Rext(OSC) = 330 kΩ;VDD = 6 V
0.9 1.6 2.5 kHz
tPD(SYNC_N) SYNC propagation delay - - 500 ns
tPD(drv) driver propagation delay VDD − VLCD = 9 V;with test load of 45 pF
- - 100 µs
I2C-bus
fSCL SCL clock frequency - - 100 kHz
tw(spike) spike pulse width - - 100 ns
tBUF bus free time between a STOPand START condition
4.7 - - µs
tSU;STA set-up time for a repeated STARTcondition
4.7 - - µs
tHD;STA hold time (repeated) STARTcondition
4.0 4.0 - µs
tLOW LOW period of the SCL clock 4.7 - - µs
tHIGH HIGH period of the SCL clock 4.0 - - µs
tr rise time of both SDA and SCLsignals
- - 1 µs
tf fall time of both SDA and SCLsignals
- - 0.3 µs
tSU;DAT data set-up time 250 - - ns
tHD;DAT data hold time 0 - - ns
tSU;STO set-up time for STOP condition 4.0 - - µs
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 30 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Fig 21. Driver timing waveforms
Fig 22. I2C-bus timing waveforms
msa834
0.7 VDD
0.3 VDD
1/fclk
tPD(SYNC_N)
0.7 VDD
0.3 VDDSYNC
CLK
0.5 V
0.5 V
tPD(drv)
C39 to C32,R31/C31 to R8/C8
and R7 to R0(VDD − VLCD = 9 V)
tPD(SYNC_N)
SDA
mga728
SDA
SCL
tSU;STAtSU;STO
tHD;STA
tBUF tLOW
tHD;DAT tHIGHtr
tf
tSU;DAT
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 31 of 46
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
PC
F8578_6
Product data shee
NX
P S
emiconducto
12.A
pplication in
t
rsP
CF
8578LC
D row
/column driver for dot m
atrix graphic displays
formation
msa844
© N
XP
B.V. 2009. A
ll rights reserved.
Rev. 06 —
5 May 2009
32 of 46 Fig 23. Stand alone application using 8 rows and 32 columns
OSCSDASA0
CLKSYNC VLCDSCLVSS
VDD
PCF8578
V2 V3 V4 V5
LCD DISPLAY
R7 R8/C8
R9/C9
R10/C10
R11/C11
R12/C12
R13/C13
R14/C14
R15/C15
R16/C16
R17/C17
R18/C18
R19/C19
R20/C20
R21/C21
R22/C22
R23/C23
R24/C24
R25/C25
R26/C26
R6R5R4R3R2R1R0 R27/C27
C32R31/C31
R30/C30
R29/C29
R28/C28C33C34C35C36C37C38C39n.c.n.c.TEST
Rext(OSC)
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Fig 24. Segment driver application for up to 384 segments
0 16 17 39
0
1
2
3
R8
R15
LCD
DISPLAY RAMPCF8578
Bank
(Using 1:16 mux, the first character data must be loaded in bank 0 and 1 starting at byte number 16)
one line of 24 digits 7 segmentone line of 12 digits star-burst (mux 1:16) Total: 384 segments
PCF8578: Segment Driver ApplicationR0
R7
a
b
c
d
e
fg
dp
abfgceddp
1-byte
LSB
MSB
112
mlb423
(1)
C16 C17 C39
ALTERNATE DISPLAY BANK
ALTERNATE DISPLAY BANK
FREE RAM
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 33 of 46
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PC
F8578_6
Product data shee
NX
P S
emiconductors
PC
F8578
LCD
row/colum
n driver for dot matrix graphic displays
VLCD
VDD
VSS
VSS
VSS
V3
V4
SCL SDA SA0CLKSYNC
A0
A1
A2
A3
PCF8579#k
40columns subaddress k−1
≤ 16)
msa845
© N
XP
B.V. 2009. A
ll rights reserved.
tR
ev. 06 — 5 M
ay 200934 of 46 Fig 25. Typical LCD driver system with 1:32 multiplex rate
Rext(OSC)OSC
SCL SDA SA0CLKSYNC
A0
A1
A2
A3
PCF8579#1
40columns subaddress 0
SCLSDA
SA0
CLK SYNC
PCF8578(ROW MODE)
VDD
VDD
VLCD
VLCD VLCD VLCD
VDD
VDD VDD VDD VDD VDD
VSS
VSS
VSS VSS VSS VSS VSS
VSS
VSS
VSS
V2
V3
V3
V4
V4
V3
V4
V5
unused columns
8
SCLSDA
32
rows
R
R
R
R
C
C
C
C
C
SCL SDA SA0CLKSYNC
A0
A1
A2
A3
PCF8579#2
40columns subaddress 1
1:32 multiplex rate32 × 40 × k dots (k(20480 dots max.)
LCD DISPLAY
(4 2 3)R
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PC
F8578_6
Product data shee
NX
P S
emiconductors
PC
F8578
LCD
row/colum
n driver for dot matrix graphic displays
SCLSDA CLK SYNC
PCF8579#1
40columns
SCL SDA SA0CLKSYNC
A0
A1
A2
A3
PCF8579#k
40columns subaddress k 1
msa847
V3
V4
VDD VDD
VSS
VSS
VLCD
VSS
© N
XP
B.V. 2009. A
ll rights reserved.
tR
ev. 06 — 5 M
ay 200935 of 46 Fig 26. Split screen application with 1:16 multiplex rate for improved contrast
OSC
SCL SDA SA0CLKSYNC
A0
A1
A2
A3
PCF8579#1
40columns subaddress 0
SCLSDA
SA0
CLK SYNC
PCF8578(ROW MODE) unused columns
16
8
rows
SCLSDA
1:16 multiplex rate16 × 40 × k dots (k ≤ 16)(10240 dots max.)
16
rows
R
R
R
R
R
C
C
C
C
C
SA0
A0
A1
A2
A3
subaddress 0
SCLSDASA0 CLK SYNC
A0
A1
A2
A3
PCF8579
40columns
subaddress k 1
#k
SCL SDA SA0CLKSYNC
A0
A1
A2
A3
PCF8579#2
40columns subaddress 1
1:16 multiplex rate16 × 40 × k dots (k ≤ 16)(10240 dots max.)
LCD DISPLAY
SCLSDASA0 CLK SYNC
A0
A1
A2
A3
PCF8579#2
40columns
subaddress 1
Rext(OSC)
V3
V4
VDD
VDD VDD
VSS
VSS
VLCD
V3
V4
VDD
VDD VDD
VSS
VSS
VLCD
VDD
V3
V4
VDDVDD
VSS
VSS
VLCD
V3
V4
VDDVDD
VSS
VSS
VSS
VLCD
V3
V4
VDDVDD
VSS
VSS
VSS
VLCD
V3
V2
V4
V5
VDD
VDD
VDD
VSS
VSS
VSS/VDD
VSS
VLCD
VLCD
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PC
F8578_6
Product data shee
NX
P S
emiconductors
PC
F8578
LCD
row/colum
n driver for dot matrix graphic displays
SCLSDA CLK SYNC
PCF8579#1
40columns
V3
V4
VDD VDD
VSS
VSS
VLCD
VSS
SCL SDA SA0CLKSYNC
A0
A1
A2
A3
PCF8579#k
40columns subaddress k 1
32
msa846
© N
XP
B.V. 2009. A
ll rights reserved.
tR
ev. 06 — 5 M
ay 200936 of 46 Fig 27. Split screen application with 1:32 multiplex rate
Rext(OSC)
OSC
SCL SDA SA0CLKSYNC
A0
A1
A2
A3
PCF8579#1
40columns subaddress 0
SCLSDA
SA0
CLK SYNC
PCF8578(ROW MODE) unused columns
8
SCLSDA
1:32 multiplex rate32 × 40 × k dots (k ≤ 16)(20480 dots max.)
32
rows
R
R
R
R
C
C
C
C
C
SA0
A0
A1
A2
A3
subaddress 0
SCLSDASA0 CLK SYNC
V3
V4
A0
A1
A2
A3
PCF8579
40columns
VDD
VDD VDD
VSS
VSS
VLCD
V3
V4
VDD
VDD VDD
VSS
VSS
VLCD
VDD
V3
V4
VDDVDD
VSS
VSS
VLCD
V3
V4
VDDVDD
VSS
VSS
VSS
VLCD
V3
V4
VDDVDD
VSS
VSS
VSS
VLCD
V3
V2
V4
V5
VDD
VDD
VDD
VSS
VSS
VSS/VDD
VSS
VLCD
VLCD
subaddress k 1
#k
SCL SDA SA0CLKSYNC
A0
A1
A2
A3
PCF8579#2
40columns subaddress 1
1:32 multiplex rate32 × 40 × k dots (k ≤ 16)(20480 dots max.)
LCD DISPLAY
SCLSDASA0 CLK SYNC
A0
A1
A2
A3
PCF8579#2
40columns
subaddress 1
(4 2 3)R
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PC
F8578_6
Product data shee
NX
P S
emiconductors
PC
F8578
LCD
row/colum
n driver for dot matrix graphic displays
VSS
msa852
n.c.
C27 C28 C39
PCF8579
to otherPCF8579s
© N
XP
B.V. 2009. A
ll rights reserved.
tR
ev. 06 — 5 M
ay 200937 of 46 Fig 28. Example of wiring, single screen with 1:32 multiplex rate (PCF8578 in row driver mode)
SDA VLCD
SCL VDD
PCF8578
LCD DISPLAY
Rext(OSC)
n.c.n.c.
R31/C31
R0
RRRR(4 2 3)R
n.c.
C0 C27 C28 C39
PCF8579
C0
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
13. Package outline
Fig 29. Package outline SOT190-1 (VSO56) of PCF8578T/1
UNIT A1 A2 A3 bp c D (1) E(2) (1)e HE L L p Q Zywv θ
REFERENCESOUTLINEVERSION
EUROPEANPROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
0.30.1
3.02.8
0.250.420.30
0.220.14
21.6521.35
11.111.0
0.7515.815.2
1.451.30
0.900.55 7
0
o
o
0.1 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
1.61.4
SOT190-197-08-1103-02-19
w M
θ
AA1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
v M A
X
(A )3
A
y
56 29
281
pin 1 index
0.0120.004
0.120.11
0.0170.012
0.00870.0055
0.850.84
0.440.43
0.0295
2.25
0.0890.620.60
0.0570.051
0.0350.022
0.004
0.2
0.008 0.0040.0630.055
0.01
0 5 10 mm
scale
VSO56: plastic very small outline package; 56 leads SOT190-1
Amax.
3.3
0.13
Notes
1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 38 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Fig 30. Package outline SOT314-2 (LQFP64) of PCF8578H/1
UNITA
max. A1 A2 A3 bp c E(1) e HE L L p Zywv θ
REFERENCESOUTLINEVERSION
EUROPEANPROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.200.05
1.451.35
0.250.270.17
0.180.12
10.19.9
0.512.1511.85
1.451.05
70
o
o0.12 0.11 0.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.750.45
SOT314-2 MS-026136E1000-01-1903-02-25
D(1) (1)(1)
10.19.9
HD
12.1511.85
EZ
1.451.05
D
bpe
θ
EA1
A
Lp
detail X
L
(A )3
B
16
c
DH
bp
EH A2
v M B
D
ZD
A
ZE
e
v M A
X
1
64
49
48 33
32
17
y
pin 1 index
w M
w M
0 2.5 5 mm
scale
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 39 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
Fig 31. Package outline SOT357-1 (TQFP64) of PCF8578HT/1
UNITA
max. A1 A2 A3 bp c E(1) e HE L L p Zywv θ
REFERENCESOUTLINEVERSION
EUROPEANPROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.2 0.150.05
1.050.95
0.250.270.17
0.180.12
10.19.9
0.512.1511.85
1.451.05
70
o
o0.08 0.11 0.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.750.45
SOT357-1 137E10 MS-02600-01-1902-03-14
D(1) (1)(1)
10.19.9
HD
12.1511.85
EZ
1.451.05
D
bpe
θ
EA1A
Lp
detail X
L
(A )3
B
16
c
DH
bp
EHA2
v M B
D
ZD
A
ZE
e
v M A
X
1
64
49
48 33
32
17
y
pin 1 index
w M
w M
0 2.5 5 mm
scale
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm SOT357-1
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 40 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth accountof soldering ICs can be found in Application Note AN10365 “Surface mount reflowsoldering description”.
14.1 Introduction to solderingSoldering is one of the most common methods through which packages are attached toPrinted Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides boththe mechanical and the electrical connection. There is no single soldering method that isideal for all IC packages. Wave soldering is often preferred when through-hole andSurface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is notsuitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and highdensities that come with increased miniaturization.
14.2 Wave and reflow solderingWave soldering is a joining technology in which the joints are made by solder coming froma standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadlesspackages which have solder lands underneath the body, cannot be wave soldered. Also,leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed bycomponent placement and exposure to a temperature profile. Leaded packages,packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave solderingKey characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, boardtransport, the solder wave parameters, and the time during which components areexposed to the wave
• Solder bath specifications, including temperature and impurities
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 41 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
14.4 Reflow solderingKey characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads tohigher minimum peak temperatures (see Figure 32) than a SnPb process, thusreducing the process window
• Solder paste printing issues including smearing, release, and adjusting the processwindow for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board isheated to the peak temperature) and cooling down. It is imperative that the peaktemperature is high enough for the solder to make reliable solder joints (a solder pastecharacteristic). In addition, the peak temperature must be low enough that thepackages and/or boards are not damaged. The peak temperature of the packagedepends on package thickness and volume and is classified in accordance withTable 19 and 20
Moisture sensitivity precautions, as indicated on the packing, must be respected at alltimes.
Studies have shown that small packages reach higher temperatures during reflowsoldering, see Figure 32.
Table 19. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature ( °C)
Volume (mm 3)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220
Table 20. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature ( °C)
Volume (mm 3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 42 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
For further information on temperature profiles, refer to Application Note AN10365“Surface mount reflow soldering description”.
15. Abbreviations
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature= minimum soldering temperature
maximum peak temperature= MSL limit, damage level
peak temperature
Table 21. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DC Direct Current
I2C Inter-Integrated Circuit
IC Integrated Circuit
LCD Liquid Crystal Display
LSB Least Significant Bit
MSB Most Significant Bit
MSL Moisture Sensitivity Level
PCB Printed-Circuit Board
POR Power-On Reset
RC Resistance-Capacitance
RAM Random Access Memory
RMS Root Mean Square
SCL Serial Clock Line
SDA Serial Data Line
SMD Surface Mount Device
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 43 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
16. Revision history
Table 22. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCF8578_6 20090505 Product data sheet - PCF8578_5
Modifications: • The format of this data sheet has been redesigned to comply with the new identityguidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added package type TQFP64 (PCF8578HT/1)
• Removed bare die types
• Rearranged information in data sheet
• Corrected values for 1:32 multiplex mode in Table 4
• Changed letter symbols to NXP approved symbols
• Added RAM addressing scheme (Figure 17)
PCF8578_5 20030414 Product specification - PCF8578_4
PCF8578_4 19980908 Product specification - PCF8578_3
PCF8578_3 19970328 Product specification - PCF8578_2
PCF8578_2 19961028 Product specification - PCF8578_1
PCF8578_1 19940125 Product specification - -
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 44 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodifications or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences ofuse of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet is intendedfor quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full datasheet, which is available on request via the local NXP Semiconductors salesoffice. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate andreliable. However, NXP Semiconductors does not give any representations orwarranties, expressed or implied, as to the accuracy or completeness of suchinformation and shall have no liability for the consequences of use of suchinformation.
Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including withoutlimitation specifications and product descriptions, at any time and withoutnotice. This document supersedes and replaces all information supplied priorto the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure ormalfunction of an NXP Semiconductors product can reasonably be expectedto result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use ofNXP Semiconductors products in such equipment or applications andtherefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for thespecified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined inthe Absolute Maximum Ratings System of IEC 60134) may cause permanentdamage to the device. Limiting values are stress ratings only and operation ofthe device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limitingvalues for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are soldsubject to the general terms and conditions of commercial sale, as publishedat http://www.nxp.com/profile/terms, including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case ofany inconsistency or conflict between information in this document and suchterms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance or thegrant, conveyance or implication of any license under any copyrights, patentsor other industrial or intellectual property rights.
Export control — This document as well as the item(s) described hereinmay be subject to export control regulations. Export might require a priorauthorization from national authorities.
17.4 TrademarksNotice: All referenced brands, product names, service names and trademarksare the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www .nxp.com
For sales office addresses, please send an email to: salesad [email protected]
Document status [1] [2] Product status [3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
PCF8578_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 5 May 2009 45 of 46
NXP Semiconductors PCF8578LCD row/column driver for dot matrix graphic displays
19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ordering information . . . . . . . . . . . . . . . . . . . . . 25 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pinning information . . . . . . . . . . . . . . . . . . . . . . 47.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 78 Functional description . . . . . . . . . . . . . . . . . . . 88.1 Display configurations. . . . . . . . . . . . . . . . . . . . 88.2 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 108.3 Multiplexed LCD bias generation . . . . . . . . . . 108.4 LCD drive mode waveforms . . . . . . . . . . . . . . 138.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168.5.1 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 168.5.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 168.6 Timing generator. . . . . . . . . . . . . . . . . . . . . . . 168.7 Row and column drivers . . . . . . . . . . . . . . . . . 178.8 Characteristics of the I2C-bus. . . . . . . . . . . . . 178.8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 178.8.2 START and STOP conditions . . . . . . . . . . . . . 178.8.3 System configuration . . . . . . . . . . . . . . . . . . . 178.8.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 188.8.5 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 198.8.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 198.8.7 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 198.9 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 218.9.1 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 218.9.2 Subaddress counter . . . . . . . . . . . . . . . . . . . . 218.10 Command decoder . . . . . . . . . . . . . . . . . . . . . 218.11 RAM access . . . . . . . . . . . . . . . . . . . . . . . . . . 248.12 Display control . . . . . . . . . . . . . . . . . . . . . . . . 279 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 2810 Static characteristics. . . . . . . . . . . . . . . . . . . . 2911 Dynamic characteristics . . . . . . . . . . . . . . . . . 3012 Application information. . . . . . . . . . . . . . . . . . 3213 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 3814 Soldering of SMD packages . . . . . . . . . . . . . . 4114.1 Introduction to soldering . . . . . . . . . . . . . . . . . 4114.2 Wave and reflow soldering . . . . . . . . . . . . . . . 4114.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 4114.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 4215 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 4316 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 44
17 Legal information . . . . . . . . . . . . . . . . . . . . . . 4517.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 4517.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4517.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 4517.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 4518 Contact information . . . . . . . . . . . . . . . . . . . . 4519 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
© NXP B.V. 2009. All rights reserved.For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: [email protected]
Date of release: 5 May 2009
Document identifier: PCF8578_6
Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.