PCI Express® Transmitter Compliance and DebugPCE3 Datasheet

Features & BenefitsPCIe Test Support: Supports Compliance and Validation of PCIeGen1/2/3 Interfaces based on PCIe Base and CEM Specifications

Automated Setup: Automatically Set Up the Oscilloscope Horizontal andVertical Scales to Optimize Signal Quality for Accurate Analysis

Automated Acquisition / Waveform Management: Automatically Acquireand Save the Waveform as per the PCI-SIG-Recommended NamingConvention to Help Manage the Numerous Waveforms that need to beAcquired per Lane for Completing the Tx Test

Automated DUT Control: Automatically Control the Dut and Step Itthrough the Various Supported Speeds and Presets Necessary for TxTesting

De-Embedding: De-Embed the Effects of the Channel, Test Fixtures andCables to Provide Results that More Accurately Represent the Signal(Requires Option SLA Serial Data Link Analysis)

Test Selection: Select The Specification against Which to Perform theAnalysis, as well as Select Individual Tests or Groups of Tests to PerformTargeted Compliance Analysis for Failing Tests

SIGTEST Integration: Integrates the SIGTEST Dll to Perform theAnalysis of the Acquired Waveforms, Providing the Ability to Test aSystem using the PCI-SIG-Recommended Analysis Tool

Reporting: Compile all the Results of a Test Run into a CustomizableReport with Pass/Fail Results for Easy Analysis and Record Keeping

Pattern Matching: Verifies that the Correct Set of Compliance Patternsare sent by the Transmitter before Acquiring Signals for ComplianceAnalysis.

PHY Level protocol Decode: Decode and Display of PCIe Data ina Protocol-Aware View. A Time-Correlated Event Table View withWaveforms allows for Quickly Searching through Events of Interest.

Multi-Lane Testing: Perform Analysis on Multiple Lanes of PCI ExpressData using Differential Probes that Speed Up the Tx Analysis in aMulti-Lane System

Compliance And Debug: Provides a Toolkit of DPOJET-Based Setupsto Quickly Switch into Debug and Validation Mode in case a DUT FailsCompliance

Analysis And Debug Tools: Tektronix provides a Broad Range ofCompliance, Debug, and Validation Tools for Transmitter, Receiver andProtocol Testing

Datasheet

ApplicationsTektronix provides the most comprehensive solutions to serve the needs ofengineers designing PCI Express silicon and embedded systems as well asthose validating the physical-layer compliance of PCI Express devices tothe PCI Express Compliance Test Specification. PCE3 includes Gen1/2/3Compliance Testing and Electrical Validation for:

Root Complex

Endpoints

Switches

Bridges

Add-In Cards

System Boards

Embedded Systems

Express Module

Tektronix PCE3 application provides the most comprehensive solution forPCI Express Gen1/2/3 Transmitter compliance testing as well as debug andvalidation of PCI Express devices against the specifications. The PCE3application includes a TekExpress™ compliance automation solution thatintegrates SIGTEST from PCI-SIG as well as DPOJET-based PCI ExpressJitter and Eye Diagram analysis tools for debug purposes all in a singlesoftware package.

The PCE3 application is compatible with Tektronix DPO/DSA/MSO70000series oscilloscopes that are designed to meet the challenges of thenext generation of serial data standards such as PCI Express. Theseoscilloscopes provide the industry's leading vertical noise performance withthe highest number of effective bits (ENOB) and flattest frequency responseamong oscilloscopes in their class. Tektronix DPO/DSA/MSO 70000 seriesof oscilloscopes have been approved by PCI-SIG for compliance testing.

Compliance TestingThe PCI-SIG provides PCI Express compliance tests for testing PCIExpress systems and add-in cards. For a PCI Express system or a deviceto be placed on the Integrators List, the system or device must passinteroperability and compliance testing. For electrical validation PCI-SIGuses SIGTEST Post Capture Analysis Software that uses acquisition froman oscilloscope to perform the analysis. Manually capturing the requiredwaveforms and analyzing them is tedious, time consuming and error prone.

The TekExpress Automation for PCI Express Transmitter Compliancegreatly reduces the effort and accelerates the compliance testing forPCI Express systems and devices with several unique and innovativecapabilities.

TekExpress Automation software can control the DUT using a TektronixAFG and automatically cycle it through the various speeds, de-emphasisand Presets that are necessary for the compliance test. This eliminates theerror-prone manual push button approach that is normally used for DUTcontrol.

A complete test run requires tens of waveforms to be acquired at differentDUT settings. This will increase several folds depending on the numberof lanes that need to be analyzed. The ability to manage and store therequired data for analysis and future reference is an important criterion

TekExpress PCIe test selection for compliance analysis

TekExpress PCIe compliance analysis report generation

for any compliance solution. The TekExpress automation software, apartfrom adjusting the horizontal and vertical settings as well as the acquisitiondepth for optimal signal quality for accurate analysis, also makes managingthe multiple waveforms acquired for analysis easy. The SIGTEST DLL isintegrated into the solution and is used to analyze the acquired waveforms.This make results of the analysis consistent with the SIGTEST post captureanalysis software that is used at PCI-SIG workshops for compliance.

The TekExpress automation software also provides flexibility in selectingthe data rates, voltage swing, presets and the tests to run, it also providesthe option to de-embed the effects of the channel and the text fixtures andprovide an accurate representation of the signal at the pins as required bythe specification.

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PCI Express® Transmitter Compliance and Debug — PCE3

PCE3 base specification measurement suite

All the analysis results are compiled in an html-format report that caninclude pass/fail summary, eye diagrams, setup configuration, and usercomments. The contents of the report can be customized to includeinformation of interest such as append results and custom report generationbased on test name/pass fail/equalization.

Debug and ValidationIf a DUT or Add-In card fails compliance, the PCE3 application includes aDPOJET-based debug and analysis toolkit that is customized for debug andvalidation of PCI Express interfaces.

The new jitter measurements introduced with PCIe Gen3 provide separatelimits for data dependent (DDJ) and uncorrelated deterministic jitter(UDJDD). It is important to separate DDJ (which can be compensated withtransmitter and receiver equalization) and UDJDD (which can be caused byeffects such as crosstalk and power supply noise).

Apart from the above Jitter measurements Pulse Width Jitter (PWJ) isa new measurement that addresses the increased channel loss at 8Gb/s. The purpose of the PWJ measurement is to ensure that lone bitsmeet minimum pulse width requirements. All new jitter measurementimplement Q-scale extrapolation as defined in the base specification. PCE3

PCE3 CEM measurement analysis before channel, after channel, after CTLE, and DFE

provides the complete set of PCI Express 3.0 jitter measurements enablingsilicon designers to verify that their silicon meets the base specificationrequirements.

Furthermore, the base specification requirements are defined at the pins ofthe transmitter. Before the measurements are computed the test channelmust be de-embedded. De-embed filters can be easily created using SerialData Link Analysis software (SDLA) and then quickly entered into thePCE3 base specification measurement setup and saved for future use. Inaddition to jitter, PCE3 also provides voltage, package loss, and transmitterequalization measurements.

PCE3 leverages the channel modeling and receiver equalizationfunctionality of SDLA to support CEM measurements. Unlike othersolutions, PCE3 provides full visibility to the signal as it has been modifiedto embed the compliance channel and provide receiver equalization. Eyediagrams and measurements can be set up to visually see the resultsof channel embedding, CTLE application, and DFE. For example whendetermining the optimal RX Equalization settings (CTLE setting and DFEtap value) the resulting eye diagrams and measurements show the effectsof post processing on the acquired signal. Compliance measurements canthen be taken on the waveform.

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Datasheet

PCIe Gen 3 compliance pattern decoded with SR-PCIe

PCI Express Serial Triggering and Analysis(SR-PCIe)Decode and Display of PCIe data in a protocol-aware view with thecharacters and names that are familiar from the standard such as theordered sets: SKP, Electrical Idle, and EIEOS. A time correlated event tableview with waveform allows for quickly searching through events of interestsimultaneously. The PCIe data stream is integrated with serial bus triggerand search for PCIe gen 1 and 2 allows for triggering on information ofinterest.

Comprehensive Measurements for PCIeValidation, Debug, and PrecomplianceOption PCE3 provides measurements that span multiple test points andversions of the PCIe specification. All PCIe specifications, test points, andmeasurements supported are listed in the following sections.

Option PCE3 Provides Coverage for a Broad Set of PCIeSpecifications and Test Points

Test Method Spec Revision PCI ExpressSpecification

Title

Test PointsDefined

Rev 1.1 Base Specification Transmitter andReceiver

Rev 1.1 CEM Specification System and Add-inCard Reference

ClockRev 1.0 Express Module

SpecificationTransmitter Path

and System BoardRev 1.0 PCMCIA Express

Card StandardHost SystemTransmitter

Express CardTransmitter

Rev 1.1

Ver. 3.0 Rev 1.1 Mobile PCIExpress

Module (MXM)Electromechanical

Specification

PCI Express

Rev 1.0 External CablingSpecification

Transmitter andReceiver Path

Rev 2.0 Base Specification Transmitter andReceiver

Mobile Low-powerTransmitter

Rev 2.0 CEM Specification System and Add-inCard (3.5 and 6 dB

de-emphasis)

Rev 2.0

Ver. 3.0 Rev 1.1 Mobile PCIExpress

Module (MXM)Electromechanical

Specification

PCI Express

Rev 1.0 Base Specification TransmitterRev 3.0Rev 0.7 CEM Specification System and Add-in

Card

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PCI Express® Transmitter Compliance and Debug — PCE3

Characteristics

Supported Base Specification Measurements

Differential 8 GT/s Transmitter (Tx) Output Measurements

Parameter Symbol

Tx Voltage with No Tx Equalization VTX-NO-EQ

Minimum Swing during EIEOS VTX-EIEOS

Pseudo Package Loss ps21TX

Data-dependent Jitter TTX-DDJ

Tx Uncorrelated Deterministic Jitter TTX-UDJDD

Tx Uncorrelated Total Jitter TTX-UTJ

Deterministic DjDD Uncorrelated PulseWidth Jitter

TTX-UPW-DJDD

Total Uncorrelated Pulse Width Jitter TTX-UPW-TJ

Differential Transmitter (Tx) Output Measurements

Parameter Symbol(s) 2.5 GT/sRev 1.1/2.0

5 GT/sRev 2.0

Clock Recovery NA Specified SpecifiedUnit Interval UI Specified SpecifiedDifferential p-p TxVoltage Swing

VTX-DIFF-P-P

VTX-SWING

VTX-EYE-FULL

Specified Specified

Low-powerDifferential p-p TxVoltage Swing

VTX-SWING-LOW

VTX-EYE-HALF

Specified Specified

De-emphasizedOutput VoltageRatio

VTX-DE-RATIO Not Specified Specified

InstantaneousLane Pulse Width

TMIN-PULSE Not Specified Specified

Transmitter Eyeincluding All JitterSources

TTX-EYE

TTX-EYE-TJ

Specified Specified

Maximum Timebetween theJitter Medianand MaximumDeviation from theMedian

TTX-EYEMEDIAN-to-MAXJITTER Specified Specified

Deterministic Jitter TTX-DJ-DD Not Specified SpecifiedTx RMS Jitter<1.5 MHz

TTX-LF-RMS Not Specified Specified

D+/D– Tx OutputRise/Fall Time

TTX-RISE

TTX-FALL

Specified Specified

Tx Rise/FallMismatch

TRF-MISMATCH Not Specified Specified

AC Peak-to-PeakCommon ModeOutput Voltage

VTX-CM-AC-PP Not Specified Specified

AC Peak CommonMode OutputVoltage

VTX-CM-AC-P Specified Specified

Absolute Delta ofDC Common ModeVoltage betweenD+ and D–

VTX-CM-DC-LINE-DELTA Specified Specified

Differential Receiver (Rx) Input Measurements

Parameter Symbol(s) 2.5 GT/sRev 1.1/2.0

5 GT/sRev 2.0

Clock Recovery NA Specified Not SpecifiedUnit Interval UI Specified SpecifiedMinimum ReceiverEye Opening

VRX_EYE Specified Specified

ReceiverDeterministic Jitter– DJ

TRX_DJ_DD Not Specified Specified

Minimum WidthPulse at Rx

TRX-MIN-PULSE Not Specified Specified

Maximum Timebetween theJitter Medianand MaximumDeviation from theMedian

TTX-EYEMEDIAN-to-MAXJITTER Specified Not Specified

Rx AC CommonMode Voltage

VRX-CM-AC-P Specified Specified

Supported CEM Specification Measurements

Add-in Card Transmitter Path Compliance Measurements

Parameter Symbol

Transition Eye Voltage PCIe V-TXANontransition Eye Voltage PCIe V-TXA-dEye Width PCIe T-TXA

Add-in Card Transmitter Path Compliance Measurements

Parameter Symbol(s) 2.5 GT/sRev 1.1/2.0

5 GT/sRev 2.0

Clock Recovery NA Specified SpecifiedUnit Interval UI Specified SpecifiedEye Height ofTransition Bits

VTXA Specified Specified

Eye Height ofNontransition Bits

VTXA_d Specified Specified

Eye Width withSample Size of 106

UI

TTXA in Rev 1.1 Specified Not Specified

Jitter Eye Openingat BER 10–12

TTXA in Rev 2.0 Specified Specified

MaximumMedian-Max JitterOutlier with SampleSize of 106 UI

JTXA-MEDIAN-to-MAX-JITTER Specified Not Specified

Total Jitter atBER 10–12

TJ at BER 10–12 Not Specified Specified

Deterministic Jitterat BER 10–12

Max DJ Not Specified Specified

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Datasheet

System Board Transmitter Path Measurements

Parameter Symbol(s) 2.5 GT/sRev 1.1/2.0

5 GT/sRev 2.0

Clock Recovery NA Specified SpecifiedUnit Interval UI Specified SpecifiedEye Height ofTransition Bits

VTXS Specified Specified

Eye Height ofNontransition Bits

VTXS_d Specified Specified

Eye Width withSample Size of 106

UI

TTXS in Rev 1.1 Specified Not Specified

Jitter Eye Openingat BER 10–12

TTXS in Rev 2.0 Specified Specified

MaximumMedian-Max JitterOutlier with SampleSize of 106 UI

JTXA-MEDIAN-to-MAX-JITTER Specified Not Specified

Total Jitter atBER 10–12

TJ at BER 10–12 Not Specified Specified

Deterministic Jitterat BER 10–12

Max DJ Not Specified Specified

Reference Clock Measurements

Parameter Symbol 2.5 GT/sRev 1.1/2.0

Reference Clock Phase Jitter atBER 10–6

NA Specified

PCI ExpressModule™Measurements

ExpressModule Add-in Card Transmitter Path Measurements

Parameter Symbol Rev 1.0

Clock Recovery NA SpecifiedUnit Interval UI SpecifiedEye Height of Transition Bits VTXA SpecifiedEye Height of Nontransition Bits VTXA_d SpecifiedEye Width with Sample Size of 106 UI TTXA

in Rev 1.1Specified

Jitter Eye Opening at BER 10–12 NA SpecifiedMaximum Median-Max Jitter Outlierwith Sample Size of 106 UI

JTXA-MEDIAN-to-MAX-JITTER Specified

ExpressModule System Board Transmitter PathMeasurements

Parameter Symbol Gen1Rev 1.0

Clock Recovery NA SpecifiedUnit Interval UI SpecifiedEye Height of Transition Bits VTXS SpecifiedEye Height of Nontransition Bits VTXS_d SpecifiedEye Width with Sample Size of 106 UI TTXS SpecifiedJitter Eye Opening at BER 10–12 NA SpecifiedMaximum Median-Max Jitter Outlierwith Sample Size of 106 UI

JTXA-MEDIAN-to-MAX-JITTER Specified

PCI Express External Cabling Measurements

External Cabling Transmitter Path Measurements

Parameter Symbol Rev 1.0

Clock Recovery NA SpecifiedUnit Interval UI SpecifiedEye Height of Transition Bits VTXA SpecifiedEye Height of Nontransition Bits VTXA_d SpecifiedJitter Eye Opening at BER 10–12 TrxA at BER 10–12 SpecifiedEye Width with Sample Size of 106 UI TrxA at 106 Samples Specified

External Cabling Receiver Path Measurements

Parameter Symbol Gen1Rev 1.0

Clock Recovery NA SpecifiedUnit Interval UI SpecifiedEye Height of Transition Bits VRXA SpecifiedEye Height of Nontransition Bits VRXA_d SpecifiedJitter Eye Opening at BER 10–12 TrxA at BER 10–12 SpecifiedEye Width with Sample Size of 106 UI TrxA at 106 Samples Specified

PCMCIA ExpressCard™Measurements

ExpressCard – Module Transmitter Path Measurements

Parameter Symbol Release 1.0

Clock Recovery NA SpecifiedUnit Interval UI SpecifiedEye Height of Transition Bits VTXA SpecifiedEye Height of Nontransition Bits VTXA_d SpecifiedEye Width across Any 250 UIs TTXA Specified

ExpressCard™ – Host System Transmitter PathMeasurements

Parameter Symbol Release 1.0

Clock Recovery NA SpecifiedUnit Interval UI SpecifiedEye Height of Transition Bits VtxS SpecifiedEye Height of Nontransition Bits VtxS_d SpecifiedEye Width across Any 250 UIs TTxS Specified

MXMMeasurements

PCI Express Measurements*1

Parameter Symbol Release 1.1

Eye Height of Transition Bits VTXS SpecifiedEye Height of Nontransition Bits VTXS_d SpecifiedWidth at BER TTXS SpecifiedDeterministic Jitter DJ SpecifiedTotal Jitter TJ Specified

*1 All de-emphasis levels supported.

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PCI Express® Transmitter Compliance and Debug — PCE3

Ordering InformationRecommended DPO/DSA/MSO70000 Series oscilloscopes

2.5 Gb/s (PCI Express 1.0/1.1): DPO/DSA/MSO70000 Series(6 GHz or higher bandwidth models)

5.0 Gb/s (PCI Express 2.0): DPO/DSA/MSO70000 Series(12.5 GHz or higher bandwidth models)

8.0 Gb/s (PCI Express 3.0): DPO/DSA/MSO70000 Series(16 GHz or higher bandwidth models, minimum of 12.5 GHz isrecommended)

PCE3*2

PCI Express 3.0/2.0/1.x Physical-layer Test ApplicationModel New Instrument

OrdersProductUpgrades

FloatingLicenses

DPO/DSA/MSO70KSeries

Opt. PCE3 Opt. DPO-UP PCE3 Opt. DPOFL-PCE3

*2 Requires Option DJA (DPOJET Jitter and Eye Diagram Analysis) and Option SLA (Serial Data Link AnalysisAdvanced). DJA is standard on DSA70K Series oscilloscopes.

Recommended Accessories

Order Description

P7500 Series TriMode™ Differential ProbeOption SLA Serial Data Link Analysis Advanced (with

equalization)Option SLE Serial Data Link Analysis Essentials (no

equalization)

Recommended for DUT control

Order Description

Tektronix AFG3252 Arbitrary Function GeneratorSMP to SMP Matched cables

Recommended Test Fixtures

Order Description

CLB1*3 PCI Express Compliance Load Board (CLB) fortesting PCI Express platforms

CBB1*3 Rev 1.1 of the PCI Express Compliance BaseBoard (CBB) for testing PCI Express Add-in Cards

CLB2*3 PCI Express Compliance Load Board (CLB) fortesting PCI Express platforms(Supports testing of Rev 1.1/2.0)

CBB2*3 Rev 2.0 of the PCI Express Compliance BaseBoard (CBB) for testing PCI Express Add-in Cards(Supports testing of Rev 1.1/2.0)

CBB3*3 PCI Express Compliance Base Board (CBB)for testing PCI Express Add-in Cards (Supportstesting of Rev 1.1/2.0/3.0)

CLB3*3 PCI Express Compliance Load Board (CLB) fortesting PCI Express platforms(Supports testing of Rev1.1/2.0/3.0)

Matched SMA Cables 174-4944-XX

SMP-SMA Cables*4 71M-19K1-32S1-01000ACLB2/CBB2 Terminators*4 19K15R-001E4

*3 Available from PCI-SIG (http://www.pcisig.com).

*4 Available from Rosenberger (http://www.rosenberger.com/index.com.html).

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Datasheet

Additional Information

PCI Express 3.0 Receiver Testing

PCIe receiver test setup

A complete PCI Express 3.0 Receiver testing solution from Tektronix. Includesstressed pattern generation as required by PCI-SIG test specifications and supportfor automated clock multiplication and eye opening measurements. Automated DUTloopback control simplifies the testing process and reduces time to test results. Thereceiver testing solution also supports adding pre-emphasis to the stress pattern,common-mode interference testing, and PLL loop BW testing.

The Receiver testing solution consists of the following components:

BERTScope C Model for Pattern Generation, stressed eye sources, andError Detection

New DPP125C Option ECM that provides Eye opener, Clock doublerand clock Multiplier functionality

New BSAITS125 that provides CM/DM interference and compliant ISIchannels and programmable, variable expanded ISI with Opt EXP

New Opt PCIE8G PLL analysis for Gen1/2/3

New BSAPCI3 SW for Auto calibration, link training, and testing

MSO/DSA/DPO70000 Series Real-Time Oscilloscope for calibration

TLA7SA00 Series Protocol Analyzers

TLA7SA00 series instrument

TLA7SA00 data views

The TLA7SA00 Series logic protocol analyzer modules provide an innovativeapproach to PCI Express validation that spans all layers of the protocol from thephysical layer to the transaction layer. Feature rich software provides improvedinformation density for viewing statistical summary and protocol analysis usinginnovative Transaction and Summary Profile windows. Hardware capabilitiesincluding hardware acceleration, OpenEYE, ScopePHY, and FastSYNC provide fastaccess to data and helps shorten the time it takes to build confidence in the testsystem. Powerful trigger and filtering capabilities provide the ability to quickly focuson the data of interest. Provides a complete suite of probing solutions targeted forvarious form factors and applications.

Tektronix is registered to ISO 9001 and ISO 14001 by SRI Quality System Registrar.

Product(s) complies with IEEE Standard 488.1-1987, RS-232-C, and with TektronixStandard Codes and Formats.

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PCI Express® Transmitter Compliance and Debug — PCE3

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Datasheet Contact Tektronix:

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Finland +41 52 675 3777

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Italy 00800 2255 4835*

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Luxembourg +41 52 675 3777

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The Netherlands 00800 2255 4835*

Norway 800 16098

People’s Republic of China 400 820 5835

Poland +41 52 675 3777

Portugal 80 08 12370

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Russia & CIS +7 (495) 7484900

South Africa +41 52 675 3777

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Switzerland 00800 2255 4835*

Taiwan 886 (2) 2722 9622

United Kingdom & Ireland 00800 2255 4835*

USA 1 800 833 9200

* European toll-free number. If not accessible, call: +41 52 675 3777

Updated 10 February 2011

For Further Information. Tektronix maintains a comprehensive, constantly expandingcollection of application notes, technical briefs and other resources to help engineers workingon the cutting edge of technology. Please visit www.tektronix.com

Copyright © Tektronix, Inc. All rights reserved. Tektronix products are covered by U.S. and foreign patents,issued and pending. Information in this publication supersedes that in all previously published material.Specification and price change privileges reserved. TEKTRONIX and TEK are registered trademarks ofTektronix, Inc. All other trade names referenced are the service marks, trademarks, or registered trademarksof their respective companies.

11 Oct 2012 61W-24540-5

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