PCB Workshop using Orcad Lite Prof. George Law Objectiveglaw/PCBWorkshop/logic probe...

Prof. G. Law, CSUN

PCB Workshop using Orcad Lite Prof. George Law

Objective

To learn to use Orcad PCB Editor Lite to create a PCB board.

Development Tools

Orcad PCB Designer Lite

http://www.cadence.com/products/orcad/pages/downloads.aspx

(Request a DVD or download)

References

Orcad Design Flow Tutorial (included in Orcad PCB Designer Lite)

Useful PCB Editor Commands

1. To move PCB Part: Edit Move. Click the part and drag it to a new location. When done, right click and a pop up menu appears. Click done.

2. To cancel an operation: Right click and a pop up menu appears, click Oops or Cancel. Clicking Oops let you undo the current operation.

Download and Install ORCAD Lite version 16.6 in your own computer

Note: You need to download and install Orcad Lite version 16.6 on your own computer only if you plan to use Orcad off campus. You can always have access to the full version of Orcad in one of the Electrical and Computer Engineering labs.

1. Visit http://www.orcad.com/buy/try-orcad-for-free

2. Scroll down and fill Download Lite Request form with your information

All fields marked with an asterisk * must be filled!

3. Select OrCAD 16.6 Lite Software (All products, download)

4. Click Submit

5. Orcad acknowledges with “Your form has been submitted. An email has been sent to the address provided with more details.”

6. After a few minutes, check your email. If you don’t see the Orcad response with subject “Download links to your OrCAD software”, it may be in your spam folder. Open the Orcad email.

http://www.cadence.com/products/orcad/pages/downloads.aspx

http://www.orcad.com/buy/try-orcad-for-free

Prof. G. Law, CSUN

7. Click the Download link in the email.

8. Save 16.6_2015_OrCAD_Lite_All_Products.zip in a folder of your choice (size 1.7 GB). The download may take a few minutes, depending on your network speed.

9. Unzip 16.6_2015_OrCAD_Lite_All_Products.zip into a folder of your choice and run setup.exe.

10. Follow the Orcad Installshield wizard instructions to install Orcad Lite.

Guidelines 1. Avoid spaces in pathnames and filenames. That is, do not use “Logic Probe” as filename;

use “LogicProbe” or “Logic_Probe” as filename instead.

2. In naming nets, nodes, projects, or libraries, avoid using special characters such as *, ?, @, #, &, %, $, etc.

Note: Frequently save your design to avoid loss of hours of work! LogicProbe Folder Structure

1. Create a folder named Projects on a drive of your choice

2. In the Projects folder, create a folder named LogicProbe

3. In the LogicProbe folder, create a folder named MyFootPrint

4. Copy custom footprints files to .. \Projects\LogicProbe\MyFootPrint. Ask the instructor where the custom footprint files are located.

5. In the LogicProbe folder, create a folder named MyPadStack

6. Copy custom padstacks file to .. \Projects\LogicProbe\MyPadStack ..\Projects ..\Projects\LogicProbe

.. \Projects\LogicProbe\MyFootPrint

.. \Projects\LogicProbe\MyPadStack

Ask the instructor where the custom footprint files are located.

Prof. G. Law, CSUN

Create an Orcad Project 1. Launch Capture. 2. From the File menu, choose New --> Project. 3. In the New Project dialog box, specify the project name “LogicProbe”. 4. Select Analog or Mixed A/D as project type. An Analog or Mixed A/D project can easily be

simulated using PSpice. 5. Browse and specify the folder where you want the project files to be created.

6. Click OK.

7. In the Create PSpice Project dialog box, select the Create a blank project option button. A blank project has no libraries assigned to it yet.

8. Click OK. A project named LogicProbe will be created. Rename the schematic folder and the schematic name

1. In the Project Manager window, right-click on SCHEMATIC1.

2. From the pop-up menu, select Rename.

3. In the Rename Schematic dialog box, specify the name as SCHEMATIC.

4. Similarly, right-click on PAGE1 and from the pop-up menu select Rename.

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5. In the Rename Page dialog box, specify the page name as LogicProbe

6. Click OK.

The directory structure in the Project Manager window should look like the figure below after renaming: Create a Flat (one-page) LogicProbe Design

I. Place Title Block Information

Note: Use the LogicProbe schematic handout as a guide in placing the parts.

1. Double click LogicProbe: File -> Design Resources -> .\logicprobe.dsn -> Schematic -> LogicProbe.

2. After the blank LogicProbe schematic opens, pan to the lower left hand corner where the title block is located.

3. Click on the boundary of the Title block.

4. Right click on the title block and click edit property.

5. When the property editor window opens, click new column.

6. In the New Column pop up, enter “Author” in the name field and your name in the value field and click OK.

Before Rename After Rename

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7. Pan to the left and select Author column. Click display.

8. In the display property pop up, select Name and value. Click OK.

9. Pan to the right and select OrgName column. Click display.

10. In the display property pop up, select Name and value. Click OK.

11. Close Property Editor windows.

12. Rearrange the Author and OrgName by click and drag to the desired position.

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13. Click Title and enter “Logic Probe for CMOS and TTL” in the value field and click OK.

14. The completed TitleBlock should look similar to the one below:

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II. Place Parts A. Place Resistor part

1. On the menu bar, click Place -> Part. When Place part window opens, type R in the part box and click Place part icon.

2. Click anywhere on the schematic to place R1.

3. Click anywhere on the schematic to place R2,

4. Repeat step 3 to place R3, R4, …, R17, and R18 on the schematic. Click ESC key to end place mode.

5. Right click each resistor to orient it properly. Click and drag it to the location as shown in Logic Probe handout.

B. Place Capacitor part

1. On the menu bar, click Place -> Part. When Place part window opens, type C in the part box and click Place part icon.

2. Click anywhere on the schematic to place C1.

3. Click anywhere on the schematic to place C2.

4. Repeat step 3 to place C3, C4, and C5 on the schematic. Click ESC key to end place mode.

5. Right click each capacitor to orient it properly. Click and drag it to the location as shown in Logic Probe handout.

C. Place CON2 part

1. On the menu bar, click Place -> Part. When Place part window opens, scroll down to the lower part of the window and expand Search for the part.

2. Enter part name CON2 in Search For Box.

3. Browse to and select PSPICE folder under Orcad Lite installation folder.

4. Click Search for Part icon.

5. If CON2 part is found, it will show up in the Libraries box. If it is not found, repeat steps 3 and 4 but browse to and select the Library folder under Orcad Lite installation folder.

6. Click ADD button and click Add Part Icon.

7. Click anywhere on the schematic. Click ESC key (Escape key) to end place mode. Click and drag CON2 to the location as shown on the LogicProbe handout. Right click ICON2 and rotate it to get the correct orientation.

Prof. G. Law, CSUN

D. Place Other parts

1. On the menu bar, click Place -> Part. When Place part window opens, scroll down to the lower part of the window and expand Search for the part.

2. Enter the part name in Search For Part Box.

3. Browse to and select PSPICE folder under Orcad Lite installation folder.

4. Click Search for Part icon.

5. If the part is found, it will show up in the Libraries box. If it is not found, repeat steps 3 and 4 but browse to and select the Library folder under Orcad Lite installation folder.

6. Click ADD button and click Add Part Icon.

Expand Search part Icon

Add Part Icon

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7. Click anywhere on the schematic. Click ESC key (Escape key) to end place mode. Click and drag the part to the location as shown on the LogicProbe handout. Right click the part and rotate it to get the correct orientation.

8. Repeat steps D1 to D7 to place the other parts on the schematic. III. Change Pin numbers of Diodes

1. Select any D1N4148 diode (Click on a D1N4148 diode)

2. Edit -> Part

3. When the diode symbol appears, double click on the anode pin.

4. On the Pin Properties dialog box, change pin number from 1 to 2 and pin number from 1 to 2.

5. Click OK.

6. Double click on Cathode pin.

7. On the Pin Properties dialog box, change pin number from 2 to 1 and pin number from 2 to 1.

Anode Pin

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8. Click OK.

9. Close Part Edit window. On Save Part Instance dialog box, click Update All.

10. Click Yes to continue to save changes to the entire design.

IV. Change Pin numbers of M1 P-Channel MOSFET

1. Select M1 P-Channel MOSFET (Click on a IRF9140) 2. Edit -> Part

3. When the Mosfet symbol appears, double click on the drain pin.

4. On the Pin Properties dialog box, enter pin number 1.

Cathode Pin

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5. Click OK.

6. Double click on Gate pin.


8. Click OK.

9. Double click on Source pin.


11. Click OK.

12. Close Part Edit window. On Save Part Instance dialog box, click Update All.

Click Yes to continue to save changes to the entire design.

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V. Place VCC

1. On the menu bar, click Place -> Power. When Place Power window opens, select VCC/CAPSYM.

2. Click OK.

VI. Place Ground

1. On the menu bar, click Place -> Ground. When Place Ground window opens, select 0/CAPSYM.

2. Click OK.

VII. Place Text

1. On the menu bar, click Place -> Text. When Place Text window opens, type the desired text.

2. Click OK.

3. Drag and place the text in the desired location. Press the ESC key to end text placement.

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VIII. Change Part Reference 1. Double click on the part reference and rename it according to the schematic

handout.

2. For example, to rename the part reference of BATT1 to ProbeIn. Double click on BATT1. When the display Properties window opens, change the value to ProbeIn.

IX. Change Part Value

1. Double click on the part value and rename it according to the schematic handout.

2. For example, to rename the part value of 1K to 62K. Double click on 1K. When the display Properties window opens, change the value to 62K.

Change to ProbeIn

Part Reference

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X. Wiring

Once all part references and values are correct and their locations are in the right place, we can now wire the parts.

1. On the menu bar, click Place -> Wire or press W key to go into wiring mode. Use the ECS key or press the W key again to end wiring mode.

2. Once in the wiring mode, drag the wire. To turn, click and drag again. Once the wire is connected, press ESC key or press W key again.

XI. Adding Net Aliases

Net aliases are used for connecting two wires on one page, without a crisscrossing many wires. The wires are not physically connected as shown on the schematic, but they are connected because they share the same net alias.

1. On the menu bar, click PLACE > NET ALIAS.

2. Enter Name in the pop up.

3. Rotate the text as desired

4. Click OK.

5. Move to above wire, click to place Net Alias.

6. Move to the other end of the connected wire, click to place Net Alias. XII. Assign Footprints

Use the footprint list below to assign footprints

Part Reference Part value Footprint

BATT1

myPowerIN

C1 1u CAPCK06

C3,C4,C8 0.1u CAPCK06

C2,C5,C7 0.01u CAPCK06

Change to 62K

Part Value

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C6 4.7u CAP196

D1,D2,D3 LED myLED

D4,D5,D6,D7,D8,D9,D10,D11 D1N4148 DO-35

ProbeIn

myProbeIn

M1 IRF9140 Actual Part # VP3203N3-G TO92VAR

R1 62k RES400

R2 62k RES400

R3 22k RES400

R4,R5 33k RES400

R6,R11,R13 1M RES400

R7, R16 560k RES400

R8,R9,R10 470 RES400

R12,R15,R17 10k RES400

R14,R18 3M RES400

SW1 SW_SL_DPDT MYDPDT_SW

U1 LM393 dip8_3

U2 CD40106B dip14_3

U3 ICM7555 dip8_3

Y1 Piezo myPiezo

1. To assign footprints to C1, C3, C4, C8, C2, C5, and C7 all at one time, select all of these

capacitors by holding the CTRL key and click the respective capacitor.

2. On the top menu, EDIT -> PROPERTIES to bring up Properties spread sheet.

3. Pan to the right to the Foot Print Column. Enter name of footprint CAPCK06

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4. Close property editor.

5. Repeat Steps 1 through 4 for the footprints of the remaining parts.

XIII. Design rule check

1. Click LogicProbe Project Tab

2. Highlight the LogicProbe.dsn

3. On the menu bar, click TOOLS > DESIGN RULES CHECK

4. Click YES on Undo warning.

5. Set the options according to the Design Rules Check popup shown below:

Assure that view output option is checked so that you can see if there is an error.

Project Tab

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6. Click OK.

7. If there is an error, fix the error.

8. Repeat steps 3 through 6 until no error. If there is no error, the LogicProbe.DRC shall give messages as shown below:

XIV. Bill of material Bill of material contains the quantity of each part in the schematic including their reference and part values. 1. Click LogicProbe Project Tab 2. Highlight the LogicProbe.dsn 3. On the menu bar, click Tools -> Bills of material 4. Bill of Materials window pops up. Check View Output to see the bill of material on the

screen. A copy of the bill of materials is also saved in the design folder 5. Click OK.

Prof. G. Law, CSUN

Prof. G. Law, CSUN

Bill of Materials

Quantity

Item Qty Reference Part Footprint Digikey Part# Price/EA Price/EA Min

1 1 BATT1

myPowerIN 2 1 C1 1u CAPCK06 445-8517-ND $0.40 $0.27 (10pc)

2 3 C3,C4,C8 0.1u CAPCK06 BC2665CT-ND $0.18 $0.07 (50pc)

3 3 C2,C5,C7 0.01u CAPCK06 399-4206-ND $0.24 $0.11 (50pc)

4 1 C6 4.7u CAP196 P15798CT-ND $0.36 $0.19 (100pc)

5 3 D1,D2,D3 LED myLED

Red 160-1708-ND $0.32 $0.13 (100pc)

Green 160-1710-ND $0.32 $0.13 (100pc)

Yellow 160-1946-ND $0.32 $0.13 (100pc)

6 8 D4,D5,D6,D7 D8,D9,D10,D11 D1N4148 DO-35 1N4148VSCT-ND $0.10 $0.05 (100pc)

7 1 ProbeIn

myProbeIn

8 1 M1 VP3203N3-G TO92VAR VP3203N3-G-ND $1.37 $1.14 (25pc)

9 2 R1, R2 62k RES400 62KQBK-ND $0.10 $0.02 (100pc)

10 1 R3 22k RES400 CF14JT47K0CT-ND $0.10 $0.02 11 3 R4,R5 33k RES400 CF14JT33K0CT-ND $0.10 $0.02 12 3 R6,R11,R13 1M RES400 CF14JT1M00CT-ND $0.10 $0.02 13 2 R7, R16 560k RES400 560KQBK-ND $0.10 $0.02 14 3 R8,R9,R10 470 RES400 CF14JT470RCT-ND $0.10 $0.02 15 3 R12,R15,R17 10k RES400 CF14JT10K0CT-ND $0.10 $0.02 16 2 R14, R18 3M RES400 CF14JT3M00CT-ND $0.10 $0.02 17 1 SW1 SW_SL_DPDT MYDPDT_SW CKN9545-ND $0.57 $0.54 (25pc)

18 1 U1 LM393 dip8_3 497-7679-5-ND $1.07 $0.85 (25pc)

19 1 U2 CD40106B dip14_3 296-3503-5-ND $0.48 $0.31 (100pc)

20 1 U3 ICM7555 dip8_3 ICM7555IPAZ-ND $0.83 $0.55 (100pc)

21 1 Y1 Piezo myPiezo 445-2525-1-ND $0.72 $0.39 (100pc)

Total Cost $9.98 $5.67

XV. Print Schematic

1. On the menu bar, click File -> Print Preview. 2. If the preview looks OK, click Print on the Print Preview Manu Bar.

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XVI. Creating layout netlist

1. Highlight Logicprobe.dsn (Logicprobe.dsn is listed under Logicprobe.opj tab). Under top menu, click Tools Create Netlist. Click Yes to the Undo Warning!

2. Set the Create Netlist dialog options as shown below (do not click OK now, click OK after the next step):

Note: For now, leave the input Board File field blank. On subsequent netlist creations, you need to supply the name to the previously stored SmallLogicProbe.brd; otherwise, you will lose all of your PCB work and start with a blank SmallLogicProbe.brd board!

3. Click Layout tab in the Create Netlist dialog and set the option as shown below and then click OK. When you are prompted to save file, click OK.

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If there are no errors in your design, the Orcad PCB Editor dialog box will open. Click Yes. Otherwise, read the error messages in the message pane (bottom section) and fix the errors and do the Netlist Creation again.

Orcad PCB Editor Lite

I. Set Up Paths for Footprints

1. START -> PROGRAMS -> OrCAD PCB EDITOR

2. Choose SETUP -> USER PREFERENCES.

3. Expand Paths under Categories, select (click) the Library folder.

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4. Click the 3 dots (…) to the right of psmpath to add the path to the footprints

5. When psmpath items popup opens, click New(Insert) and enter the path to MyFootPrint. Move the new path to top by clicking the up arrow ↑ icon.

6. Click OK.

7. Click the 3 dots (…) to the right of padpath to add the path to the MyPadStack

New (Insert)

Up Arrow To move up

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8. When padpath items popup opens, click New(Insert) and enter the path to MypadStack. Move the new path to top by clicking the up arrow ↑ icon.

9. Click OK.

10. On the User Preferences editor, click OK.

II. Set up PCB Constraints

A. Set up physical constraint on all layers

On the top menu bar, click Setup -> Constraint -> Physical. When the Constraint Manager window pops up, select All Layers under Physical Constraint. Change the minimum line width to 8, maximum line width to 15, minimum neck width to 8, minimum BB Via Stagger to 40, and maximum BB Via Stagger to 40 as shown below:

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B. Set up VCC and Ground traces linewidth

1. Select ALL Layers under NET. Scroll to row BatteryPositive and change the minimum line width to 30, maximum line width to 40, and minimum neck width to 30 as shown below.

2. Scroll to row VCC and change the minimum line width to 30, maximum line width to 40, minimum neck width to 30 as shown below.

3. Scroll to row 0 and change the minimum line width to 30, maximum line width to 40, minimum neck width to 30 as shown below.

4. After you verify the line width, close the Constraint manager by clicking File -> Close.

III. Miscellaneous Suggestions

1. When a mistake is made, right click and choose Oops to remove the last action.

2. When a mistake is made, right click and cancel to undo a completed action.

3. When a mistake is made, click EDIT -> UNDO to go further back.

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4. When a mistake is made, reload without saving to try again.

5. To highlight tracks, turn ALL ON in the Find option panel then ALL OFF, then select CLINE SEG. The highlighted track can then be deleted or moved.

6. Use route -> connect to redraw the track.

7. Save the design regularly and often.

IV. Create PCB Board

Orcad PCB Editor Lite will open because you click OK on the last step in the Orcad Capture tool and the PCB was created successfully.

A. Draw Board Outline

Firstly, you need to decide the size of your PCB board. We want our LogicProbe board to be as small as possible and yet allows easy routing of traces.

1. View Windows. Tick Options box if it is not already has a check mark. The option pane is on the left. Select the Active class Board Geometry and the subclass Outline.

2. On the option panel, tick Line Width and change line width to 3.00.

Line width

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3. On the top menu bar, click Setup -> Outlines -> Board Outline. When Board Outline dialog pops up, change the Board Edge Clearance to 200.00 MIL. Keep Draw Rectangle option selected.

4. Click OK.

5. Toggle the grid by pressing F10 key. You will draw a rectangle with corner coordinates (16,100, 12,300), (23,700, 12,300), (23,700, 10,700), and (16,100, 10,700) to set the board boundary. Use the arrow key to pan up, down, right, or left, and zoom in or out so that all four coordinates are on the screen area.

6. On the top menu bar, click Setup -> Outlines -> Board Outline. When the board outline dialog pops up, change the Board Edge Clearance to 200.00 MIL. With the board outline dialog still displayed (DO NOT click OK now; it will close the board outline dialog), move the mouse to coordinate (16,100, 12,300), click and drag the cursor to coordinate (23,700, 10,700).

7. Click OK on the board outline dialog.

The gray rectangle is the board boundary and the brown rectangle is the keep-in boundary.

8. Use zoom in or out and pan left, right, up or down to place the entire rectangle across the entire screen.

Coordinate

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B. Lay components on board

1. On the top menu bar, click Place Manually. When the placement window pops up, you should see all of the part footprints in the Placement dialog box as shown below. Scroll up and down the footprint list and see if any footprint is missing. If a footprint is missing, it indicates that you have forgotten to assign the footprint for a part in the Orcad Capture tool. If this is the case, you then need to return to Orcad capture to insert the respective footprint and repeat the process from there.

2. Click on the box next to Components by refdes and drag a stack of all of the footprints and drop it outside the board boundary. Drag a footprint and place it in an unoccupied spot outside the board boundary. Repeat dragging a footprint in an occupied spot outside the board boundary until all of the footprints are placed. Do not worry about the locations of the footprints; You will rearrange each footprint to a desired location later.

3. Close the Placement dialog box by clicking OK. The screen shot below shows the footprints spread over the area outside the board boundary.

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C. Hiding Footprint Texts

1. Zoom in until you can see the alphabet letter clearly.

2. On top menu bar, click Display -> Color/Visibility. When the color dialog box pops up, expand the Components folder and select Tolerance. Uncheck all subclasses and click apply. This step will hide all Tolerance text which we do not need to see.

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3. Under Components folder, select User Part Number. Uncheck all subclasses and click apply. This step will hide all User part Number text which we do not need to see.

uncheck

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4. Under Components folder, select Device Type. Uncheck all subclasses and click apply. This step will hide all Device Type text which we do not need to see.

5. Click OK.

6. The footprints below do not show the wanted texts.

uncheck

Apply

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D. Rearrange the footprints

Rearrange the footprints by clicking and dropping it to a location inside the keep-in boundary as shown in the diagram below. If the orientation of the footprint is not the same as shown, highlight it, right click and select “rotate” to rotate it to the desired orientation. To move the part, you can also use the move command: Edit Move. If you use Move, after all parts have been moved to the desired locations, remember to do right click and then click done.

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Enlarged Version:

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E. Route the power lines Vcc and Ground

1. View Windows. Tick Options box if it is not already has a check mark. The option pane appears on the left. Select the Active Class Etch and the Subclass Top as shown:

2. So that you can identify which nets are VCC nets, you make PCB editor highlight them for you. Click Find on left of Option pane. Type NET in Find by name field and type VCC in Name field. Click More. The VCC nets are now highlighted.

3. Route Connect. Click one of the pads on a VCC net, use the routing in the following layout as an example, follow the ratsnet and drag it to another pad. You may need to do multiple turns to reach the other pad by dragging and release left mouse button. Repeat this step for all VCC nets. To change layer, right click and select the other layer. Right Click and click done to end routing mode.

Option Pane

Find

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VCC Nets Top Layer (Green)

VCC Nets Bottom Layer (Yellow)

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4. Repeat Steps 3 to route the GND nets. In these steps, use GND name and route GND nets instead.

GND Nets

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F. Route the signal nets on the bottom and top layers.

1. View Windows. Tick Options box if it is not already has a check mark. The option pane appears on the left. Select Active Class Etch and Subclass Bottom.

2. Route Connect. Click one of the pads on any signal net, use the routing in the following diagram as an example, follow the ratsnet and drag it to another pad. You may need to do multiple turns to reach the other pad by dragging and release left mouse button. Repeat this step for all signal nets. To change layer, right click and select the other layer. Right Click and click done to end routing mode.

3. View Windows. Tick Options box if it is not already has a check mark. The option pane appears on the left. Select Active Class Etch and Subclass Top.

4. Route Connect. Click one of the pads on any signal net, use the routing in the following diagram as an example, follow the ratsnet and drag it to another pad. You may need to do multiple turns to reach the other pad by dragging and release left mouse button. Repeat this step for all signal nets. To change layer, right click and select the other layer. Right Click and click done to end routing mode.

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G. Add Company Information on Board

1. View Windows. Tick Options box if it is not already has a check mark. The option pane appears on the left. Select Active Class Board Geometry and Subclass Silkscren_Top as shown:

2. Add Text. On the Option pane (left pane) set the text block size to 3. Type “Your name, California State University …” on the space shown below. When done, press return key. Right click and press Done. If needed, use Edit Move to move it. The text will be painted when the board is fabricated.

H. Design Rules Check (DRC check)

Tools Update DRC. If the DRC check finds no errors, the DRC tab on the lower message bar will be in green color. Any other color on the DRC tab indicates either warning or error. You can also do Tools Quick Report Design Rules Check (DRC) Report to open the DRC report. Read the report to see the warning or error in details, if any. The DRC display color on the bottom desktop menu bar will be green if there are no errors.

I. Unconnected Pin Check

Tools Quick Report Unconnected Pins Report to open the unconnected pin report. Read the report to see if you miss any pins when you routed the nets.

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H. Generate Artwork

1. Manufacture Artwork. Artwork control form dialog box opens.

Under the Available films window, you may not see all the films shown on the Artwork control form dialog box above. You should see BOTTOM and TOP films.

2. Click the General Parameters tab. Select the device type format Gerber RS274X format which is the industrial film format required by the PCB fabricator company. Choose the other options as shown below:

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3. Click OK. H1. Generate BOTTOM Layer Film

1. Manufacture Artwork. Artwork control form dialog box opens. 2. Expand the bottom film by clicking the + symbol on the left of BOTTOM. You should

have three subclasses included: ETCH/BOTTOM, PIN/BOTTOM, and VIA CLASS/BOTTOM.

3. Select the BOTTOM film by ticking the blank box on the left of BOTTOM.

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4. Click Create Artwork button.

5. Check if the artwork creation is successful by right click on BOTTOM layer and select (click) Display for Artwork Check. You should see the bottom layer artwork as shown below:

H2. Generate TOP Layer Film

1. Untick BOTTOM layer.

2. Expand and tick TOP layer. You should have three subclasses included: ETCH/TOP, PIN/TOP, and VIA CLASS/TOP.

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4. Check if the artwork creation is successful by right click on TOP layer and select (click) Display for Artwork Check. You should see the TOP layer artwork as shown below:

H3. Generate Board Outline

1. Right click on BOTTOM. Scroll down and select (click) Add.

2. When the Enter New Film Name dialog box appears, type/enter Board_Outline and click OK.

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3. Expand Board_Outline by clicking the + sign on its left.

4. Right click on one of the subclasses of Board_Outline and click Add.

5. The Subclass Selection dialog box appears. Expand Board Geometry and select OUTLINE.

6. Click OK.

7. Delete all unnecessary subclasses in Board_Line except BOARD GEOMETRY/OUTLINE by right click the unwanted subclass and click Cut. Repeat this step until only the BOARD GEOMETRY/OUTLINE subclass remains.

Prof. G. Law, CSUN

8. Set the Undefined line width to 1.00.


10. Check if the artwork creation is successful by right click on Board_Outline and select (click) Display for Artwork Check. You should see the Board Outline artwork as shown below:

H4. Generate Silkscreen Top layer


2. When the Enter New Film Name dialog box appears, type/enter Silkscreen_Top and click OK.

Enter 1.00

Prof. G. Law, CSUN

3. Expand Silkscreen_Top by clicking the + sign on its left.

4. Right click on one of the subclasses of Silkscreen_Top and click Add.

5. The Subclass Selection dialog box appears. Expand Ref Des and select SILKSCREEN TOP.

6. Click OK.


8. The Subclass Selection dialog box appears. Expand COMPONENT VALUE and select SILKSCREEN_TOP and ASSEMBLY_TOP.

Prof. G. Law, CSUN

9. Click OK.


11. The Subclass Selection dialog box appears. Expand BOARD GEOMETRY and select SILKSCREEN_TOP.

12. Click OK


14. The Subclass Selection dialog box appears. Expand PACKAGE GEOMETRY and select ASSEMBLY_TOP.

Prof. G. Law, CSUN

15. Click OK

16. Delete all unnecessary subclasses in Board_Line except REF DES/SILKSCREEN_TOP, COMPONENT VALUE/ASSEMBLY_TOP, COMPONENT VALUE/SILKSCREEN_TOP, and BOARD GEOMETRY/SILKSCREEN_TOP by right click the unwanted subclass and click Cut. Repeat this step until only the desired subclasses remain.

17. Set the Undefined line width to 5.00.


19. Check if the artwork creation is successful by right click on Silkscreen_Top and select (click) Display for Artwork Check. You should see the Silkscreen Top artwork as shown below:

Enter 5.00

Prof. G. Law, CSUN

H5. Generate Solder Mask Bottom layer


2. When the Enter New Film Name dialog box appears, type/enter Soldermask_Bottom and click OK.

3. Expand Soldermask_Bottom by clicking the + sign on its left.

4. Right click on one of the subclasses of Soldermask_Bottom and click Add.

5. The Subclass Selection dialog box appears. Expand PIN and select SOLDERMASK_BOTTOM.

6. Click OK.

7. Delete all unnecessary subclasses in Board_Line except PIN/SOLDERMASK_BOTTOM by right click the unwanted subclass and click Cut. Repeat this step until only the PIN/SOLDERMASK_BOTTOM subclass remains.


Prof. G. Law, CSUN

9. Check if the artwork creation is successful by right click on Soldermask_Bottom and select (click) Display for Artwork Check. You should see the Soldermask Bottom artwork as shown below:

H6. Generate Solder Mask Top layer


2. When the Enter New Film Name dialog box appears, type/enter Soldermask_Bottom and click OK.

3. Expand Soldermask_Top by clicking the + sign on its left.

4. Right click on one of the subclasses of Soldermask_Top and click Add.

5. The Subclass Selection dialog box appears. Expand PIN and select SOLDERMASK_Top.

6. Click OK.

7. Delete all unnecessary subclasses in Board_Line except PIN/SOLDERMASK_Top by right click the unwanted subclass and click Cut. Repeat this step until only the PIN/SOLDERMASK_Top subclass remains.

Prof. G. Law, CSUN


9. Check if the artwork creation is successful by right click on Soldermask_Top and select (click) Display for Artwork Check. You should see the Soldermask Top artwork as shown below:

Prof. G. Law, CSUN

I. Generate NC Drill

Manufacture NC NC Drill. In the NC Drill dialog box, click Drill tab. NC Drill completed successfully message is shown on the message window. Close the dialog box.

J. PCB Files for PCB fabrication Company

Congratulation! You have successfully completed the PCB layout. You can now send the files created by Orcad PCB to a PCB manufacturer to have the PCB board fabricated. Since Orcad PCB generates the artwork files in Gerber RS274X format by default, these files should meet the manufacturer’s requirements.

1. Zip all artwork files

Compress these files into smallLogicProbe.zip:

Board_Outline.art, BOTTOM.art, Silkscreen_Top.art, Soldermask_Bottom.art, Soldermask_Top.art, Top.art, and Smalllogicprobe-1-2.drl.

2. Check PCB layout at http://instantdfm.bayareacircuits.com/

Follow the link, fill the required information, upload the smallLogicProbe.zip, and click submit.

Bay Area Circuits will email you the result of the instantdfm check.

Watch the video at the link above for more information about the design submission and result of the instantdfm check.

http://instantdfm.bayareacircuits.com/

Prof. G. Law, CSUN

3. Submission to Bay Area Circuits

a. Once your PCB design has passed InstantDFM check, visit http://store.bayareacircuits.com/student-special/

b. Upload the smallLogicProbe.zip, tick “NC Drill file included” box and tick “Board Outline included” box.

c. Click Add to Cart and follow the instruction there.

http://store.bayareacircuits.com/student-special/

Prof. G. Law, CSUN

4. Alternate submission to http://www.seeedstudio.com/service/index.php?r=pcb

Cost of ten 5 cm by 20 cm PCB boards: $41.48 plus cost of shipping.

Tick both boxes

PCB Workshop using Orcad Lite Prof. George Law Objectiveglaw/PCBWorkshop/logic probe...

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