PCB Virtual Prototyping with PSpice

Parag ChoudharyEngineering Architect

Agenda

• Overview of Design Trends & Designer Challenges

• PCB Virtual Prototyping in PSpice – Simulator extensions for Models and Abstraction levels

• Examples of a coding algorithm models into PSpice PCB Level cycle accurate mixed signal simulation

Design Trends

Electronic systems trending to large devices for lower power, higher

reliability, and increased functionality in smaller package

Software controlled Digital Content with Analog circuitry all in one Electronic Package are the new

Mixed Signal devices

Handhelds, wearable(s) and Internet of Things boosting growth

of Embedded Systems

System integration trends

Design Development Challenges

Discrete Devices

Basic Integration

Mixed-Signal Technologies

Mixed-Signal Electro-

Mechanical

SoCIntegration

Package Integration

SPICE Models Mixed-Signal Models System Models

Higher abstraction and lower accuracy and lower simulation time

Embedded Software controlled Mixed Signal Device require solutions

where S/W algorithms can be tested together with H/W

In PCB systems simulation –for large ICs – HDL-level IC models are prohibitively

slow for the new emerging class of devices

PCB Virtual prototyping

RequirementsModel Abstractions

Architectural

Functional

Behavioral

Gate Level

Circuit Level

Physical Implementation

Package Integration

SoC Integration


Mechanical


Basic Integration

Discrete Devices

Physical SPICEparametric extraction and curve fitting

Mixed-signalSPICE and gate-level simulation (Small D- Big A)

System macro-model (System model embedded in mixed-signal model)

Cadence, the Cadence logo, and PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Integrated C/C++ & Spice language based solution to model large mixed signal electronic devices at any

abstraction level and achieve desired accuracy at PCB level simulation while supporting existing PCB

analysis flows

PSpice virtual

prototyping

PCB systems

PSpice Model

PSpice® System Macro Model with SystemC-TLM

PSpice System Macro Model with SystemC, C, C++, PSpice Digital

PSpice System Macro Model with SystemC, C/C++, PSpice Mixed Signal

PSpice Mixed-Signal Macro Model with C/C++, PSpice Mixed Signal Devices

PSpice Macro Model with SPICE, Analog-C/C++/SystemC-AMS

PSpice Macro Model with SPICE, Analog-C/C++/SystemC-AMS with

Physical Parasitic

Cadence, the Cadence logo, PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Package Integration

SoC Integration


Mechanical


Basic Integration

Discrete Devices

Physical SPICEparametric extraction and curve fitting

Mixed-signalSPICE and gate-level simulation (Small D- Big A)

System macro-model (System model embedded in mixed-signal model)

Model Abstractions

Architectural

Functional

Behavioral

Gate Level

Circuit Level

Physical Implementation

Integrated C/C++ & Spice language based

solution to model large mixed signal

electronic devices at any abstraction level and achieve desired accuracy at PCB level

simulation while supporting existing PCB analysis flows

PSpice mixed-signal simulator

Behavioral

Logic

(Functional

Model)

[G][V]=[I]

IN

0

IN

1

IN

2

OUT

0

Pin to PinTiming Model

Constraint Model

Pin I/O Models

Digital Event Solver6 logic levels (Z level is strength)

Analog Matrix Solver

D/A & D/A ConvertorsOUT

1

OUT

2


PSpice mixed-signal device models

A/D (O device)Behavioral primitives

Bidirectional transfer gates

D/A (N device) Delay line

File stimulus Flip-flops and

latches Input/output

model

Multi-bit A/D and D/A

converters

Programmable logic array

Pullup and pulldown

Random access read-write memory

Read-only memory

Standard gates Stimulus

generator

Tristate gates

D/A & D/A Convertors

GaAsFET Capacitor Diode VCVS and Flux

SourceCCVS

VCCS and Charge Source

CCCS Independent

Current source JFET

Mutual Coupling

Inductor Mosfet D/A A/D IGBT

Bipolar transistor

Resistor Voltage-

Controlled switch

Transmission lines

Independent Voltage Source

Current Controlled

Switch

Generic C/C++ Model


PSpice mixed-signal macro model with

C/C++/SystemC extensions

D/A and D/A Convertors

VerilogA-ADMS Configuration

C/C++ Behavioral Model

Device Compact Models

C/C++ Digital Model

SystemC Model


A/D (O device)Behavioral primitives

Bidirectional transfer gates

D/A (N device)

Delay line File stimulus Flip-flops and

latches Input/output

model

Multi-bit A/D and D/A

converters

Programmable logic array

Pullup and pulldown

Random access read-write memory

Read-only memory

Standard gates Stimulus

generator Tristate gates

GaAsFET Capacitor Diode VCVS and

Flux Source

CCVSVCCS and

Charge Source

CCCS Independent

Current source

JFETMutual

CouplingInductor Mosfet

D/A A/D IGBTBipolar

transistor

Resistor Voltage-

Controlled switch

Transmission lines

Independent Voltage Source

Current Controlled

Switch

Generic C/C++ Model

Integrated C/C++ & Spice language based

solution to model large mixed signal

electronic devices at any abstraction level and achieve desired accuracy at PCB level

simulation

PSpice Event solver Acceleration with Accuracy for PCB

SimulationSystem

Model

Abstraction

IN

0

IN

1

IN

2

OUT

0

Pin to PinTiming Model

Constraint Model

Pin I/O Models

OUT

1

OUT

2

Temporal Data Accuracy

Functionality Structural

Simulation Acceleration with System-Level Abstractions

Timing and I/O models at Interface

Example - S/W Algorithm Controlled PWM in Power Supply

PWM

Microcontroller

with S/W

control

Power StageFilter

Stage

IN

A/D

OUT

C/C++ Digital Model

SystemC Model

Develop and test MCU targeted algorithms in PSpice models

PWM Control

Detect clock edge

Read Input signal bits

Convert Signal Bits to C/C++ variables

Execute Algorithm

Convert C/C++ variables to Signal bits and post to output

Example: C/C++ Digital Model in PSpice

Read input signals

Create SystemC variables for input Signals

Write to SystemC block

Evaluate SystemC Block

Read SystemC Block output

Write to output signal bits

Example: SystemC Model in PSpice

PSpice acceleratedmixed-signal

system model for large IC on

PCB with mixed-signal accuracy at

interface

Physical device compact model

SystemC model supporting embedded S/W and different abstraction levels

Analog behavioral

Digital C/C++ with embedded SW block

Temporal Data Accuracy

Functionality Structural

Simulation Acceleration with System-Level Abstractions


Specify Model I/O , Timing and Constraints

inside Model core behavior in System

Model

or

PSpice re-usable model specification directly input as specs from

IC datasheets

PSpice Digital Block

Functional Logic

I/O Drive Specs

Timing Specificati

on

Constraint Specificati

on

PSpice® digital block allows user to specify functional logic, I/O, timing and constraints

at a block level

(PCB solutions need to work from datasheet)

I/O model, timing information and constraints can be captured directly from

datasheet

PSpice system modeling extensions allows functional logic to be simple C/C++ or can be

sophisticated models from SystemC

The PSpice C/C++ digital block API allow specification of timing and I/O also –

enabling more complex models instead of always using block-level specification

Design Algorithmic module in

Matlab/Simulink

Use MATLAB/Simulink Coder to Generate C

Code

Use PSpice Adapter to embed code inside

PSpice behavioral block

Compile code in Microsoft Visual Studio IDE to generate PSpice-

DMI compatible dll

Associate Macro-model to Schematic on OrCAD

Capture Canvas

Run PSpice simulation and verify results

Using Matlab/Simulink blocks using PSpice

Device Modeling (DMI) API

Algorithmic Block Simulation in Matlab-

Simulink

MATLAB Model Block Implementation &

Simulation in

PSpice

Mixed-level Co-simulation in Matlab-

Simulink & PSpice

Mixed-level Simulation in PSpice

Algorithmic Abstraction Implementation

Algorithmic Block Simulation in

Matlab-Simulink

MATLAB Model Block Implementation &

Simulation in

PSpice

Mixed-level Co-simulation in Matlab-

Simulink & PSpice

Mixed-level Simulation in PSpice

Using Device modeling API with MathWorks Algorithms

Algorithmic Abstraction Implementation

Matlab PSpice

Algorithm Transfer to PSpice ® Circuit

Model

PSpice® Analog Behavioral

PSpice Functional Block Defined in C

PSpice SPICE Macro-Model

PSpice

virtual

prototyping

PCB systems

Cadence, the Cadence logo, Virtuoso, MMSIM and PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Single Simulation environment with

embedded software and Electronic

devices models at multiple abstraction

levels

Simulink & PSpice co-simulation

Filter

Instantiate and co-Simulate PSpice Design Block in Simulink

Miniaturization-iterative block implementation with system design exploration to implementation

PSpice PCB Implementation

PSpice System Design

PSpice® PCBBlock in Simulink

Simulink Coderto PSpice Block

Implementation across multiple design fabrics

Chip-Package-Board

Improved model quality for

increased model complexity

Specctre ® PSpiceNetlist SupportMMSIM 14.1 Dec. 2014

PSpice ® SystemC, C/C++ Support16.6 QIR8 2014Verilog-ADMS July 2015

PCB system model in Cadence Chip-Package-Board

solutionVirtuoso®

Technology

Virtuoso® System In Package Technology

Allegro® PCB Technology

Sigrity®

Technology

OrCAD®

Technology

MMSIM with Spectre® & PSpice®• Goal

– MMSIM simulations enabled with sub-blocks defined in PSpice® format

– Allows designer to include PCB components in Spectre® simulations

• Use model– Spectre netlist: pspice_include <file>– Spice netlist: .pspice_include <file>– All file content inside <file> and any

included file are required to be in PSpice format

• No supported – PSpice only designs– PSpice control statements

Spectre Top Level

Spectre Sub-block

Spectre Spectre

PSpice

Sub-block

PSpice

MMSIM PSpice features• Features

– “pspice_include” reads the PSpice® format netlist– Models included in PSpice netlist simulated using the PSpice default

values and equations– All basic analog devices are supported

– Basic device types– Independent and dependent sources– Subckt and model definition– Parameter and function definitions– Transmission lines– Analog behavioral modeling

• Note– Digital devices are not supported with Spectre® simulation. Basic gates

may be built using analog behavioral elements.– Virtuoso® Analog Design Environment support available in IC616

ISR4/MMSIM13.1 ISR1

PSpice ®

System Design with Embedded

S/W

To

System Implementation

PSpice-Simulink

(SLPS)

Multi-Domain Modeling and

Simulation

OrCAD

World’s Leading Schematic Authoring

Technology

PSpice Mixed Signal

Co-Simulation with

Implementation

PSpice Advanced Analysis

Reliability Analysis with customized

algorithms

Open Application Programming Interface (API)

Systems Modeling

Authoring with PSpice® System Design Macro Model

Mixed-Signal Simulation with Embedded System Models

PSpice Behavioral and Compact Device Modeling with VerilogA and C/C++

Circuit Reliability Analysis

SI/PDN Analysis (Sigrity™ Technology with PSpice)

Interface to post-

processing and reports

• PSpice® system model extensions enable modeling of large mixed-signal ICs in PCB simulation enabling simulation of entire PCB

• PSpice analog C/C++ extensions with VerilogA-ADMS configurations enable modeling of:– Analog behavioral blocks for multi-domain PCB simulation – New technology device compact models into PSpice simulator

• PSpice-Virtuoso® collaboration provide model and netlist portability between Virtuoso-Spectre® environments and PSpice

Summary

Next Level Implementation details in Session on modeling Embedded Device

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, OrCAD, PSpice, Spectre, and Virtuoso are registered trademarks and Sigrity is a trademark of Cadence Design Systems, Inc, All other trademarks are the property of their respective owners.

PCB Virtual Prototyping with PSpice

Engineering

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