PC Board Layout Techniques for...

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PC Board Layout Techniques for FAEs

High Speed, Mixed-Signal & Low Level Applications

ADI Confidential 2

The Art of PCB Design

Good PCB design is a discipline that takes years to master.

Reliable High-speed, mixed-signal designs require a great deal of theoretical knowledge and practical understanding to be done properly.

We’ll cover many important concepts at a high level today.

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AgendaPCBs 101Good High-Speed PCB Design Practices

The Power of Power and Ground planesProper use of decoupling capacitorsThe True Nature of Resistors and Capacitors in High-speed DesignsHigh-speed Signal Propagation - Wires or Transmission Lines?Impedance Mismatches, Series and Parallel TerminationManaging EMI

Mixed Signal PCB LayoutGrounding Mixed Signal Data Acquisition SystemGround Plane in Mixed Signal DesignsPower Filtering & decouplingParasitic ConsiderationControl Differential line impedance

Small Signal LayoutConsider Track Resistor LossProper grounding shielding cableMinimize PCB Leakage by Guard RingPrevent PCB Heating Temperature Sensors

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PCB methodologies originated in the United States Units of measurement are therefore typically in Imperial units, not SI/metric units.

Board dimensions are commonly measured in inches.Dielectric thickness & conductor length and width typically measured in inches and “mils”.

1 mil = 0.001 inches1 mil = .0254 mm

Conductor thickness measured in ounces (oz).The weigh of conductor metal in a square foot of material.Typical thickness

0.5oz = 17.5µm1.0oz = 35.0µm2.0oz = 70.0µm3.0oz = 105.0µm

PCB BasicsPCB Units of Measurement

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PCB BasicsPCB Stack-up

A PCB consists of alternating layers of prepreg and core materialsMaterials:

Core: A thin piece of cured dielectric (usually FR4 : fiberglass & epoxy) Prepreg: Short for preimpregnated. A thin piece of uncured dielectric (usually “FR4” : fiberglass-epoxy). Prepreg melts into an epoxy glue when heated and pressed, and then hardens / cures with the same dielectric constant as the core material. Copper Foil : Thin piece of copper that is bonded / laminated to both sides of the core using epoxy resin.

The number of layers of copper foil corresponds to the “layers of the PCB”An 8-layer PCB has 8 layers of copper foil.

Stack-up is symmetrical about the center of the board in the vertical axis to avoid mechanical stress in the board under thermal cycling.

Prepreg

Core

Prepreg

Core

Prepreg

Core

Prepreg

Copper Foil

Cross Section of a typical 8-layer stack-up

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Copper (Cu) is the most commonly used conductor in PCBs.Traces and/or connectors may be plated in nickel followed by gold to provide a corrosion-resistant electrically conductive.

Trace Width (W) and Length (L) – controlled by PCB layout engineerWidth and spacing between traces typically ≥5 mil in common fabrication processes

Trace Thickness (h) – variable of fabrication processTypically 0.5oz – 3oz Trend towards 0.25oz

Signal Integrity Tip: All of the above affect the resistance, capacitance and impedance of the trace and must be well understood for high-speed design.

PCB (Printed Circuit Board) AnatomyPCB Conductors : Traces

Source: http://circuitcalculator.com/wordpress/wp-content/uploads/2007/04/pcb-trace-geometry-1.png

WLRs

WhL

ALR =

⋅⋅

=⋅

=ρρ

Cu resistivity: ρ=1.7E10-8Ωm

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PCB BasicsPCB Conductors : Power Planes

Power PlanesA solid layer of copper used to provide power or ground.Typically use thicker copper layer than signal layers to reduce resistance.

Why are they needed?Provide a stable, low-impedance path for power and ground signals to all devices on the PCBShield signals between layers to minimize cross-talk

Signal Integrity Tip: By placing power and ground on opposite sides of thin core material, we can maximize the “intra-plane capacitance”. Also, this minimizes PCB warping.

Prepreg

Core

Prepreg

Core

Prepreg

Core

Prepreg

Copper Foil

Signal trace

Power plane

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PCB BasicsPCB Insulators / Dielectrics

Common Dielectric MaterialsFR-4 (Woven fiberglass and epoxy)

Most commonly used, widely available, relatively low-costDielectric constant (permittivity) : 4.70 Max, 4.35 @ 500 MHz, 4.34 @ 1 GHz

Acceptable for signals up to about 2 GHz (loss and cross-talk will increase beyond this)

Fairly rigid (17 GPa using Young’s modulus)FR-2 (Phenolic cotton paper)

Very low-cost, used in cheap consumer devices.Susceptible to crackingDielectric constant (permittivity) : 4.5 @ 1 GHz

CEM-3 (Woven glass and epoxy)Very similar to FR4, widely used in Japan

PolyimideGood performance at high frequencies

FR & CEMFR : Flame RetardantCEM : Composite Epoxy Material

Signal Integrity Tip: Most PCB insulator materials support a relatively controlled dielectric - this is important for maintaining a constant impedance for transmission lines!

More on this soon

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PCB BasicsVias

Vias (plated holes)Used to connect layersFormed by drilling or punching hole through PCB layers and plating the insideTypically much larger than signal traces

Buried and Blind ViasProvide increased wiring densityAdded cost to PCB fabrication – typically used only in high-volumeBuried vias are difficult to debug

Signal Integrity Tip: vias introduce capacitance and change the characteristic impedance of a trace.

Via Blind Via Buried Via

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PCB BasicsTypical PCB Design Process

Schematic Capture

Schematic Library

PCB Layout

Footprint Library

SchematicDRC Report PCB

DRC Report

Gerber Files

Drill File

Netlist

DRC = Design Rule Check

PCB

Fabrication

Fabrication Tolerance

(i.e. min trace width, min hole size, etc.)

PCB Parameters(i.e. core material,

copper weight, etc)

Librarian and/or device provider

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PCB BasicsTypical PCB Fabrication Process

1. Receive Gerber files, Drill files and other PCB attributes from customer.2. Prepare the PCB substrate and laminate (core)

1. Copper film is attached to the substrate material (i.e. FR4).3. Inner layer image transfer

1. Etch-resist chemical is masked and cured (hardened) over copper film where copper is to remain (i.e. traces and vias).

2. Un-cured chemical is washed away3. Etchants applied to copper film (typically FeCl or Ammonia). Unmasked copper

is dissolved. 4. Solvent applied to remove the cured etch-resist5. PCB washed to remove all residues

4. Laminate layers5. Drilling, cleaning & plating vias

1. This is how connections are made between layers2. Holes drilled through layer stack where vias are desired3. PCB immersed in plating solution where a thin layer of copper forms within holes4. Electro-plating then used to deposit around 1mil of copper

6. Outer layer image transfer7. Apply soldermask8. Silkscreen (text and graphics)

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Good High-Speed PCB Design Practices Overview

Some customers still design PCBs by “feel” and not using proper methodologies and/or discipline. For modern high-speed analog and digital design, it is almost impossible to produce a reliable design based on “feel”.Result may be

Improper or unexpected system behaviorUnacceptable levels of noise in analog pathsSystem stability/reliability that varies across temperature and/or board build lot.Spurious bit-errors between connected devices on same PCBLarge amounts of power supply and ground noiseOver-shoot, under-shoot and glitching on signals.

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Good High-Speed PCB Design Practices Using the Right Equipment

A good oscilloscope with ample bandwidth is an essential tool in high-speed PCB projects.

Need to consider the bandwidth and sampling frequency of the device.

What will a 133MHz SDRAM signal look like on a low-cost scope with 200MHz bandwidth and 2GSPS sampling rate?

Important events like glitching, overshoot and undershoot, and power supply noise may not be properly represented on a low-cost scope.

Remember! High-speed digital signals are square waves!

Square waves are rich in high-energy, odd harmonics

As process geometry decreases (130nm->90nm->65nm), rise and fall times decrease = more harmonics!

How are these related?

)...5sin(51)3sin(

31)sin()( ttttx ++=

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Good High-Speed PCB Design PracticesPower and Ground Planes

Power and ground planes should always be used when possible. Why?

Provides a low-impedance path between the power supply and the devices in the system.Provide shieldingProvide heat dissipationReduces stray inductance

A solid, unbroken plane is best. Breaks in the ground plane can introduce parasitic inductance in traces above or below the plane.

Remember!At low frequency, current will follow the path of least resistance. At high frequency, current will follow the path of least inductance.

Pulse response with and without a ground plane

(source Analog Dialogue: Volume 39, September 2005)

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Generally Good PCB Design PracticesDecoupling Capacitors (or “bypass” caps)

When gates within a device switch, there is an instantaneous change in impedance within the device.

Result is an instantaneous change in current.

Decoupling capacitors provide a low-impedance current source for these instantaneous changes.

Reduces voltage fluctuation on the ground and power signals.Helps ensure power and voltage signals are within the operating specification of the device.

CGATE

VDDint

PMOS

NMOS

VDD

VDD

GND

GND

Low to high transition

High to lowtransition

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Good High-Speed PCB Design PracticesDecoupling Capacitors

Five broad frequency bands need to be “bypassed” with high-speed devices

DC to 10kHzTaken care of by the regulator

10kHz to 100kHzTaken care of by electrolytic bypass capacitors

100kHz to 10MHzTaken care of by multiple 100nF (0.1uF)

10MHz to 100MHzTaken care of by multiple 10nF (0.01uF)

100MHz and aboveTaken care of by multiple 1nF & PCB Power & Ground Planes

SUPPLY, V

+3.300V+3.383V(+2.5%)+3.465V(+5%)

+3.135V(-5%)+3.218V(-2.5%)

+1.200V+1.230V(+2.5%)+1.260V(+5%)

+1.140V(-5%)+1.170V(-2.5%)

VD

DEX

TV

DD

INT

165mVpp

60mVpp

NOTE SUPPLY VO LTAGE DROPS BELOW 5% LIMIT DURING SWITCHING TRANSIENTS AND DURING HEAVY CURRENT DEMAND CAUSED BY INCREASED PROGRAM ACTIVITY

SUPPLY, V

+3.300V+3.383V(+2.5%)+3.465V(+5%)

+3.135V(-5%)+3.218V(-2.5%)

+1.200V+1.230V(+2.5%)+1.260V(+5%)

+1.140V(-5%)+1.170V(-2.5%)

VD

DEX

TV

DD

INT

165mVpp

60mVpp

NOTE SUPPLY VO LTAGE DROPS BELOW 5% LIMIT DURING SWITCHING TRANSIENTS AND DURING HEAVY CURRENT DEMAND CAUSED BY INCREASED PROGRAM ACTIVITY

This device is operating out of specification! Ample oscilloscope bandwidth is essential for detecting these events.

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How many decoupling capacitors are required?System dependent!

Need to consider frequency of operation, number of I/O pins switching, Capacitive load on each pin, trace impedance, junction temperature, internal chip operation, etc. For processors, consider the variety of internal operations like cache, internal memory accesses, DMA, etc. etc. etc.

The rule of thumb: At all frequencies from DC, to well above the highest clock frequencies, the supply pins should have less than ±5% of VDD total noise.The tolerance of the maximum DC supply voltage drift PLUS the peak noise amplitude must be less than 5% of the nominal supply voltage.

An oscilloscope with ample bandwidth is required.Various methods exist for estimating the total required capacitance and how to distribute the capacitance across a number of smallervalue capacitors

This is a complex problem, particularly when dealing with the complexities of modern processors which contain millions of gates.Numerous application notes on semiconductor websites

www.freescale.com/files/32bit/doc/app_note/AN2586.pdf

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For best performance, minimize the inductance and resistance between the device supply pins and the decoupling capacitors.

PCB traces and vias introduce impedance!

ABSOLUT ELY NOT ! BETT ER

EVEN BETT ER EVEN BETT ER ST ILL

THE BEST!SOLID VIA WIT HIN PAD

ABSOLUT ELY NOT !ABSOLUT ELY NOT ! BETT ERBETT ER

EVEN BETT EREVEN BETT ER EVEN BETT ER ST ILLEVEN BETT ER ST ILL



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When ground/power plane pairs are used, capacitors can be just as effective on the top side of the PCB.

Mini-BGA (17x17mm)GND

PWRs = 4-mil

hA = 12-mil

hB = 46-mil1.59mm(62-mil)FR-4

0603 SMD CAPACITOR(63×31 mils)

‘A’

‘B’

L = 10mm 1mm BALL PITCH

VIAS DIAM, d = 0.47mm (12-mil)NOTE: DRAWING IS NOT TO SCALE

‘X’

Mini-BGA (17x17mm)GND

PWRs = 4-mil

hA = 12-mil

hB = 46-mil1.59mm(62-mil)FR-4

0603 SMD CAPACITOR(63×31 mils)

‘A’

‘B’

L = 10mm 1mm BALL PITCH

VIAS DIAM, d = 0.47mm (12-mil)NOTE: DRAWING IS NOT TO SCALE

‘X’

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Effective bypassing at frequencies over 100MHz…As clock frequencies and edge rates increase it becomes more difficult to effectively bypass the power supply pins of high-frequency devices.

Capacitor ESL (Effective Series Inductance) results in increasing reactance with frequencyCapacitor ESR (Effective Series Resistance) increases, reducing the effectiveness of capacitorsCapacitor parasitic mounting (pads, vias) reactance increases with frequency100nF capacitors are useless above 100MHz

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Good High-Speed PCB Design PracticesUnderstanding Capacitors - ESL

ESL (Effective Series Inductance) is caused by the inductance of the electrodes and leads of the capacitor.The ESL of a capacitor sets the limiting factor of how well (or fast) a capacitor can de-couple noise off a power buss.

Capacitors are essentially an L-C circuit thus they have a resonant point. The ESL and the capacitance thus both affect the resonate-point of a capacitor.Capacitors with a high resonant frequency will perform

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Good High-Speed PCB Design PracticesUnderstanding Capacitors - ESL

Source: www.murata.com/emc/knowhow/pdfs/te04ea-1/12to16e.pdf

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Good PCB Design PracticesUnderstanding Capacitors

Different types of capacitors…TBA

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High Speed PCB Design and Layout Understanding Resistors

James Bryant’s paperTBA

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Wire or Transmission Line?Wire – we consider every point of a wire to be at the same potential at any given point in timeTransmission Line – we consider the effects of signal propagation and assume that points along the transmission line will be at different voltage potentials as signals traverse.

When to treat a signal path as a transmission line?

If the length is greater than 1/100 of the wavelength.If the receiving device is edge sensitive.If the system is not tolerant of excessive overshoot and undershoot.Almost always!

High Speed PCB Design and LayoutWire or Transmission Line?

Source: Johnson & Graham, High-Speed Digital Design (AHandbook of Black Magic)

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Propagation Delay : the rate at which an electrical signal travels through a medium.

Typically measured in picoseconds/inch.Electrical signals propagate at a speed dependent on the surrounding medium.

Propagation delay increases proportionally to the square root ofthe dielectric constant

High Speed PCB Design and LayoutPropagation : Time and Distance

1.0Speed of light : 84.72528Vacuum

8-10240-270Alumina PCB (inner trace)4.5180FR4 PCB (inner trace)

2.8-4.5140-180FR4 PCB (outer trace)2.3129Coaxial Cable (66% velocity)

1.8113Coaxial Cable (75% velocity)

~1.085Air (radio waves)

Dielectric ConstantDelay (ps/in)Medium

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When the impedance of a conductor changes a portion of the signal energy is reflected.The amount of energy reflected is proportional to the difference in impedance between the two conductors.

High Speed PCB Design and LayoutTransmission Lines and Impedance Mismatch

AB

ABR ZZ

ZZE+−

∝

AB

ER

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The physical characteristics of the PCB trace will have a large effect on the impedance.

Trace materialWidth of traceTrace thicknessProximity to other traces and planesDielectric constants of surrounding materials (i.e. air, FR4, etc).

Many free tools available to help estimate the impedance of a trace.

http://emclab.umr.edu/pcbtlc2/index.html

High Speed PCB Design and LayoutUnderstanding Trace Impedance

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Device A to Device B, a propagating signal will likely traverse multiple impedance changes.The largest mismatches will almost always occur at the source and load

Will generate large reflections!How can we deal with this?

Let’s look at a story…

High Speed PCB Design and LayoutChanges in Impedance Across Signal Path

Device A Device Bvia via connector connector

cable tracetracetrace trace

Output DriverZtypical ≈ 25Ω

Transmission LineZtypical ≈ 50Ω

LoadZtypical ≈ 1MΩ

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The Story of EDGAR the Energy PacketCourtesy of Bob Kilgore

Edgar is a jogger

He travels at a rate of 6 inches / nanosecond on a Printed Circuit Board

He changes the voltage of conductors that he touches

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Edgar Meets The “Unterminated”Transmission line

Attributes:Point to point connection25 Ohm impedance Output Driver50 ohm impedance Transmission Line (Z0)1 Meg Ohm impedance receiver

Driver Receiver

Transmission Line

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At The Start

The Driver lowers the voltage by from VDD to GND.

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Edgar Starts for the Receiver

Edgar travels at 6 inches per nanosecond

Driver Receiver

Transmission Line

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Edgar Is REFLECTED!

Edgar is moving from a 50Ω transmission line to 1MΩreceiver!

Almost 100% of Edgar is reflected back towards the source!

1501000000501000000

0

0≈

+−

=+−

ZZZZ

L

L

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Edgar Returns to the Driver

Edgar travels at 6 inches per nanosecond with most of his original energy!

Driver Receiver

Transmission Line

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Edgar Finds the Next Obstacle

Edgar meets the 25Ω source driver after his return journey on the 50 ohm transmission line.The Reflected Energy is:

31

50255025

0

0−=

+−

=+−

ZZZZ

L

L

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Edgar Is Sent to the Receiver Again


Driver Receiver

Transmission Line

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Edgar Is Sent to the Driver Again


Driver Receiver

Transmission Line

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Edgar Is Sent to the Receiver a Third Time


Driver Receiver

Transmission Line

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What would we see on the scope?

VDD

GND

Measured at the Driver Measured at the Receiver

Always measure at the Receiver not the Driver!

And what effect might this have on an edge-sensitive input?

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Leverage Ohms’ law to minimize the impedance mismatch at the source side and load of the transmission line.Managing the Source :

Source impedance is typically less than 50ΩWe can add a series resistor to the source to increase its impedance to match the transmission line.This technique is called “serial termination”

Managing the Load :Load impedance is typically much greater than 50ΩWe can add a parallel resistor to the load to decrease its impedance to match the transmission line.This technique is called “parallel termination”

Each method has its pros and cons. A combination of both is often most effective.

High Speed PCB Design and LayoutTransmission Line Termination

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Parallel resistor at the receiver can work well but has: Increases drive current and thus increases power dissipation.Increased Crosstalk, Increased EMI.Increased ground bounce or supply noise (depending on if the parallel resistor is pulled high or low).

Driver Receiver

Transmission Line

Drive current about 50 mA

High Speed PCB Design and LayoutParallel Termination

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Series resistor at the driver is less disruptive:…but the driver impedance is nonlinear and you lose some energy getting into the transmission line

Driver Receiver

Transmission Line

High Speed PCB Design and LayoutSeries Termination

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DDR SDRAM Termination

DDR uses Dual termination.At VCC/2 = 1.25V, Io of the driver is about 14mA

Driver Receiver

Transmission Line

VCC/2

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Edgar Meets DDR in the Real World

Driver Receiver

Transmission Line

VCC/2

The Series Resistor Plus the Drive impedance is 50 OhmsThe Parallel Resistor is 50 OhmsThe Transmission Line Impedance is 60 Ohms (Bad PCB)

5025

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Edgar Finds the First Obstacle

The Receiver is a 50 Ohm Load But the Transmission Line was 60 Ohms Due To FR4 Construction and Fabrication Errors

The Reflected Energy is:

111

60506050

0

0 −=

+−

=+−

ZZZZ

L

L

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Edgar is Reflected


Driver Receiver

Transmission Line

VCC/2

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Edgar Finds the Next Obstacle

The Driver is a 50 Ohm Load But the Transmission Line was 60 Ohms Due To FR4 Construction and Fabrication Errors

The Reflected Energy is:

111

60506050

0

0 −=

+−

=+−

ZZZZ

L

L

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Edgar is Reflected

Edgar Travels at 6 inches per nanosecondEdgar is now about 1/100 of its original EnergyTherefore Edgar changes the voltage by 1/10 or about 0.2 volts

Driver Receiver

Transmission Line

VCC/2

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Good PCB Design PracticesElectro-Magnetic Emissions

Two primary tenants of electro-magnetism Current passing through a conductor generates a magnetic field.Placing a conductor in a magnetic field will induce current

The shape an intensity of a magnetic field generated by passing current through a conductor is affected by the shape of the conductor and visa versa.

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Good PCB Design PracticesEMI : Electro-Magnetic Interference

EMI typically refers to an undesirable amount of electromagnetic emission from a design.EMI from one device on a PCB may affect the performance of another device.

Digital circuits are more likely to be the source of disruptive emissions due to the handling of periodic waveforms and the fast clock/switching rates. Analog circuits are more likely to be the susceptible victims due to higher gain functions.

EMI from the entire system may affect the performance of other near-by systems.

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Good PCB Design PracticesReducing EMI in PCBs

There are many widely used techniques for minimizing the EMI of a PCB design.Fundamentals:

Power and ground planes providing shieldingTop and bottom ground planes can help reduce radiation from multi-layer boards by at least 10 dB.

Physical placement of devices on the PCB – keep analog and digital systems as far apart as possible on the PCBProper use of decoupling caps reduces power/ground noise and thus EMI from these planes.Keep signal traces away from the edge of the PCBAvoid right angles in PCB tracesBe cognizant of PCB trace resonance at fundamental frequency or harmonics due to reflections.More to come…

http://www.radioing.com/eengineer/pcb-tips.html

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Getting the best performance on our PCBsAs amplifiers and converters’ performance improved, achieve their performance on your PCB will be challenging.

Layout guide & design notes training before PCB layout will save much time in debugging.

Moving on today’s trainingMixed Signal PCB Layout TechniquesSmall Signal PCB Layout Techniques


Mixed Signal PCB Layout

Grounding Data Acquisition

System

ADI

ADI Confidential 55

Digital Currents Flowing in AnalogReturn Path Create Error Voltages

DigitalCircuitry

AnalogCircuitry

Res

isto

r

ClockCircuitry

ANALOGCIRCUITS

DIGITALCIRCUITS

VD VA

+ +

ID

IA

IDIA + ID

VIN

GNDREF

Incorrect

DigitalCircuitry

AnalogCircuitry

Res

isto

r

ClockCircuitry

ANALOGCIRCUITS

DIGITALCIRCUITS

VD VA

+ +

VIN

ID

IA

ID

IAGNDREF

Correct

Sensitive Analog Circuitry Disrupted by Digital Supply Noise

Sensitive Analog Circuitry Disrupted by Digital Supply Noise

Sensitive Analog Circuitry safe from

Digital Supply Noise

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Grounding Mixed Signal ICs with LowInternal Digital Currents: Multiple PC Boards

ANALOGCIRCUITS

DIGITALCIRCUITS

A A D D

VA VD

ANALOGGROUND PLANE

DIGITALGROUND PLANE

MIXEDSIGNALDEVICE

AGND DGND

A A D D

TO SYSTEM STAR GROUND

TO SYSTEM DIGITAL SUPPLY

TO SYSTEM ANALOG SUPPLY

A

VA VDBUFFERLATCH

FILTER

VN

BUSR

VN = NOISE BETWEEN GROUND PLANES

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Star Ground System which has Separated Analog and Digital Ground Planes

POWERSUPPLIES

ANALOGGROUNDPLANE

DIGITALGROUNDPLANE

A D

ANALOGGROUNDPLANE

DIGITALGROUNDPLANE

A D

VA

VD

VA VAVD VD

ANALOG GROUND PLANE

DIGITAL GROUND PLANE

BACKPLANE

PCB PCB

SYSTEMSTAR

GROUND

X

XNot Over Lay

X

XX

No connection

X

X

No connection

X X

High Voltage Capacitor may need here to provide high frequency interference shot cut path (for EMC/EMI purpose)

VNVN



Using Ground Plane

ADI

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Characteristics of Ground PlanesDigital Radios frequently have high speed digital logic on the same board as high gain RF electronics. Shielding and Grounding are significant aspects of the receiver design.

Radiation should be shielded at the sourceGround currents should be returned to their sourceSupply currents should take the path of least resistance & inductance back to the source

Minimum 1 whole ground layerOne entire PCB side (or layer) is a continuous ground conductor

Gives minimum ground resistance and inductance, but itn’t always sufficient to solve all ground problems.Breaks in ground planes can improve or degrade circuit performance – there is no general ruls

Eliminate the possibility ground loopsCareful attention should be paid to layout to ensure that digital return currents do not flow through analog section of the board.

Using Mulit-layer (>=4) with ground and voltage plane

Ground plane acts as a shield

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How to make full use of your Ground Plane?Provide as much ground plane as possible

Especially under traces that operate at high frequencyUse thickest metal as feasible

Reduces resistance and provides improved thermal pathHelps reduce resistive losses due to skin effect

Mount components that conduct fast rise times or high frequencies as close to the board as possible

Minimize use of leaded componentsTry to single-point the critical components into the ground plane to avoid voltage drops.Provide as much ground plane as possible

Especially under traces that operate at high frequency

Use thickest metal as feasibleReduces resistance and provides improved thermal path)Helps reduce resistive losses due to skin effect

Mount components that conduct fast rise times or high frequencies as close to the board as possible

Minimize use of leaded components

Try to single-point the critical components into the ground plane to avoid voltage drops.Confine Analog circuitry to one section and digital circuitry to another.Avoid running digital and analog tracks close to each other, this will help avoid coupling digital noise into analog lines.

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Grounding example of solid ground plane

Single GND Layer for High Speed Converters PCB board.

Cover empty space of TOP / Bottom layer with GND, but no small unconnected island.Via to connect 2 or more GND layer, as many as possible but do not cut some plane to pieces.

ExampleThe top layer is solid ground. The Bottom has a trace connecting the RF connector to the load. Return current flows from the load back to the RF connector, directly above the trace on the opposite side.

Res

isto

r

Top Side

Bottom side

I

Dielectric

Ground PlaneTop TraceI

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Grounding Example of split ground plane

Res

isto

r

ADC Dig

ital

Ground LoopPotential coupling to input

transformer

Ground loops are introduced by splitting the two grounds. For example, a digital line that switches at 1 V/nS into a 10 pF load will

generate a 10 mA transient. If 16 lines move at the same time, this is 160 mA of switching current in the loop!

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Grounding – DC current vs. AC currentSingle GND or Split GND plane

To be simple, using signal GND layer for High Speed Converts layout (>10MHz), no AGND and DGND layer difference. Separated AGND and DGND and connect with signal point only applies in low speed design (less than 1MHz).Some cut lines allowed to separate difference area, but connection must be bigger than Component (>10mm width). And no signal trace cross cut lines. If all frequency range are consider (IE, sampling signal from DC to 50MHz), then ground layer is difficult, need case by case study.

ExampleIn a broken ground or split ground, the return currents follow the path of least impedance. At DC, the current follows the path of least resistance. As the frequency increases, the current follows the path of least inductance.Since there is now a ‘loop’ the inductance can be quite high and an EMI/RFI problem can exist.

Res

isto

r

DC current follows the

path of least resistance

AC current follows the

path of least impedance

Top Side

Bottom side

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Cut lines with good Component placement

Separate Analog area, mixer signal area and pure digital area.No cross over of input and out put.Clock area is an independent area.Power supply is an independent area, especially DC-DC area.

DC-DC must be a corner, better in an other PCB board.Cut lines must be used for DC-DC.Big Capacitors must be in a corner or near PCB boundary.

FPGA

Amp

Amp

ADC

ADC DSP

DAC

DAC

Amp

AmpVin2

Vin1 Vout1

Vout2

SDRAM

Connector 1 Connector 2

ClockClockLDO LDO

Big Capacitors

Big Capacitors

LDO LDO

GND Cut Line

GND Cut Line

DGND Area



Power Filter&

Decoupling Capacitor

consideration

ADI Confidential 66

C1100μF/20V

TANTALUM

R11Ω

3-5V NOISY INPUT FROM SWITCHING SUPPLY OR

DC-DC CONVERTER

C21μF

CERAMIC

L1 *

100μH

+ +

- -

3-5V CLEAN OUTPUT TO

300mA LOAD ANALOG STAGE

+

* Fastron MESC series or equivalent

Regulation priorities for power supply systems

A Card-entry Filter is useful for low medium frequency power line noise filtering in analog systemDual-Supply low frequency rail bypass / distribution filter for Power distribution.High performance analog power systems use linear regulators, with primary power derived from:

AC line powerBattery power systemsDC- DC power conversion systems

Remember Electrolytic Capacitor Impedance vary with Frequency

TOINDIVIDUALSTAGE +VS

RAILC1

100μF/25V

C2100μF/

25V

#1#2#3

#1#2#3

TOINDIVIDUALSTAGE -VS

RAIL

+VS RAILINPUT

-VS RAILINPUT

COMMON(GND)INPUT

CARDCONNECTOR

MULTIPLEPIN

CONTACTS GROUND PLANE

ESR = 0.2Ω

10kHz 1MHz

LOG FREQUENCY

LOG|Z|

C (100µF)REGION

ESL (20nH)

REGION

ESR (0.2Ω)REGION

ADI Confidential 67

DC-DC power filter

Switching regulators should be avoided if at all possible, but if not…Apply noise control techniquesUse quality layout and groundingBe aware of EMI ADI do not suggest DC-DC power supply as analog power supply, at least add LDO

DC-DC power supply can be used as digital power supply of ADC or MCV (ADuC702x)Let the DC-DC far away from ADC (or ADuC702x)The C-L-C filter near DC-DC. Still need 0.1uF on each power pin. Big 3.3V plane in Power layer helps a lot.

DC-DC+12VF.B.F.B.

Added the C-L-C filter to remove to switching noise generated from DC-DC.Those components have to enclose the DC-DC Vin pin as possible.C1, C2 need consider switch frequency (50k, 100k, 1.2M)

+3.3V

47uF0.1uFC2C1

Via from 3.3V layer

0.1uF0.1uF

0.1uF

Pin1

Pin3

Pin2Power layer

10uF

ADI Confidential 68

Grounding and Decoupling Points

AMP

VA VD

VA

A

A

AGND DGND

ADCOR

DAC

VA

A

VOLTAGEREFERENCE

VA

A

SAMPLINGCLOCK

GENERATOR

A A

VA

A

BUFFERGATE

ORREGISTER

VD

D

D

A A

R

R

AANALOG

GROUND PLANE

DDIGITAL

GROUND PLANE

TO OTHERDIGITAL

CIRCUITS

FERRITEBEAD

SEE TEXT

ADI Confidential 69

V+

GNDVIAS TOGROUNDPLANE

DECOUPLINGCAPACITOR

V+

GND

DECOUPLINGCAPACITOR

VIA TOGROUNDPLANE

PCBTRACEIC IC

POWERSUPPLYTRACE

POWERSUPPLYTRACE

CORRECT INCORRECTOPTIONAL

FERRITE BEADS

Decoupling on SOIC parts

RULE OF THUMB: VIA RESISTANCE ≈ 1mΩ, VIA INDUCTANCE ≈ 1nH

Localized high frequency supply filters provide optimum filtering and decoupling via short low inductance path (ground plane)Rule of Thumb:

Via resistance ≈ 1mΩ, Via inductance ≈ 1nH

ADI Confidential

Decoupling on LQFP/LFCSP parts

C

Via

C

Correct

Wrong

Wrong

CorrectWrong

C

No long trace under ICShort trace then to bottom by via

Short trace to GND or Power under IC.Short trace to decouple Capacitors

Maybe your AD9779 Layout like this!

VCCGND

LQFPLFCSP

VCC

VCC

VCC

GND

GND

GN

D

GN

D

GN

D

GN

D

GN

D

ADI Confidential 71

Different Capacitors’ Impedance vs. Frequency

Paralleling caps reduces impedance over a wider frequency range.Put the smaller decoupling capcitor as near as possible to power pin.

2.2uF 0.1uF

0.01uF 1000pF 100pf2.2uF

0.1uF

0.01uF

1000pF

100pf

MuRata 0805 GMR216 SERIES

ADI Confidential 72

Why every power pin need decoupling Caps?

ANALOGCIRCUITS

DIGITALCIRCUITS

BUFFERGATE ORREGISTER

VA

A B

VD

CSTRAY

CSTRAY

R

A

A A D

D

VNOISE

VA

AIN/OUT

AGND DGND

DATABUS

FERRITE BEAD

DATA

VD

A = ANALOG GROUND PLANE D = DIGITAL GROUND PLANE

CIN ≈ 10pF

LP LP

LP LP

RP

RP RP

RP

SHORTCONNECTIONS

IA ID

ADI Confidential 73

Low Speed High Resolution ADC layout Skills ExampleAD7656 possible issue in Grounding and Decoupling

ANALOGCIRCUITS

DIGITALCIRCUITS

A A D D

D

VA VD

ANALOGGROUND PLANE

DIGITALGROUND PLANE

AGND DGND

AD7656

A

DIGITALSUPPLY

ANALOGSUPPLY

SYSTEMSTAR

GROUND

VA VD

AD7656 Missing code (No codes between 0 ~ -32)

Poor Grounding and poor power supply

+5V AVCC must be very stableHalf AVCC power plan, half DVCC power plan. Use wide trace (>1mm) for +/-12V power supply on bottom layer, aviod +/-12V cut AVCC power layer to piecesSingle point connect AGND and DGND

Insufficient decouple220uF Decoupling Cap for each AD765610uF + 0.1uF for each AVCC pin (8pins total)Short but wide trace from Via to AVCC pinLeadless capacitor layout

ADI Confidential 74

Summary of Power Supply Bypassing & decoupling

Place bypass caps as close to the power supply pins as possible

SMT ferrite beads are very effective in reducing ripple contentHigh Frequency requires ground plane

Minimize parasiticsUse stable, well behaved components

Low drift and low ESRCompletely Analytical Approaches can be difficult

Prototyping is required for optimal results

Use a combination of paralleled capacitors to achieve frequency rejection of unwanted noise across a wide bandwidth



ParasiticConsideration

ADI

ADI Confidential 76

Approximate Trace Inductance

Example

L= 2.54cm =25.4mm, W = 0.25mm

H = .035mm (1oz copper)

Strip Inductance = 28.8nH

At 10MHz ZL = 1.86 Ω a 3.6% error in a 50Ωsystem

All dimensions are in mm

Minimize Inductance 1) Use Ground plane 2) Keep length short: Halving the

length reduces inductance by 44%

3) Doubling width only reduces inductance by 11%

2LLW+H

W+H( ))STRIP INDUCTANCE = 0.0002L ln + 0.2235 + 0.5 μH(

1cm of 0.25 mm PC track has an inductance of 9.59 nH(H = 0.038mm, W = 0.25mm, L = 1cm)

L

W H

ADI Confidential 77

Trace/Pad Capacitance

d dkAC

3.11=

A

K = relative dielectric constant

Reduce Capacitance1) Increase board thickness 2) Reduce trace/pad area 3) Remove ground plane

Example: Pad of SOIC

L = 0.2cm W = 0.063cm

K= 4.7

A = 0.126cm2

d = 0.073cm

C = 0.072pF

Capacity of PC track over ground plane is roughly 2.8pF/cm

Most common PCB type uses 1.5mm glass-fiber epoxy material with E = 4.7

0.00885 E Ad

r

r

2

C = pF

A = plate area in mm

d = plate separation in mm

E = dielectric constant relative to air

ADI Confidential 78

INTERFERENCE CIRCUIT SIGNAL CIRCUIT

M = MUTUAL INDUCTANCEB = MAGNETIC FLUX DENSITYA = AREA OF SIGNAL LOOPωN = 2πfN = FREQUENCY OF NOISE SOURCE

V = INDUCED VOLTAGE = ωNMIN = ωAB

BASIC PRINCIPLES OF COUPLING

C

INVN Z1 VCOUPLED

Z1 = CIRCUIT IMPEDANCEZ2 = 1/jωC

VCOUPLED = VN⎛⎜⎝

Z1Z1 + Z2

)

CAPACITIVE COUPLING EQUIVALENT CIRCUIT MODEL

BASIC PRINCIPLES OF INDUCTIVE COUPLING

ADI Confidential 79

0

IPEAK = 1A

didt

Ans

=1

100

Equivalent f = 3.5MHz

0

VPEAK ESL didt

ESR IPEAK mV

= •

+ • = 400

ESL = 20nH

ESR = 0.2Ω

C = 100µFXC = 0.0005Ω @ 3.5MHz

INPUTCURRENT

OUTPUTVOLTAGE

v

i

ESR • IPEAK = 200mV

CAPACITOR EQUIVALENT CIRCUIT AND RESPONSE TO INPUT CURRENT PULSE

ADI Confidential 80

Via Parasitics

⎥⎦

⎤⎢⎣

⎡+⎟

⎠⎞

⎜⎝⎛= 14ln2

dhhL

L = inductance of the via, nHH = length of via, cmD = diameter of via, cmConsider a power supply pin of an op amp that goes through a via to the power plane of an 0.157 cm thick board, the diameter of the via is 0.041 cm

Via Inductance Via Capacitance

⎥⎦

⎤⎢⎣

⎡+⎟

⎠⎞

⎜⎝⎛= 1

041.0)157.0(4ln)157.0(2L

L = 1.2nh

12

155.0DDTDC r

−=

ε

D2 = diameter of clearance hole in the ground plane, cmD1 = diameter of pad surrounding via, cmT = thickness of printed circuit board, cm

= relative electric permeability of circuit board materialC = parasitic via capacitance, pF

Consider a signal coming from the back of the board to the top of the board through a via. Board thickness = 0.157cm, D1=0.071cm D2 = 0.127

C = 0.51pf

rε

nH

ADI Confidential 81

Parasitic Model

C = CapacitorRP = insulation resistance RS = equivalent series resistance (ESR)L = series inductance of the leads and plates RDA = dielectric absorptionCDA = dielectric absorption

L

r

RP

C

RDA CDA

RS

Capacitor Parasitic Model

CP

R

L

R = ResistorCP = Parallel capacitanceL= equivalent series inductance (ESL)

Resistor Parasitic Model

ADI Confidential 82

Stray Capacitance & Stray Inductance at inverting input RF

RG

VO

VI

-V

RL

VIA

PAD

TRACE

VIA

TRACEPAD

PAD

PAD PADPAD

PAD

PAD

PAD

PAD

PAD

PAD

+V

TRACEStray Capacitance

Low Frequency Op Amp Schematic High Frequency Op Amp Model

RF

RG

Vi

+V

-V

RL

Stray Inductance

ADI Confidential 83

Stray Capacitance Simulation

R31

1k

V21-5

V

U11

AD8055an/AD

3

2

74

6+

-

V+V-

OUT

0

V115

0

0

R11

150

C8

1pf

0

R21

1k

0

0V34

1V

1pF stray capacitance

1.8dB peaking

6.5% overshoot

Pulse Response with 1pF Stray Capacitance

Frequency Response with 1pF Stray Capacitance

Reduce Overshoot1) Increase board thickness 2) Reduce trace/pad area 3) Remove ground plane 4) Lower Resistance

ADI Confidential 84

Stray Inductance Simulation Schematic

0

0

0

0

0

R11

150

R21

1k

R31

1k

U11

AD8055an/AD

3

2

74

6+

-

V+

V-

OUT

V31

V21-5

V115

L7

29nH

AD8055

1”x0.01” =29nH

Pulse Response With and Without Ground Plane

Approximately 0.6dB over shoot.

ADI Confidential 85

Layouts – What to do and not do!

Good PCB layout

RI+Vs

NC -Vs

+IN

-In

NC

Vout

Disable

C

RL C

RF

Bad PCB layout

XInput Grounds

RL

RI

NC

+Vs

NC -Vs

+IN

-In

Disable

Vout

C

C

RF

Vias and long return distance adds several nHEven a few pF on summing

junction can destabilize op amp

Remove ground plane under Negative input to

reduce input capacitance

Reduce return path length to reduce Inductance

ADI Confidential 86

Power Supply Bypassing

ADXXXX

Correct

ADXXXX

Incorrect

Electrolytic Bypass

Elec

trol

ytic

B

ypas

s

Elec

trol

ytic

B

ypas

s

Electrolytic B

ypass

Ceramic

Ceram

ic

Cer

amic

Cer

amic

ADI Confidential 87

SOIC Layout Example

RG

Disable

VIN

-VS

ElectrolyticBypass

CeramicBypass

Vout

RF

C1

CompCap

RC

Elec

trol

ytic

Byp

ass

ADI Confidential 88

AD8099 Layout Example

RFRL

Disable

+VS

RC C1

CC

VIN

VO

-VS

Ceramic Bypass

Ceramic Bypass

ElectrolyticBypass

ElectrolyticBypass

RG

0402components



Control Differential Line Impedance

ADI

ADI Confidential 90

Typical LVDS Driver in CMOS

(3.5mA)

(3.5mA)

+3.3V)

3.5kΩ 3.5kΩ

+1.2V

(3.5mA)

(3.5mA)

OUTPUT DRIVER+3.3V)

3.5kΩ 3.5kΩ

+1.2V

V+

V+V–

V–

A standard LVDS driver in CMOS.The nominal current is 3.5mA, and the common-mode voltage is 1.2V.

The swing on each input at the receiver is therefore 350mV p-p when driving a 100Ωdifferential termination resistor.

This corresponds to a differential swing of 700mV p-p.

ADI Confidential 91

Differential Line impedances

dtw w

h εr

2*]ln[*[ )8.0(67.04

67.0475.060

dwh

r ++εZodiff(Ω)=

εr = 3.8~4.0 @1.65Gbps

ADI Confidential 92

Control Differential Line Impendence

Control differential line impendenceTrace characteristic impedance will be around 54 Ohm single / 102 Ohm differential on ½ OZ copper (1.7mil) with dielectric of 4.7. After coating, it will change about 5-12 Ohm. Distance between Differential line pair should be greater than 30mil to avoid interference of adjacent pairs.

Lower down the length of differential linesIt’s better to control >100MHz clock or RF signal trace length less than 2 inch.

Routing differential signal pair together and minimize the total numbers of via on each trace as few as possible.

Recommend softwarePolar Si6000

1/2oz

6mil

Top Layer

Dielectric Layer

GND Layer

8mil 8mil

12mil 8.1mil30mil

RX0+ RX0- RX1+ RX1-

GND

ADI Confidential 93

Measuring the TMDS pair impedance

WaveformDigitizer

D.U.T

incident

Reflections

High SpeedS/H

50 Ohm

TDRStep

Generator

TDR (Time Domain Reflector)

ADI Confidential 94

The Visual lumped interconnect analysis using TDR

ADI Confidential 95

Summary Mixed Signal Layout Techniques

Use ground planeHigh speed applications require low impedance returnsHelps minimize parasitics

ParasiticsParasitic capacitance, inductance and resistance can ruin the best designed circuitLayout is critical!

Shielding Long WireControl Differential Line Impendence


Small Signal PCB Layout

Consider loss on Track Resistor

ADI Confidential 97

R

X

Z

Y

ρ = RESISTIVITYR =

ρX

ZY

SHEET RESISTANCE CALCULATION FOR1 OZ. COPPER CONDUCTOR:

ρ = 1.724 X 10–6 Ωcm, Y = 0.0036cm

R = 0.48 m Ω

= NUMBER OF SQUARES

R = SHEET RESISTANCE OF 1 SQUARE (Z=X)= 0.48mΩ/SQUARE

XZ

XZ

Calculation of Sheet resistance (For Standard Copper PCB)

ADI Confidential 98

16-BIT ADC,RIN = 5kΩ

SIGNALSOURCE

0.25mm (10 mils) wide,1 oz. copper PCB trace

5cm

Assume ground pathresistance negligible

Long Track Resistance Impact on ADC

OHM’s Law predicts >1 LSB of error due to drop in PCB conductor.Consider a 16-bit ADC with a 5kΩ input resistance, PCB track is 5cm of 0.25mm wide 1 oz. The track resistance of nearly 0.1Ω.The resulting voltage drop is a gain error of 0.1/5k (~0.0019%), Over 1LSB (0.0015% for 16 bits).

ADI Confidential 99

G2

RGROUND0.01Ω

U1AD8551

R199kΩ

R21kΩ

G1

ISUPPLY700μA

+5V

VIN5mV FS

VOUT

ΔV ≅ 7μV

Small Common Ground Currents can degrade Precision Amplifier Accuracy

A low-level signal VIN of 5mV FS, Design required to precisely gain of 100.Using an AD8551 chopper-stabilized amplifier for best dc accuracy.Recall AD8551 Spec:

Low offset voltage: 1 μV, offset drift: 0.005 μV/°CAt the load end, the signal VOUT is measured with respect to G2, the local ground.

Because of the small 700μA ISUPPLY of the AD8551 flowing between G1 and G2, there is a 7μV ground error on 0.01Ohm Ground impedance.About 7 times the typical input offset expected from the op amp!

ADI Confidential 100

A More Realistic Model of a Ground System

Any current flow through a common ground impedance can cause errorsΔV = (I + i) * Z

Z: The impedance between G1 and G2 I : Signal related currents.i : The effect of any non-signal related currents.

ΔV

SIGNALHIGH CURRENT CIRCUIT

SIGNAL SOURCE

ADC

+Vs

With changes,this becomes "star" ground

G1 G2IiZ



Proper Grounding Shielding Cable


Ground loops in shield twisted pair cable can cause errorsVN Causes Current in Shield (Usually 50/60Hz)Differential Error Voltage is Produced at Input of A2 Unless:A1 Output is Perfectly Balanced andA2 Input is Perfectly Balanced andCable is Perfectly Balanced

A2A1

VN

IN

GND 1 GND 2

Ground loops in shield twisted pair cable

NC

C

RTD

RTD

BRIDGEAND

CONDITIONINGCIRCUITS

BRIDGEAND

CONDITIONINGCIRCUITS

“HYBRID”GROUND

Hybrid grounding of shielded cable with passive sensor


A2

C

A1

A1 A2

C

RS/2

RS/2

RS/2

RS/2

Impedance-balanced Driver of Balanced Drive of Balanced Shielded Cable & Coaxial Cables

A1 A2

COAX CABLE

Shield Carries Signal Return Current

A1 A2

DIFFAMP

SINGLE-ENDED

AMP

Impedance-balanced driver of balanced drive of balanced shielded cable aids noise-immunity with either balanced or single end source signals

Coaxial cables can use either balanced or single-ender receivers


DIELECTRIC

TRACEW

H

T

GROUND PLANE

Transmitter low level IF/RF signal with Micro-Strip line

A micro-strip transmission line with defined impedance is formed by a PCB trace of appropriated geometry, spaced from a ground plane.

A Symmetric strip line transmission line with defined impedance is formed by a PCB trace of appropriate geometry embedded between equally spaced ground and/or power planes.

DIELECTRIC

EMBEDDEDTRACE

W

H

TGROUND, POWERPLANES

B

H


NOT EMBEDDED

Route

Power

Ground

Route

Power

Route

Route

Ground

EMBEDDED

The pros and cons of not embedded vs the embedded signal trace in multi-layer PCB design

Fast switching signals (clocks etc) should be shieldedUsing digital ground to avoid radiating noiseClock signals should never be run near analog inputs of the devicesAvoid cross over of digital and analog signals.

Advantages of embedded tracesSignal traces shielded and protectedLower impedance, thus lower emissions and crosstalk Significant improvement > 50MHz

Disadvantages of embedded tracesDifficult prototyping and troubleshootingDecoupling may be more difficultImpedance may be too low for easy matching



Minimize PCB Leakage by Guard

Ring


Using Guard-Rings Minimizes PCB Leakage Paths

Leakage current from +Vspin to -Vin through FR4

SOT23-5 package is 50XInput bias current

100k

+5v

-5v

Vout

.1uF

.1uF

-5v

0.33pF

1x1011

+5v50pA

1pA

ID - 50pA

ID

Result is an errorin the output

voltage at lowlevel input

signals

Board leakage resistance

+IN

+V

-IN

Vout

-V

AD8067

Inverting

Guard-Ring Layout for SOT-23 Guard-Ring Layout for SOIC / MSOP


Guard Patterns

INPUT

GUARD

GUARD–V S

1

2

3

4 5

6

7

8GUARD

INPUT

GUARD

1

2

3

4 5

6

7

8

–V S

INVERTING MODEGUARD PATTERN

NON-INVERTING MODEGUARD PATTERN

NOTE: PINS 1, 5, & 8 ARE OPEN ON MANY “R” PACKAGED DEVICES

PCB GUARD PATTERNS FOR INVERTING AND NON-INVERTING MODE OP AMPS USING 8 PIN SOIC (R) PACKAGE

INVERTING MODE GUARD:RING SURROUNDS ALL LEADENDS AT THE "HOT NODE"

AND NOTHING ELSE Example application:Photodiode Preamps

INVERTING MODE GUARD ENCLOSES ALL OP AMP INVERTING INPUT CONNECTIONS WITHIN A GROUNDED GUARD RING

NON-INVERTING MODE GUARD:

RING SURROUNDS ALL "HOT NODE"LEAD ENDS - INCLUDING INPUT

TERMINAL ON THE PCB

LOW VALUE GAINRESISTORS

RL

USE SHIELDING (Y) ORUNITY-GAIN BUFFER

(X) IF GUARD HAS LONGLEAD

Y

Y

Y X

Y

NON-INVERTING MODE GUARD ENCLOSES ALL OP AMP NON-INVERTING INPUT CONNECTIONS WITHIN A LOW IMPEDANCE, DRIVEN GUARD RING


Summary of PCB Layout Skills For Low PCB Leakage Applications

Including photodiodes, pressure sensors, and other high source impedance inputs

#1) Use a CMOS or JFET input amplifier

#2) Minimize the PC-board leakage currentKeep trace lengths as short as possibleUse guard rings around the input pins

#3) Keep the board CLEAN!!Dirt and oil are a major cause of PC-board leakage current



Minimize PCB Heating Temperature Sensors


Minimize PCB Heating Temperature Sensors BasicsHeat Transfer

• The transfer of heat is normally from a high temperature object to a lower temperature object.

•Heat transfer from a cold region to a hot region can be done by forcing the system e.g. refrigerators, to perform the energy transfer.

• Heat transfer is accomplished by three basic methods –•Conduction•Convection•Radiation

Conduction Convection Radiation


Minimize PCB Heating Temperature Sensors Basics Heat Transfer Theory - Conduction

• Conduction is the most prevalent heat transfer method in pcbs

•If one end of a PCB is at a higher temperature, then energy will be transferred down the PCB towards the colder end. The higher speed particles will collide with the slower ones with a net transfer of energy to the slower ones. The rate of conduction heat transfer is:

H = (K x A (THOT – TCOLD) / L

H = Energy conducted in time (joules/second)K = Thermal conductivity of the copper (385 W/(m·K)

@ room temp)A = Area of copper on pcb

T = TemperatureL = Distance between hot and cold bodies

A

H

T

0.01Styrofoam

0.017Silica aerogel

0.026Air (300 K, 100 kPa)

0.03Expanded polystyrene ("beadboard")

0.04Fiberglass

0.05Wool

0.04-0.12Wood

0.6Water

0.8Glass

1.6Ice

8Quartz

8.3Mercury

34.7Lead

50.2Steel

70Platinum

109Brass

205Aluminium

320Gold

385Copper

406Silver

1000-2600Diamond

W/m·K

Thermal conductivityMaterial

Excellent Temperature Conductive Material


Minimize PCB Heating Temperature SensorsCorrect PCB layout for measuring ambient temperature

Main Heat Source(uController)

TempSensor

• Many designers don’t want to measure the PCB temperature• Just want to measure the ambient air temperature• Problem is, how do you prevent the heat from the PCB heat sources affecting the ambient temperature measurement of the temp sensor

• Use a hatched GND plane. Reduce GND plane area therefore increasing thermal resistance.• Keep the temp sensor as far away from heat sources as possible.• Use a separate GND plane for the temp sensor and keep connections to main GND plane as low as possible.• Use narrow GND connections as this will increase thermal resistance.• Use solid GND plane under main heat source and expose green solder mask. This will give the min thermal resistance for the MHS to dissipate heat.

Tips for ambient temperature measurement


Minimize PCB Heating Temperature SensorsSummary...

• There will be some customers that want to monitor air temperature and also use the accuracy, linearity, speedy response and convenience of an IC temp sensor.• Therefore they should use this pcb layout technique.

H = (K x A (THOT – TCOLD) / L

H = Energy conducted in time (joules/second)K = Thermal conductivity of the copper (385 W/(m·K) @ room temp)

A = Area of GND planeT = Temperature

L = Distance between hot and cold bodies

• Most customers will want to use IC Temp Sensors to measure the temperature of the PCB or a component.•Therefore it is better to use this pcb layout technique.


Backup


Further References1. “High-Speed Digital Design - A Handbook of Black Magic”, Howard W. Johnson,

Martin Graham, Prentice-Hall, 1993, ISBN 0-13-395724-12. “Tolerance Calculations in Power Distribution Networks”, Istvan Novak, Sun

Microsystems, Note published in Xcell Journal, Summer 2004. Available at www.Xilinx.com

3. “Power Distribution System (PDS) Design; Using Bypass/Decoupling Capacitors”, Mark Alexander, Xilinx Application Note, XAPP623 (V2.0) April 2004

4. “Decoupling Basics”, Arch Martin, AVX Corp Application Note, 5. “The Effects of ESR & ESL in Digital Decoupling Applications”, Jeffrey Cain, Ph.D.,

AVX Corp Application Note6. “High Speed PCB Design & System Design”, Course notes, Instructor Lee Ritchie,

UC Berkeley Engineering Extension, May 1998.7. “Bypass Capacitor Selection for High-Speed Designs”, Micron Technical Note, TN-

00-068. “Effective Decoupling Radius of Capacitor”, H. Chen, J. Fang, W. Shi, paper

presented at 2001 EPEP conference.9. “ESR & Bypass Capacitor Self Resonant Behavior – How to Select Bypass Caps”,

Douglas Brooks, UltraCAD Design, Inc., 200010. “Optimum Placement of Decoupling Capacitors on Packages & Printed Circuit

Boards Under the Guidance of Electromagnetic Field Simulation”, Y. Chen, Z. Chen, J. Fang, Conf’ Proc’, 46th Electronic Components & Technology Conf, Orlando Fl, 1996.

11. “Low-Impedance Power Delivery Over Broad Frequencies”, J. Fang, J. Zhao, Printed Circuit Design & Manufacture, Sept, 2003.

12. “Right the First Time – A Practical Handbook on High Speed PCB & System Design”, Lee W. Ritchey, Speeding Edge, May 2003, ISBN 0-9741936-0-7


PCB BasicsVias

Vias (plated holes)Used to connect layersFormed by drilling or punching hole through PCB and plating the insideTypically much larger than signal traces

Blind Signal Integrity Tip: PCBs introduce capacitance and change the characteristic impedance of a trace.


PCB BasicsVias Types

Vias (plated holes)Used to connect layersTypically much larger than signal traces

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