Pass Transistor Logic.pdf
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Transcript of Pass Transistor Logic.pdf
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Pass Transistor and
Transmission Gate Logic
P.K. Shetty, MCIS, Manipal
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Building Logic Circuits
In designing digital systems in MOS technology
there are 2 basic ways of building logic circuits:
Switch Logic
Pass Transistor Logic
Transmission Gate Logic
Gate (Restoring) Logic
P.K. Shetty, MCIS, Manipal
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Pass Transistor Logic
Approach is faster for smaller arrays
Takes no static current from the supply rails. Thus power
dissipation of such arrays is small since current only flows on
switching
The path through each switch is isolated from the signal
activating the switch
N transistors instead of 2N
No static power consumption
Ratioless
Bidirectional (versus undirectional)
B
P.K. Shetty, MCIS, Manipal
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Pass Transistor - Drawbacks
Undesirable threshold voltage effects which give rise to
the loss of logic levels (Logic level degradation)
VDD output
X (=1)
VDD output
X’ (=0)
1
0
Vtn 1
0 Vtp
Pure PT logic is not regenerative - the signal gradually degrades after
passing through a number of PTs (can fix with static CMOS inverter
insertion)
P.K. Shetty, MCIS, Manipal
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Complementary PT Logic (CPL)
P.K. Shetty, MCIS, Manipal
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CPL Properties
Differential; so complementary data inputs and outputs are always available (so don’t need extra inverters)
Still static, since the output defining nodes are always tied to VDD or GND through a low resistance path
Design is modular; all gates use the same topology, only the inputs are permuted.
Simple XOR makes it attractive for structures like adders
Fast (assuming number of transistors in series is small)
Additional routing overhead for complementary signals
Still have static power dissipation problems
P.K. Shetty, MCIS, Manipal
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4-input NAND in CPL
P.K. Shetty, MCIS, Manipal
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CPL Full Adder
P.K. Shetty, MCIS, Manipal
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NMOS Only PT Driving an Inverter
Vx does not pull up to VDD, but VDD – VTn
Threshold voltage drop causes static power consumption (M2
may be weakly conducting forming a path from VDD to GND)
Notice VTn increase of pass transistor due to body effect (VSB)
P.K. Shetty, MCIS, Manipal
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Voltage Swing of PT Driving an Inverter
Body effect – large VSB at x - when pulling high (B is tied to GND and S charged up close to VDD)
So the voltage drop is even worse
Vx = VDD - (VTn0 + γ(√(|2φf| + Vx) - √|2φf|))
P.K. Shetty, MCIS, Manipal
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Cascaded NMOS Only PTs
Pass transistor gates should never be cascaded as on the left
Logic on the right suffers from static power dissipation and reduced noise margins
P.K. Shetty, MCIS, Manipal
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Transmission Gate (TG) Logic
The degradation of logic levels in simple n or p switches
can be overcome by using transmission gates, comprising
an n-pass and p-pass transistors in parallel.
C A B
C
Transmission Gate Symbols Used
P.K. Shetty, MCIS, Manipal
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Transmission Gates (TG)
Most widely used
Full swing bidirectional switch controlled by the gate
signal C.
A = B if C = 1
P.K. Shetty, MCIS, Manipal
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Resistance of TG
P.K. Shetty, MCIS, Manipal
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TG Multiplexer
P.K. Shetty, MCIS, Manipal
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TG XOR
P.K. Shetty, MCIS, Manipal
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TG Full Adder
P.K. Shetty, MCIS, Manipal
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Differential TG Logic
P.K. Shetty, MCIS, Manipal
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Transmission Gate - Drawbacks
Occupies more area – one pass transistor is replaced by
2 transistors
Requires complementary signals to drive it
P.K. Shetty, MCIS, Manipal
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Gate Logic
Inverter – the most basic gate
In
Out
VDD
VGG
Load (pull-up)
Driver (pull-down)
Note: The driver transistor is enhancement mode device to satisfy
I/O compatibility.
P.K. Shetty, MCIS, Manipal
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Basic Single Channel Inverters
1. If VGG–VT > VDD then the load is said to be NELT (N-channel Enhancement Load in Triode region) – Needs a separate supply.
2. If the load is maintained in the saturation region throughout, then the load is said to be NELS (N-channel Enhancement Load in Saturation)
3. HMOS (High performance MOS) – Trademark given to Intel.
In Out
VDD
VGG
In Out
VDD
In Out
VDD
1. NELT 2. NELS 3. HMOS
P.K. Shetty, MCIS, Manipal
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HMOS
The load is a depletion mode transistor.
Advantages:
Good noise margin
High speed
Low power consumption
High packing density
Limitations:
It is difficult to fabricate both enhancement and depletion mode
MOSFETs together
(W/L)Load
(W/L)Driver
R = Determines the performance of the Inverter.
P.K. Shetty, MCIS, Manipal
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Realization of Basic Gates
1. NOR Gate
A
F
VDD
B C
A
F
VDD
B
C
2. NAND Gate
P.K. Shetty, MCIS, Manipal
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Power Dissipation in Single Channel
Inverters
NELS : P VDD3
NELT : P VDD3
HMOS: P = ½LVDD VP;
P VDD
P.K. Shetty, MCIS, Manipal
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CMOS Inverter
Realized by the series connection of a p and n
device, as shown.
Vin Vout
P.K. Shetty, MCIS, Manipal