Pass transistor logic
-
Upload
tripurna-chary -
Category
Documents
-
view
2.295 -
download
3
Transcript of Pass transistor logic
Pass Transistor Pass Transistor LogicLogic
AgendaAgenda
Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated Electronics Static CMOS Logic Circuits Pseudo nMOS Logic Circuits Pass Transistor Logic Circuits Dynamic Logic Circuits Case Studies
Pass Transistor Logic Pass Transistor Logic CircuitsCircuits nMOS Pass transistor – transmission
properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
nMOS Pass Transistor – Logic ‘1’ nMOS Pass Transistor – Logic ‘1’ TransferTransfer
nMOS Pass Transistor – Logic nMOS Pass Transistor – Logic ‘0’ Transfer‘0’ Transfer
PASS TRANSISTORS IN SERIES
PASS TRANSISTOR LOGIC PASS TRANSISTOR LOGIC CIRCUITSCIRCUITS
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
TRANSMISSION GATESTRANSMISSION GATES
NMOS pass transistor passes a strong 0 and a weak 1. PMOS pass transistor passes a strong 1 and a weak 0. Combine the two to make a CMOS pass gate which will pass a strong 0 and a strong 1.
TRANSMISSION GATETRANSMISSION GATE
PROBLEMS WITH PROBLEMS WITH TRANSMISSION GATESTRANSMISSION GATES
No isolation between the input and output. Output progressively deteriorates as it passes through
various stages. However designs get simplified.
TRANSMISSION GATE - LAYOUTTRANSMISSION GATE - LAYOUT
PASS TRANSISTOR LOGIC PASS TRANSISTOR LOGIC CIRCUITSCIRCUITS
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
MultiplexorMultiplexor
Pass Transistor Logic CircuitsPass Transistor Logic Circuits
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
XOR gateXOR gate
PASS TRANSISTOR LOGIC PASS TRANSISTOR LOGIC CIRCUITSCIRCUITS
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
D – Latch D – Latch
TIMING ISSUESTIMING ISSUES
D LATCHD LATCH
D - LATCHD - LATCH
D LATCH – ALTERNATE CIRCUIT TOPOLOGY
PASS TRANSISTOR LOGIC PASS TRANSISTOR LOGIC CIRCUITSCIRCUITS
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
Static Flip FlopStatic Flip Flop
0
1
D1
0
Q
ClkClk
Transparent when Clk=0
Transparent when Clk=1
At Clk= 0 → 1, Q = D. Else Q is held.
D Flip Flop – Circuit D Flip Flop – Circuit DiagramDiagram
D Flip Flop - OperationD Flip Flop - Operation
D Flip Flop - WaveformsD Flip Flop - Waveforms
Pass Transistor Logic CircuitsPass Transistor Logic Circuits
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
Handling Clock SkewHandling Clock Skew
Clk-in
Clk
Clk'
Pass Transistor Logic CircuitsPass Transistor Logic Circuits
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
Pass Transistor Logic Pass Transistor Logic FamiliesFamilies
Complementary Pass Transistor Logic Family Dual Pass Transistor Logic Family Swing Restored Pass Transistor Logic Family
ProblemsProblems
Design 4 to 1 multiplexor using transmission-gates. Implement an XOR gate using minimum number of
transistors. Implement a full adder using transmission gates.
Solution - 1Solution - 1
C'0
C0
C1
C'1
Y
A0
A1
A2
A3
Solution - 2Solution - 2
C'0
C0 C'1
A0
A1
A2
A3
C1 Y
XOR GateXOR Gate
A B
A⊕B