Parasitic inductance hindering utilization of power devices · › Modul: FF450R12ME4 › L S =...

Parasitic inductance hindering utilization of power devicesDr. Reinhold Bayerer Infineon Technologies AG, Warstein, Germany

Content

Introduction

Effect on switching characteristics and electrical stress

System losses, adjusting RG for worst case operation

Switching speed (di/dt) as a function of RG

Current sharing of paralleled power devices

Symmetry in 3 phase inverter

Conclusion

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22015-10-30 Copyright © Infineon Technologies AG 2016. All rights reserved.

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Introduction






Conclusion

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V

I

Overvoltage is not the only consequence of parasitic inductance

Turn-off

Load

LS


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Conclusion

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Effect of parasitic inductance during IGBT Turn-on – diode reverse recovery

V

I

Diode

IGBT

IGBT

Diode


at high inductance› Peak of Reverse Recovery current is widened, charge is removed earlier › no tail for soft decline of current

Diode with low Tail-Charge, IF=1/10 IN

65nH 200nH

Example of reverse recovery: 1200A/3,3kV-Module


Diode with high tail charge

› soft Diode recovery leads to higher switching losses

Diode with low tail charge

managing high parasitic inductance by higher tail charge, 1200A/3,3kV-Modul


XHP: Lower parasitic inductance reduces peak power in diode, di/dt at turn-on can increase

› IGBT turn-on under nominal conditions– VCE = 1800 V; IC = Inom– Tj = 25°C

› Eon - 21%, at same diode stress


XHPIHM

V

I

Diode

IGBT

IGBT

Diode

IGBT Turn-off - Diode Turn-on


Turn-off under different parasitic inductance (3,3kV/1200A-Module)

L=95nH L=350nH

› limited change in Eoff, if voltage can develop › Tail gone› oscillation


Example XHP: IGBT Turn-off

› VCE = 2400 V; high current IC = 2 x Inom› Tj = 25°C

› Early pull off of carriers, no tail current and oscillation› Low parasitic inductance less overvoltage and tail for damping of

oscillations


Example: Loss minimized 750V IGBT cannot be used because of high parasitic inductance

› Exceeding voltage rating› Early pull off of carriers, no tail current and oscillation› Low parasitic inductance less overvoltage and tail for damping of

oscillations


Compromise IGBT has excessive tail current for lower peak voltage and softness

› To compromise for high parasitic inductance tail charge has to be added

› It means higher switching losses


Content

Introduction






Conclusion

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Procedure for 450A/1200V IGBT4

› Modul: FF450R12ME4

› LS = 25nH

› Measure Eon, Erec, Eoff, at Inom, VDC=600V, RGnom=1Ohm, TJ = 150°C

› Adjust RG to stay below 1150V at TJ=25°C, VDC=800V, I=5*Inom

› Measure Eon, Erec, Eoff again at Inom, VDC=600V, TJ = 150°C and adjusted RG

› Compare losses


Details for worst case condition

Mess.Nr. T[ｰ ] Rg_on Rg_off Vce Ic Vce Ic Eoff Vce_max1 25 15 15 887 1800 799.664 1800.624 429.235 11442 150 15 15 622.5 450 599.59 449.576 72.194 8243 150 1 1 622.5 450 599.504 450.512 59.498 7764 25 12 12 837.5 900 800.71 899.36 155.76 11525 150 12 12 623.5 450 600.221 450.36 68.002 832

#1


Details: Eoff for RG,nom and increased RG

Mess.Nr. T[ｰ ] Rg_on Rg_off Vce Ic Vce Ic Eoff Vce_max1 25 15 15 887 1800 799.664 1800.624 429.235 11442 150 15 15 622.5 450 599.59 449.576 72.194 8243 150 1 1 622.5 450 599.504 450.512 59.498 7764 25 12 12 837.5 900 800.71 899.36 155.76 11525 150 12 12 623.5 450 600.221 450.36 68.002 832

#3#2


Increasing RG to manage parasitic inductance for worst case, doubles switching losses

› RG_high means increased RG to stay within VDSS at VDC=800V, IC=5xInom, TJ=25°C

› Energies are measured at same conditions but different RGs


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Introduction






Conclusion

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Today’s IGBT increase di/dt when RGincreases until a maximum di/dt is reached

› Turn-off IGBT3: 6.5kV, 25A, RT› Maximum di/dt at RG = 100 Ohm

› To lower di/dt by increase of RG the >350 Ohm are required› dV/dt is slowed down, increasing switching losses


Low LS allows soft switching at low losses

› di/dt, dV/dt, Eoff over RG

› Crossing the maximum in di/dt and reaching lower di/dt than for low RG = 1…30 Ohm increases Eoff by 60%

› Parasitic inductance should be low enough to be able to stay in the left of the maximum in di/dt


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Even low inductance may deteriorate gate voltage, significantly

› Turn-on of an IGBT

› See di/dt in IC, it is typical

› See impact on gate voltage

› Emitter shifts by approx. 6V

› Influence on current share of paralled devices

250A/200ns=1250A/µs

VL2 = induced voltage at stray inductance

VG = gate to ground

VGE = gate to emitter

IC

VC

VC IC

Representing short conductor


Paralleling of devices is the way to achieve the required power level – current to be shared

› current flows perpendicular to row of semiconductors› Equal LC’s, equal LE1’s, equal LE2’s from power terminals to each

semiconductor› The asymmetric Gate to Aux. Emitter circuit may be accepted › LCx and LEx are ineffective because of current sharing

LC LC LC

LE1 LE1 LE1

LE2 LE2 LE2

LCx LCx

LEx LEx


Cross current within paralleled devices causes voltage drop among devices

› current flows along the row of semiconductors› current flows through LCx and LEx causing voltage drop from

semiconductor to semiconductor› Voltage drop at Lex deteriorates gate voltages› Imperfect current sharing

LC

LE1 LE1 LE1

LE2

LCx LCx

LEx LEx


How big is LEx?

› Shield on back plane assumed

› Approx. 1 nH from terminal to terminal on copper track

thickness 1mm:= width 6mm:= Length 6mm:=

L1Length µ0⋅

2 π⋅width

2⋅

thickness−

2

thickness

2

yatan

width

2

thickness2

y−

atan

width

2

thickness2

y+

+

⌠⌡

d⋅:= L1 1.126 109−

× henry⋅=

L µ 0 Length⋅db⋅:=

Lhenry

1.3 10 9−×=


Significant impact during turn-on, when considering track inductance, only

Inductance of track on PCB

IC_1

IC_2

VC

VG_1,2

Vext

› An inductance of ≈1nH between 2 IGBT

– causes a difference in gate voltage by approx. 1 V

– A difference of 1 V in gate voltage results in a difference of current per chip by a factor of approx. 2

2 switches out of the previous chain


Inductance of leads improves balancing of current in asymmetric design

Inductance of leads added

IC_1

IC_2

VG_1,2

› Difference in gate voltage reduced to approx. 0.2 V, resulting in less difference in current


“Parallel plate waveguide design” – backside shield for DC+, symmetric terminals

› Parallel plates for DC+ and DC-› plate for phase

Single switch Half bridge


Parallel plate waveguide design for half bridge; also phase should be symmetric


Rule for orientation of switches, parallel plates and current

› Row of switches along x-axis› Current perpendicular to x-axis› Low L, Low Z, No breaks in L, Z › Line contact at interfaces, required

paralleled switches

substrate

current

x

y

z

X


Module sample; Half bridge 1200V/600A+

› Parallel plates from chip level to terminal, approximated › Press-fit interface to external plates › Low resistance at conductors (wide and short)


With DC-link

› Capacitance C=1,64mH

› Total inductance

– LKK = LDClink + LModul = 4,3nH + 5,3nH = 9,6nH

Pulse cap


turn off 400A, TJ=25°C, 100ns/div

› Low L low voltage overshoot› No lumped parasitics – no localized resonant circuits

New moduleVDC=900V

FF400R12K

T3

vSense: 1V/div

Standard moduleVDC=700V

vCE: 200V/div iL/iC: 200A/div iC*: 200A/div vGE: links 20V/div, rechts: 10V/div *skaliert auf iL

ICE

VCE


Current sharing of paralleled IGBTs and diodes: Example IHM

› how to implement into DC bus?

› 3 subsystems to be paralleled outside the module


Equivalent circuit for IHM containing 3 sub-systems

› Power terminals to be connected outside

› Gate- und auxiliary emitter connected, internally


Symmetric set up of phase leg - 2 IHMBottom ModuleTop ModuleCapacitor Module

Phase Output+-


Current measurement in each emitter› 3 Rogowski coils for individual emitters

› Pearson for total current

› DC capacitor behind module 2nd module of phase behind capacitor


Equivalent circuit for 2 IHMs in a phase leg

› Symmetric design

› no voltage between emitters or collectors same current in each subsystem


results

› Total current: turquoise; voltage: black

› Partial currents: red, green, black

› Minor differences


Asymmetric setup

modules oriented with long side along the bus

Phase Output

+-


Equivalent circuit for asymmetric setup› Voltage drop along the emitter or collector chain during di/dt and › Voltage along the auxiliary emitter› Different voltage at each subsystem


Results with same basic differences › Differences in conduction phase

› Circulating currents through aux. emitter

› Largest differences in turn-on


Conduction mode

› Current per sub-system: 800A, 550A, 450A

x3


Turn-on

› Current per sub-system: 1400A, 580A, 300A

x3


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Half bridge Module

(+)

(Phase)

C

Parallelplates

LS

Load

(+)

(-)

(Phase)C

phase leg with capacitor, minimized inductance

› Effective within single phase

(-)


Inductance from half bridge to half bridge causes current flow from the side

› 3 Phase inverterInductance from half bridge to half bridge

Half bridge Module

(+)

(Phase)

(-)

Half bridge Module

(+)

(Phase)

(-)

Half bridge Module

(+)

(Phase)

(-)


Example: 3 phase inverter with low inductance within half bridge


Hal

f br

idge

M

odul

e

Hal

f br

idge

M

odul

e

Hal

f br

idge

M

odul

e

To prevent current flow form the wrong side and overall low inductance and symmetry

› 3 Phase inverter

› Modules side by side along main current flow of half bridge

› Low inductance from capacitor to all half bridges / phases

› Phase output to be symmetric, as well

Main direction of current(+

)(-

)


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Introduction






Conclusion

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Conclusion

› Parasitic inductance does not only generate overvoltage

› It changes switching characteristics of bipolar power devices

› Excessive tail charge is required to deal with parasitic inductance

› Simple gate drivers: High parasitic inductance hinders the use of RG values which result in low switching losses.

› For paralleled devices even very small parasitic inductance may result in a large imbalance of current

› For paralleled devices parasitic inductance has usually more impact on current sharing than the spread of the devices’ characteristics

› big potential for better utilization of power devices by strict geometry of conductors


Acknowledgment

› Many thanks to

– F. Wolter and Th. Geinzer for data on 750V IGBT – Chr. Urban for data from worst case operation– D. Heer for data from 6.5kV turn-off characterization


Parasitic inductance hindering utilization of power devices · › Modul: FF450R12ME4 › L S =...

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