Parametric Yield Driven Resource Binding in Behavioral ...
Transcript of Parametric Yield Driven Resource Binding in Behavioral ...
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Yibo Chen1, Yuan Xie1, Yu Wang2, Andres Takach3
1The Pennsylvania State University2Tsinghua University
3Mentor Graphics [email protected]
Parametric Yield Driven Resource Binding in Behavioral Synthesis Using Multi-Vth/Vdd Library
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Outline
Introduction and MotivationMulti-Vth/Vdd Library Characterization under PVYield-Driven Resource Binding with Multi-Vth/VddExperiment Results and Conclusion
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Motivation Process variation (PV) has become a prominent concern as technology scalesDevice and interconnect process variations increase with shrinking feature sizes
(Source: Intel)(Source: K. Roy DAC05)
2interVT ,σ
2intraVT ,σ
Intra-die
Inter-die 0.9
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Normalized Leakage (Isb)
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0.18 micron~1000 samples20X
30%
Require a shift in the design paradigm, from today’s deterministic to probabilistic design
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Probabilistic Design Paradigm
GATE
CIRCUIT
VoutVin
MODULE+
DEVICE
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S Dn+
G
Process variation modeling
Statistical timing analysisStatistical gate level optimizationStatistical technology mapping
Variation-aware architecture
Variation-aware behavioral synthesis
A holistic design paradigm shift to statistical design
ARCHITECTURE
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Behavioral SynthesisESL (Electronic System Level) design methodologies
Move design hierarchy to a higher level Close the gap of productivity and design complexity
Behavioral synthesis (a.k.a. high level synthesis) Enables an ESL-to-RTL implementation flow
Gain a lot of emphasis recently (e.g. workshop @ DAC: HLS-back to the future)
Industry success stories:Mentor Graphics: Catapult-CCadence: C-to-silicon Compiler Forte Design: CynthesizerBlueSpecAutoESL
Variation-aware behavioral synthesis is still in its infancy
System level modelC/System C
Behavioral synthesis
Tech. Lib.
DesignConstraints
RTL
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Variations’ Impact on Behavioral Synthesis
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Behavioral synthesis schedules operations at difference clock cycle and maps them to function units (FU)Traditionally, each FU has a fixed latency value
However, under process variation…CDFG
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Parametric yield
The probability that the synthesis hardware meeting a specified constraint
∫=CLKT
dttpdfYield0
)(
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Motivation Example
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CC1
CC2
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+Nominal case analysis: any
Worst case analysis: R1
Variation-aware analysis: R2
∫=T
0dttpYield )(
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Design Space Exploration For Power
Resource lib: various kinds of multipliers (booth, array, etc) adders (tree, carry-lookahead, etc.) multipurpose units (ALUs, multiplier/divider, etc.)
Arch I
Arch II
Arch III
Delay
Power
different architectures
Delay Constraint
different Vth/Vdd9
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Outline
Introduction and MotivationMulti-Vth/Vdd Library CharacterizationYield-Driven Resource Binding with Multi-Vth/VddExperiment ResultsConclusions
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Multi-Vth/Vdd Selection
Multi-Vth/Vdd in conjunctionEffective reduction in both dynamic and static power
Combination of dual-Vth and dual-Vdd4 “Corners” of dual-Vth and dual-Vdd
multi-Vth/Vdd applied at function unit level
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PV-aware Library Characterization
Based on 45nm technologyMulti-Vdd/Vth SettingsVariations on Device Parameters
Gate Length, Metal Line WidthGate Oxide Thickness
Statistical timing characterizationSynopsys PrimeTime VX
Statistical power characterizationHspice Monte Carlo Analysis
System level modelC/System C
Behavioral synthesis
Tech. Lib.
Desig Constraints
RTL
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Timing Characterization Results
2 Adder Designs Delay : Kogge16 Delay : Bkung16
Case Power Mean(μ)
Deviation(σ)
Mean(μ)
Deviation(σ)
Nominal Medium 3.26417 0.07934 3.46797 0.17013
High-Vth Low 3.66011 0.09215 3.89041 0.19547
Low-Vdd Low 4.22523 0.11554 4.49699 0.24630
High-Vth/low-Vdd leads to larger variations
Different design implementations have different variations
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Power Characterization Results
Statistical power characterization of FUsLibrary cells’ leakage power characterized by Hspice Monte Carlo analysisLeakage power distribution of FUs computed by summing library cells’ leakage power distributions
Name of FU Leakage Power
μ (nW) σ (nW)
Bkung 3626.612 85.739
Kogge 5007.009 94.330
Pmult 4982.431 91.697
Booth 15523.711 205.399
Mux21 383.314 24.089
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Outline
Introduction and MotivationMulti-Vth/Vdd Library CharacterizationYield-Driven Resource Binding with Multi-Vth/Vdd LibraryExperiment ResultsConclusions
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PV-Aware Resource Sharing/Binding
This work focuses on Resource Binding/Sharing
Scheduling already taken place
Control/Data-path structure available
Sharing and binding of the type of functional units is up to optimization
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Parametric Yield Analysis for DFGs
Need two atomic functions sum(A,B) and max(A,B):
Sum(A,B) is easy to performIf both A, B are Gaussian, sum(A,B)
is Gaussian:μ = μA + μB
σ = (σA2 + σB
2 - 2ρσAσB )½
where ρ is the correlation coefficient between A and B
Max(A,B) is quite complex to compute
Tightness probability techniques are used to facilitate the computation of the max function
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Voltage-Level Conversion for Yield Level Conversion needed with low-Vdd units driving high-Vdd unitsAsynchronous conversion allows passing slacks and helps improve timing yield
+ Low Vdd Units + High Vdd Units
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Outline
Introduction and MotivationMulti-Vth/Vdd Library CharacterizationYield-Driven Resource Binding with Multi-Vth/VddExperiment Results and Conclusion
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Variation Aware Resource Sharing/BindingGiven
Scheduled CDFGDesign constrains
Clock period / Timing yield constraintTechnology library with variation
Perform sharing/binding:Determine how operations are assigned to and shared between resourcesMinimize power without violating timing yield
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Power yield improvementwith joint multi-Vth/Vdd
average power reduction of 21% with 95% timing yield constraint
95% yield
LC-Asynchronous
Multi-Vth Only
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Conclusion
As technology scales, process variation has increasing impact on performance and power variationsMulti-Vth/Vdd techniques are used for design space explorationWe propose a statistical behavioral synthesis framework for multi-Vdd/Vth designSignificant power reduction can be achieved with the proposed variation-aware framework
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