Parameter-Insensitive Mixed-Signal Hysteresis-Band Current ...skapat/paper/MSHCC.pdf ·...

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Parameter-Insensitive Mixed-Signal Hysteresis-BandCurrent Control for Point-of-Load Converters with

Fixed Frequency and Robust StabilitySantanu Kapat,Senior Member, IEEE

Abstract—The inductor current ripple under hysteresis currentcontrol is sensitive to system as well as controller parameters,which often deviates from the desired band. Thus a phase-locked-loop (PLL) is employed to regulate the switching frequency overthe operating range. Digital platform drastically simplifies thisusing an all-digital PLL (ADPLL) and offers the controller-tuningflexibility for improved performance. However, the use of uniformvoltage-sampling often leads to multi-limit cycle instability. Thispaper proposes a mixed-signal hysteretic current controller(MSHCC) with the digital voltage-loop and the analog current-loop. A digital-to-analog converter is sufficient to generate time-multiplexed current references. This achieves robust stabilityand parameter-insensitive current ripple by sampling the error-voltage at the rising edge of the high-side gate signal. Stabilityanalysis is carried out using discrete-time models. The proposedMSHCC can be configured to either of the peak, average, orvalley current-mode techniques along with the flexibility to adjustthe switching frequency using an ADPLL for real-time energy-optimization. The proposed scheme is implemented using anFPGA device and tested on a buck converter prototype. TheMSHCC scheme can be extended to a multi-phase buck converter.

Index Terms—Hysteresis current control, mixed-signal control,asynchronous sampling, parameter-insensitivity, robust stability.

I. I NTRODUCTION

T he ever increasing growth of digital devices facilitateshigh performance control implementation for point-of-

load converters [1]– [8]. A mixed-signal architecture seemsto be a promising solution, because of implementing the fast-changing inductor current in the analog domain [3]– [5]. Thispaper proposes a mixed-signal hysteretic current controller thataddresses some longstanding issues in hysteresis control.

Hysteresis current control (HCC) offers (a) inherent current-loop stability and (b) current limiting, (c) fast transient re-sponse, and (d) good accuracy [9]– [24]. However, it suffersfrom serious practical problems [10], as discussed below.

A. Parameter sensitivity in an analog HCC technique

Figure 1 shows a buck converter schematic governed by ananalog HCC scheme [9]. The control waveforms are shown

Manuscript received February 27, 2016; revised June 19, 2016; acceptedSeptember 03, 2016. This work was carried out at the Embedded PowerManagement Lab., Indian Institute of Technology (IIT) Kharagpur.

S. Kapat is with the Department of Electrical Engineering, IIT Kharagpur,West Bengal-721302, India (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Fig. 1. Conventional hysteresis current control in a dc-dc buck converter:voandvref indicate the output and reference voltages;iL is the inductor current.

Fig. 2. Control waveforms related to the circuit in Fig. 1 withGc(s) = kp.

in Fig. 2, assuming the output-voltage ripple∆vo being dom-inated by the effective-series-resistance (ESR) of the outputcapacitorC and considering a proportional voltage controller,i.e., Gc(s) = kp in Fig. 1. Considervc andvc −∆iH as thepeak and valley current references in Fig. 2. The current ripple∆iL and the time periodTh can be derived as

∆iL =∆iH

(1 + kprC), Th =

vin∆iHL

(vin − vo) vo (1 + kprC), (1)

wherevin is the input voltage. This shows that∆iL in (1) issmaller than the desired hysteresis band∆iH. Moreover,∆iLandTh vary with the capacitor ESR and the controller gain.The time periodTh would also vary with the output capacitor,if the characteristics impedance can no longer be neglected[6]. Thus it is difficult to design an input filter using an HCCscheme, which eventually leads to EMI problems [10].

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available at http://dx.doi.org/10.1109/TPEL.2016.2608913

Copyright (c) 2016 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].

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B. PLL/DLL-based frequency regulation in analog HCC

Prior research efforts in [9]– [18] have been attempted toregulate the switching frequency in HCC. Generally a phase-lock-loop (PLL) is considered to achieve a desired switchingfrequency by varying the hysteresis band. A direct hysteresisband adaptation technique in [14], [15] considers an analogPLL-based arrangement. This requires a frequency-to-voltageconverter which increases analog component count, therebyincreasing size and power loss along with a slower frequency-loop. A faster recovery can be achieved by using a digital PLL(DLL)-based architecture in [16]. However, beside using atime-to-digital converter (TDC), the use of a voltage-controlledresistor increases component count. A delay-line DLL-basedapproach in [17] enables ultra high-frequency implementation,and a comprehensive survey of PLL/DLL-based techniquescan be found in [18]. The above approaches are primarilylimited to an analog HCC scheme.

C. Existing digital/mixed-signal hysteresis control techniques

Digital/mixed-signal hysteresis control can simplify the fre-quency regulation method by considering an all digital PLL(ADPLL) [19], which also offers an auto-tuning flexibly forthe feedback voltage controller [20]– [27]. A fully digital HCCscheme requires multiple A/D converters [22]. A mixed-signalsolution seems to be a promising alternative [23]. However, auniform output voltage sampling in an HCC scheme may ex-hibit undesirable multiple limit cycle oscillations [24], whichis substantiated with a case study to follow.

1) Multi-limit cycle oscillation using uniform sampling:Consider a set of power circuit parameters for the buckconverter (in Fig. 1) as:L = 10 µH, C = 470 µF, R = 1Ω,vin = 8.5 V, rC = 20mΩ, ∆iH = 2 A, and vref = 3.3 V.Consider a proportional-integral (PI) voltage controller withthe proportional gainkp = 50 and (continuous-time) inte-gral gain KI = 10000. For a voltage-loop sampling ratefvs = 500 kHz, Fig. 3 clearly shows instability using a clokedHCC scheme, whereas the analog HCC scheme remains stable.Fig. 4 shows that the output voltage is sampled using a uniformrate; however, switching events occur non-uniformly as per thehysteresis logic. The timing mismatch between sampling andswitching points results in multi-limit cycle phenomena [24].This increases ripple parameters, as evident from Fig. 3, andmay lead to EMI problems. A higher sampling rate can reducethe timing mismatch, which requires a fast analog-to-digitalconverter (ADC) with increased cost and power loss.

2) Asynchronous sampling approaches:Asynchronous con-trol methods are useful to minimize limit cycle oscillations[25]– [29]. The synchronous/asynchronous voltage-mode con-trol in [25], [26] considers a digital-to-analog converter (DAC)to compare the reference signal with the output voltage. Thiswas extended to mixed-signal current-mode control [27]. Thisuses an extra DAC for the current-loop; thus the number ofDACs and analog comparators increases. Also finite quanti-zation levels using a lower-bit DAC can considerably affectsteady-state frequency regulation and cycle-by-cycle stability.

A flash ADC was used in [28], [29] to sample the outputvoltagevo once per cycle. This synchronizes the closed-loop

8 8.01 8.02 8.03 8.04 8.05

3

4

Indu

ctor

Cur

rent

(A

)

8 8.01 8.02 8.03 8.04 8.053.28

3.3

3.32

Time (ms)

Out

put

Vol

tage

(V

)

Clocked HCCAnalog HCC

Fig. 3. Simulation results of a buck converter using analog HCC (dash-dotted red trace) and clocked-HCC (solid blue trace) considering uniformoutput-voltage sampling with a sampling ratefvs = 500 kHz.

8 8.01 8.02 8.03 8.04 8.053.28

3.3

Out

put

Vol

tage

(V

)

8 8.01 8.02 8.03 8.04 8.05

2

4

Time (ms)

Con

trol

Wav

efor

ms

(A)

AnalogSampled

(a)(b)(c)

Fig. 4. Simulation results of a buck converter using a clocked-HCC schemeconsidering uniform output-voltage sampling with a sampling ratefvs =500 kHz: (a) and (b) indicate the peak and valley current references using adiscrete-time voltage controllerGc(z); (c) indicates the inductor current.

operation whenvo crosses a quantization level; however, noisein vo may considerably affect the sampling process. Also theflash ADC increases size, power, and cost.

This paper proposes a mixed-signal hysteresis current con-trol (MSHCC) scheme which can (i) be used with any ADC,(ii) reduce hardware and sampling resources, (iii) simplifycontrol mechanism, (iv) achieve parameter-insensitive currentripple ∆iL, (v) fast response, and (vi) robust stability.

This paper is organized as follows. Section II introducesthe proposed MSHCC scheme. Stability analysis is carriedout in Section III. Section IV discusses the design of theproposed scheme. Section V extends the proposed scheme toa multi-phase buck converter. Section VI presents hardwareimplementation using a synchronous buck converter. Sec. VIIconcludes the paper.

II. T HE PROPOSEDM IXED-SIGNAL HCC TECHNIQUE

Figure 5 shows the schematic of the proposed MSHCCscheme which primarily consists of three blocks: ‘timing cir-cuit’, ‘real-time band adaptation’, and ‘dead-time circuit’. Theformer generates digital codevT related to the instantaneoustime periodTh using a counter and a system clockFclk. Thisalso generates the sampling clockFvs to sample the error volt-ageve, of which detailed mechanisms will be discussed later.The digital voltage controllerGc(z) computes in synchronismwith Fvs; the outputsvc[n] and (vc[n]−∆iH) represent the



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Fig. 5. The proposed mixed-signal hysteretic current controller in a dc-dcbuck converter:ve is the error output voltage;uH anduL are the gate signalsfor the high-side and low-side MOSFETs;Fclk is the digital controller clock;∆iH is the current hysteresis band which can be adaptively varied in real-time.

Fig. 6. Internal architecture of the dead-time circuit as mentioned in Fig. 5.

peak and valley current references. Only one comparator isused in this proposed scheme as shown in Fig. 5. Thusone DAC is sufficient to generate time-multiplexed currentreferences using the high-side gate signal as the select line.The DAC outputvA is directly compared with the inductorcurrent in the analog domain.

A. Dead-time circuit configuration

Measurement noise and switching spikes may lead to chat-tering in the comparator outputuc. A dead-time circuit is usedas shown in Fig. 6, which uses an ‘edge-triggered mono-shotcircuit’ and a ‘dead-time generator’. The former identifies anactive (either rising or falling) edge and triggers the mono-shotoperation for ‘m’ consecutive clock periods using the systemclock with the frequencyfclk. This stores the status of thecomparator output at the beginning of the mono-shot operationand disables any further changes in the outputum throughoutthe durationm/fclk. Since the MUX output changes with thestatus ofuH (in Fig. 5), a smaller value ofm would be enoughto avoid initial chattering. The ‘dead-time generator’ blockattempts to avoid any shoot-through current, in which theadjustable delays should be optimized using timing parametersof the MOSFETs and the associated drivers.

B. Real-time band adaptation using an ADPLL

Figure 7(a) demonstrates control waveforms using the peak-current mode configuration, whereve[n] is sampled at everyrising edge ofuH and the current referencevc[n] remainsconstant throughout the periodic intervalTh. Thus the inductorcurrent ripple∆iL resembles the hysteresis current band∆iH.For a given time periodTh1, ∆iL1 at steady-state becomes

∆iL1 =

[

vo (vin − vo)

Lvin

]

× Th1. (2)

Referring to Fig. 5,vT is the digital code forTh and generatedusing a TDC. The desired switching periodTd can be achieved

Fig. 7. Control waveforms of a buck converter under the proposed scheme:Dotted traces are the projected output using a continuous-time PI controller.

simply by setting the desired band

∆iD =vTd

vT1

×∆iH1, (3)

where vT1 and vTd are the TDC outputs for the respectivetime periodsTh1 andTd (related to the desired time period).Thus a fixed-frequency steady-state operation can achievedby adjusting∆iH in real-time using (3). However, it wouldbe difficult to implement a division operation using fixed-point implementation. While an iterative Newton-Raphsonmethod can be used, this would require considerable hardwareresources. A more straight forward method is to piecewiselinearize the functional formf(vT1) = (vTd/vT1) in (3),thereafter, multiplying by∆iH. Using a 10-bit TDC,tclk =10ns for Fclk, and vTd = 500 for the nominal switchingfrequency of 200 kHz,vT1 is found to bevT1 ∈ [350, 650]for the input voltage rangevin ∈ [5 V, 9 V ]. Thusf(vT1) canbe approximated as

f(vT1) ≈

2.430− 0.00286× vT1 for vT1 ∈ [350, 499]1.744− 0.00154× vT1 for vT1 ∈ [500, 650],

(4)where vT1 ∈ I+. The above expression can be easilyimplemented using fixed point arithmetic. This requires ageneralized adder/subtractor and a multiplier with two (fixed)discrete gains; thus multiplier-less multiplication algorithmscan be used [30] to optimize hardware resources. The resultin (4) is finally multiplied with∆iH to compute the desiredcurrent hysteresis band in order to achieved a fixed frequencyoperation. This approach is adopted in this paper.

Alternatively, the TDC in this proposed MSHCC schemeenables one to implement an ADPLL algorithm [19], which



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Fig. 8. Generation of time-multiplexed synchronous/asynchronous samplingclockFvs: Din andDout are the input and output data of the register;kp andki are the proportional and integral gains of the discrete-time proportional-integral (PI) controllerGc(z) in Fig. 5.

would be helpful for programming the switching frequency forreal-time energy optimization over a wide operating range.

C. Time-multiplexed synchronous/asynchronous sampling

Fig. 9. A load step-transient scenario under the proposed MSHCC schemewhich uses a time-multiplexed synchronous/asynchronous sampling clock.

In this MSHCC scheme, the asynchronous sampling clockFH,g is generated fromuH (high-side gate signal) using anedge-detection circuit as shown in Fig. 8, and related timingdiagrams are shown in Fig. 9. The use ofFH,g may leadto a complete collapse of the converter during a large-signalrecovery. This is becauseuH does not change its state for along time, whenFH,g is unable to sample the output voltage.

An additional uniform sampling clockFs of time periodTs is interfaced withFH,g. The former is generated usinga counter and the system clockFclk as shown in Fig. 8,which can also be programmed. BothFs andFH,g are time-multiplexed to generate the sampling clockFvs using the selectline Fsel which is an active low signal.Fsel is generatedby comparingvT with the digital codevth related toTth

(threshold time interval), andFsel = 1 whenvT ≥ vth. ThusFs is enabled when the inter-sampling duration exceeds thethreshold timeTth as shown in Fig. 9.

D. Synchronous/asynchronous controller computation

Figure 8 demonstrates computation of the discrete-timePI controller in synchronism with the time-multiplexed syn-chronous/asynchronous sampling clockFvs. This uses thesynchronous clockFs during large-signal transients, and theevent-driven clockFH,g for computing once per switchingcycle during small-signal and steady-state conditions. Thiswould be effective in saving real-time hardware resources, yetclosely retaining the performance over a uniformly sampleddiscrete-time PI controller using the clockFs throughout [31].

E. Flexibility and real-time configurability

The proposed scheme in Fig. 5 shows a peak current modecontrolled MSHCC scheme, in which the peak current iscontrolled by the outer voltage loop, while the valley inductorcurrent is controlled using the hysteresis band∆iH.

This can be configured in real-time to a valley current modecontrol scheme by using the control voltagevc[n] as the valleycurrent reference, while∆iH will be added with vc[n] togenerate the peak reference current. At steady-state,ve[n] willbe sampled at every falling edge ofuH.

The proposed scheme can be extended to an average cur-rent mode control scheme by simply changing the peak andvalley current references (in Fig. 5) as(vc[n] + ∆iH/2) and(vc[n]−∆iH/2). All other sampling and control mechanismswill remain the same as the peak-current mode control scheme.

III. A F RAMEWORK OF DISCRETE-TIME MODELING AND

STABILITY ANALYSIS

A buck converter in Fig. 1 operating under continuousconduction mode (CCM) can take two feasible switch states,namely the MODE 1 when the high-side switch isON and theMODE 2, otherwise. State-space models can be written as

•

x = A0x + (A1x +Bvin)u+A1x (1− u) , vo = Cox, (5)

wherex = [iL, vcap]T with iL is the inductor current;vcap is

the voltage across the capacitor;vo is the output voltage, and

A0 =

[

0 00 −Rn/RC

]

; B =

[

1/L0

]

;

A1 =

[

− (rL +RnrC) /L −Rn/LRn/C −Rn/RC

]

;

Co =[

RnrC Rn

]

; Rn = R/ (R+ rC) ,

(6)

where the control inputu = 1 for MODE 1 andu = 0 forMODE 2. Thus the output voltage can be expressed as

vo (t) =RrC

(R+ rC)× iL (t) +

R

(R+ rC)× vcap (t) . (7)

Assuming linear inductor current dynamics and quadraticcapacitor voltage dynamics,iL andvcap can be written as

iL (t) = iint +mkt,

vcap (t) = vc,int +(iint − io)

Ct+

mkt2

2C,

(8)

where iint and vc,int are the initial values ofiL and vcap,respectively;io indicates the load current. The slope of the



5

inductor current,mk can be written as

mk =

m1 = (vin − vo) /L during Mode 1−m2 = −vo/L during Mode 2.

(9)

Using (8) and (9) into (7), the output voltage can be derived.

A. Discrete-time Modeling

Discrete-time models under fixed-frequency PWM are de-rived with respect to the switching clock; however, sucha clock is not available in this proposed MSHCC scheme.Instead, a rising/falling edge ofuH is used to derive discrete-time models under different current-mode configurations.

1) Peak current-mode configuration:The control wave-forms in Fig. 7(a) shows that a rising edge ofuH is used asthe sampling point using the peak current-mode configuration.Thus the complete discrete-time model can be derived for thesequence consisting of the MODE 1 followed by the MODE 2.Let the inductor current and the output voltage at the start ofthenth switching cycle bein andvn, and those at the end ofthe clock period bein+1 andvn+1, respectively.

Referring to Fig. 7(a), letiL and vo at the end of theMODE 1 be i1 andv1, which are derived using (7)–(9) as

i1 = in +m1th,

v1 = vn +R

R+ rC

[(

rCm1 +in − io

C

)

th +m1t

2h

2C

]

,

(10)the initial output voltagevn is obtained using (7) and (8) as

vn = [RrCin +Rvc,n] / (R+ rC) . (11)

Considering the final conditions of the MODE 1 as the initialconditions of the MODE 2, the final conditionsin+1 andvn+1

of the nth switching cycle can be derived using (7)–(9) as

in+1 = vc[n]−∆iH,

vn+1 = v1 −R∆iHR+ rC

[

rC −(in +m1th − io)

m2C+

∆iH2m2C

]

,

(12)wherevc[n] is the voltage-controller output as shown in Fig. 5.Assuming the output currentio to be constant, the termin−ioin (10) and (12) can be written asin − io = −m1th/2. Thisindicates that any perturbation inin is immediately reflectedin the instantaneous on-timetn. Thus the expression ofvn+1

in (12) can be further simplified using (10) as

vn+1 = vn + α1m1th − α1∆iH, (13)

where α1 =R

(R + rC)×

(

rC +∆iH2m2C

)

. (14)

2) Valley current-mode configuration:Figure 7(b) showsthe control waveforms under the valley current-mode MSHCCscheme, in which the switching cycle begins with the MODE 2,when the high-side switch is turned off. Thus a falling edgeof uH is used to sample the error voltage. Consider thenth

switching cycle with the time periodTh and the off-timeth.Let the inductor current and the output voltage at the start ofthenth switching cycle bein andvn, and those at the end ofthe clock period bein+1 and vn+1, respectively. LetiL andvo at the end of the MODE 2 bei2 andv2, which are derived

using (7)–(9) as

i2 = in −m2th,

v2 = vn +R

R+ rC

[(

in − ioC

− rCm2

)

th −m2t

2h

2C

]

.

(15)Considering the final conditions of the MODE 2 as the initialconditions of the MODE 1, the final conditionsin+1 andvn+1

of the nth switching cycle can be derived using (7)–(9) as

in+1 = vc[n] + ∆iH,

vn+1 = v2 +R∆iHR+ rC

[

rC +(in +m2th − io)

m1C+

∆iH2m1C

]

.

(16)Assuming the output currentio to be constant, the termin−ioin (15) and (16) can be written asin − io = m2th/2. Thisindicates that any perturbation inin is immediately reflectedin the instantaneous on-timetn. Thus the expression ofvn+1

in (16) can be further simplified using (15) as

vn+1 = vn − α2m2th + α2∆iH, (17)

where α2 =R

(R+ rC)×

(

rC +∆iH2m1C

)

. (18)

B. Stability Analysis using the Proposed MHSCC Scheme

Referring to Fig. 8, the output of the discrete-time PIcontrollerGc(z) in Fig. 5 can be written as

vc[n] = kpve[n] + uI[n], where (19)

uI[n] = uI[n − 1] + kive[n], ve[n] = (vref − vn). Thediscrete-time PI controller in (19) uses the time-multiplexedsynchronous/asynchronous clockFvs, and its implementationis shown in Fig. 8 with the discussion in Section II-D.

1) Stability analysis under peak current-mode MSHCC:Figure 7(a) shows the control waveforms under the peakcurrent-mode MSHCC scheme. This considers the rising edgeof the high-side gate signal,uH, for error voltage samplingand controller computation. It can be found from (12) thatthe current-loop exhibits unconditioned zero-input stability;thus the closed-loop stability is completely determined by thevoltage-controller. Referring to Fig. 7(a), the on-timeth duringthenth cycle can be derived as

th =vc [n]− in

m1

=vc [n]− vc [n− 1] + ∆iH

m1

. (20)

Using (13) and (20), the closed-loop discrete-time voltageequation can be derived; thereafter, the perturbed discrete-timemodel can be derived using (19) as

vn+1 = [1− (kp + ki)α1] vn + α1kpvn−1. (21)

It has been reported in [32] thatZ-transformation can beapplied on perturbed discrete-time maps of a DC-DC converterunder a variable frequency operation. ApplyingZ-transformon (21), the closed-loop characteristics equation can be ob-tained, and the eigenvalues become

λ1,2 =1

2

[

1− (kp + ki)α1 ±

√

[1− (kp + ki)α1]2+ 4kpα1

]

.

(22)



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Fig. 10. Stability status using the proposed MSHCC scheme using aproportional voltage controller: Solid and dashed blue traces indicate steady-state and perturbed inductor currents,iL,ss and iL,p, respectively. Blackdotted tracevem,p(t) indicates the emulated continuous-time controller outputfor the perturbed case and thevc[n] is the output of the discrete-time controllerGc(z). The error currentier = iL,ss − iL,p, and its sampled values arecaptured at the beginning of every steady-state switching cycle.

Under the assumption(kp + ki) ≫ ki, the discrete-timeeigenvalues in (22) can be approximated as

λ1 ≈ 1; λ2 ≈ − (kp + ki)α1. (23)

Using (9) and (23), the stability condition becomes

(kp + ki) < kcrit =(

1 +rCR

)

×

[

rC +L∆iH2vrefC

]

−1

. (24)

For rC = 0, (24) becomeskcrit = 2C/ [(1−D)Th]. Thisimplies that the controller gain range can be enlarged either bydecreasing the switching periodTh or by increasing the outputcapacitorC and the duty ratioD. Thus improved stability canbe obtained while operating at a higher switching frequency.

2) Impacts of the capacitor ESR on stability:Consideringthe characteristics impedance,Zc =

√

L/C, to be smallcompared to the capacitor ESR, the stability condition in (24)becomeskcrit ≈ 1/rC for rC << R. This indicates that alarger ESR would eventually reduce the stable range ofkcrit.This can be intuitively perceived from Fig. 10. This shows that,for a smaller ESR and/or the proportional gainkp, iL,p reachessteady-state within a couple of switching cycles, however, witha time offset [in Fig. 10 (a)]. For a larger ESR and/or a higherkp, iL,p does not reach steady-state within a few cycles [inFig. 10 (b)]. This may not even settle for a further increase inrC and/orkp, eventually leading to instability.

3) Stability analysis under valley current-mode MSHCC:Figure 7(b) shows the control waveforms under the valleycurrent-mode MSHCC, and the off-timeth during thenth

cycle can be derived as

tn =vc [n]− in

m2

=vc [n]− vc [n− 1]−∆iH

m2

. (25)

Substituting the above equation into (17) and incorporatingsmall perturbations, the perturbed closed-loop discrete-timevoltage dynamics can be shown to be the same as that in(21), exceptingα1 to be replaced byα2 in (18). The samestability condition in (24) can be used for the valley current-mode MSHCC scheme by replacingvref with vin − vref .

4) Stability analysis under average current-mode MSHCC:As discussed in Section II-E, the average current-modeMSHCC can be realized by simply changing the peak andvalley current references (in Fig. 5) as(vc[n] + ∆iH/2) and(vc[n]−∆iH/2). All other sampling and control mechanismswill remain the same as the peak current-mode MSHCCscheme in Section III-B1, and the on-time duringnth cyclecan be derived as

th =vc [n] + (∆iH/2)− in

m1

=vc [n]− vc [n− 1] + ∆iH

m1

.

(26)From (20) and (26), it is clear that the on-time using theaverage current-mode MSHCC scheme is exactly the same asthat using its peak current-mode version. Thus the closed-loopstability boundary would be the same as that in (24).

C. Effects due to the comparator delay

In the proposed mixed-signal CMC, an analog comparatoris used to compared the reference current with the inductorcurrent. Thus a finite comparator delayτd is expected to exist.This would increase the effective on-timeteff,n (during thenth

cycle) of a constant off-time modulator as

teff,n = tn + τd. (27)

If τd is assumed to be fixed, the perturbed discrete-time voltagedynamics in (21) will remain unaffected; thus the stabilityboundary in (24) will be retained under the proposed CMC.

IV. D ESIGN OF THEPROPOSEDMSHCC SCHEME

A. Static quantization requirements

Similar to a traditional mixed-signal current-mode controlarchitecture [4], the proposed architecture uses an ADC forthe digital voltage controller and a DAC for the analogcurrent controller. Thus these two quantizers can make theproposed scheme prone to limit-cycle oscillations. From [4],the minimum DAC quantization requirement becomes

M >

[

log2

(

vr∆vadcKs

×2LFh

√

1− 4D (1−D)

)]

, (28)

whereM is the number of bits of the DAC, andvr is the DACreference voltage;∆vadc is the ADC voltage resolution [2];Ks is the current sensor gain;Fh is the desired steady-stateswitching frequency using the proposed MSHCC technique.

B. High resolution frequency regulation using MSHCC:

Using the proposed MSHCC technique, an infinite duty ratioresolution can be achieved for the analog current controller;however, the resolution of the hysteresis current bandiH is



7

limited by the DAC voltage resolution. This eventually resultsin a finite frequency resolution∆fh as follows

∆fh =1

Nhtclk−

1

(Nh + 1) tclk≈

1

N2h tclk

≈ fh ×1

Nh

, (29)

where fh indicates the nominal switching frequency for anominal time periodTh = Nh×tclk, andtclk indicates the timeperiod of the system clockFclk. Thus the frequency resolutioncan be improved by increasingNh, which requires a higherfrequency system clockFclk.

C. Controller Design using Small-signal Modeling

An HCC technique is a typical example of non-liner controlwith a variable switching frequency; thus it is not straightforward to apply the state-space averaging technique. Thecircuit averaging technique using a PWM switch model wasapplied to an HCC scheme [33], and accuracy of the derivedsmall-signal models was demonstrated using test results. Inthis proposed MSHCC, the current-loop is implemented in theanalog domain; thus the expression of the control-to-outputtransfer functionGvc(s) in [33] can be applied, which is

Gvc(s) =R (1 + srCC)

(1 + sTh/2) (1 + sRC). (30)

Using the method of emulation, a discrete-time PI controllerin (19) can be designed using the closed-loop block diagramas shown in Fig. 11. An equivalent analog PI controller,Gc(s) is considered using the discrete-time integral gainki and the sampling intervalTh which is the time periodunder the MSHCC scheme. An additional zero-order-hold(ZOH) circuit is considered for phase compensation due tothe sampling delay, and a simplified rational transfer functionGh(s) is considered using a first-order Pade approximationas shown in Fig. 11. This ZOH equivalent for the digitalvoltage controller is applicable for a variable frequency oper-ation if the perturbation is sufficiently small near the desiredswitching frequency [34]. Using the power circuit parametersin Sec. I-C1, the simulated loop-gain plot is shown in Fig. 12.This demonstrates that the closed-loop bandwidth of nearly30 kHz for a nominal switching frequency of 200 kHz, thephase margin of 100 degree, and the closed-loop DC gain of60 dB can be achieved forkp = 50 andki = 0.9 in (19).

The bandwidth can be further improved by increasing theproportional gainkp; however, it is limited by the stabilityboundary in (24), which stimulates to investigate design meth-ods to enhance the stability boundary.

Fig. 11. Closed-loop block diagram of a synchronous buck converter usingthe proposed MSHCC technique: A small-signal perspective.

−50

0

50

Mag

nitu

de (

dB)

101

102

103

104

105

106

107

−180

−135

−90

−45

Pha

se (

deg)

Frequency (Hz)

Fig. 12. Simulated loop-gain plot using Fig. 11 with the parameter set inSec. I-C1 forkp = 50 andki = 0.9 at 5 A load current and 8.5 V input.

D. Enhanced stability boundary using ramp compensation:

After the power-stage design, it is difficult to further reducethe capacitor ESR; thus an alternative method needs to beidentified to extend the range ofkp in (24) for a stableoperation. A compensating ramp can be easily generated usinga counter, which needs to subtracted fromvc[n] in the digitaldomain. The control waveforms in Fig. 7(a) are still applicable;however, the effective rising and falling slopes of the inductorcurrent should be modified to ‘m1 + mc’ and ‘m2 − mc’,respectively. Thus the on-timeth,r under ramp compensationduring thenth cycle can be derived using (20) as

th,r =∆vc[n] + ∆iH(m1 +mc)

, where ∆vc[n] = vc[n]− vc[n− 1].

(31)Also the time period during thenth cycle becomes

Th,r =∆vc[n]

(m1 +mc)+

[

(m1 +m2)∆iHm1m2 −mc (m1 +m2 −mc)

]

.

(32)The final currentin+1 at the end of thenth cycle becomes

in+1 = vc[n]− (m2 −mc) (Th,r − th,r) = vc[n]−∆iH. (33)

Similarly, the final output voltagevn+1 can be derived using(13) with the replacement ofth by th,r. This shows thatthe current-loop retains inherent zero-input stability, and theclosed-loop stability can be carried out following the similarmethodology in Sec. (III-B1). Thereafter, using (9), the stablegain range can be found to be

(kp + ki) <

(

1 +mc

m1

)

×

[

R+ rCRrC

]

×

[

1 +L∆iH

2rCvrefC

]

−1

.

(34)Thus the controller gain range in (24) can be enhanced bya factor of (1 +mc/m1) by adding a compensating ramp;however, a larger value ofmc may degrade the bandwidth.Thus it should be carefully selected for a good trade-offbetween the performance and the stability boundary.

V. EXTENSION TO A MULTI-PHASE BUCK CONVERTER

The proposed MSHCC scheme can be extended to a multi-phase buck converter as shown in Fig. 13. Similar to asynchronous buck converter, the main phase is controlled using



8

Fig. 13. The proposed MSHCC scheme in a multi-phase buck converter withone main phase andnp−1 auxiliary phases:vA (DAC output in Fig. 5) is theanalog current reference for all the phases;vT is the digital code related to theinstantaneous time periodTh of the main phase using the proposed MSHCCscheme using the sampling clockFvs which is obtained from Fig. 8.

Fig. 14. Phase-shift circuit and analog current controllers for auxiliary phases.

Fig. 15. Steady-state timing diagrams of a multi-phase buck converter usingthe proposed scheme:Fvs is used as the reference (or master) clock.

the proposed scheme, irrespective of auxiliary phases; thus allthe circuit configurations in Section II are applicable.

A. Current-mode control of auxiliary phases

The sampling clockFvs in Fig. 8 is used as the master clockto generate phase-shifted reference clocks using the ‘phaseshift circuit’ as shown in Fig. 14. Multiple time delay units areused with the delay∆np = Th/np, the phase-shifted clocksare time-multiplexed withFvs using the select lineFflag togenerate switching clocks for auxiliary phases’ controllers.Thereafter, the current referencevA is used to implementanalog current controllers for individual auxiliary phases, andthe related timing diagrams are shown in Fig. 15.

B. Feasibility of realizing various current-mode configurations

As discussed in Section II-E, the proposed MSHCC schemecan be configured to either peak, valley, or average current-mode configurations. Thus similar configurations are alsoapplicable for the auxiliary phases because of sharing the com-mon current referencevA. Interestingly, the average current-mode architecture can be implemented, without the need forsensing averaging inductor current, simply by setting the peakand valley current references for the main-phase MSHCCcontroller as(vc[n] + ∆iH/2) and (vc[n]−∆iH/2), respec-tively. And the analog current referencevA accordingly adjuststhe average current of all the phases. If needed, the currentreference can be easily customized using the digital platform.

C. Time multiplexed operation of auxiliary phases

The MUX select-lineFflag in Fig. 14 can be configured touse either phase-shifted clocks or the master clockFvs for in-dividual phases. By settingFflag asFsel in Fig. 8, the transientresponse during a large-signal recovery can be accelerated byturning on all the phases simultaneously, thereby achieving thefastest slew rate. This would momentarily disable the phase-shift operation as long asFflag = Fsel = 1. However, thiswould result in undesirable oscillations when the phase-shiftcircuit would be enabled again after the transient recovery,which is because of mismatches in initial currents of auxiliaryphases [35]. Nevertheless, the proposed scheme provides theflexibility either to use phase-shifted clocks throughout or touse the master clockFvs during a large-signal recovery.

D. Open/closed-loop hybrid steady-state operation

In a practical multi-phase buck converter, a certain degreeof mismatches can be expected in individual inductors andcurrent sense resistances [36], [37]. The proposed MSHCCscheme allows one to implement the (steady-state) digitalduty-ratio adjustment technique in [36] for auxiliary phases.In this case, apart from the time period, the digitally coded(steady-state) on-time, related to the main-phase, can be ob-tained from TDC of the MSHCC controller. This can be usedwith the phase-shifted switching clocks in Fig. 8 to generatethe compensated open-loop gate signals for auxiliary phases,when the analog current controllers need to be disabled. Dur-ing a large-signal recovery, the current controllers should be



9

restored for fast transient response. The asymmetric clockingin [37] is also possible using the proposed scheme by suitablydelaying phase clocks for steady-state ripple minimization.

E. Phase shedding

A phase shedding method can be adopted using the pro-posed scheme by disabling some of the auxiliary phases andbypassing respective time delays in Fig. 8. Then the optimalphase algorithm in [38] can be realized to improve lightload efficiency. In this case, the time delay∆np should beaccordingly adjusted based on the number of active phases,and an adaptive windowing technique in [39] can be used todesign the optimal switching frequency under light load.

VI. H ARDWARE IMPLEMENTATION

A buck converter prototype has been made, and the pro-posed techniques are implemented using an FPGA device.The nominal power circuit parameters in Sec. I-C1 are con-sidered here. The time period of the FPGA controller clocktclk = 10 ns. A 10-bit differential pipeline A/D converter(AD9215) is used to sample the output voltage, which uses adifferential amplifier (AD8138) for reduction in common modenoise. The digital controller outputvc[n] is converted into ananalog voltagevA using a 12-bit D/A converter (AD9762)followed by a differential receiver amplifier (AD8130). TheoutputvA is compared with the sensed inductor current usinga high speed analog comparator (TLV3501). A shunt of 10 mΩis used to sense the inductor current followed by a high-sidecurrent sense amplifier (ADM4073) with a gain of 20. Thenominal switching frequency is taken to be 200 kHz.

A. Steady-state behavior and spectral characteristics

Fig. 16. Multi-limit cycle instability in a clocked HCC (in Sec. I-C1) withFvs = 10 MHz and∆iH = 2 A at 8 V input: Time scale is 40µs/div.

1) Multi-limit cycle instability: Figure 16 shows the testresult of a buck converter using the clocked HCC scheme asdiscussed in Sec. I-C1 at 3.2 A load current. Even using ahigh sampling rateFvs = 10 MHz for the A/D converterassociated with the error voltage, this exhibits multi-limit cyclephenomena [24], and the FFT trace reveals an unpredictablepower spectrum. Moreover, the inductor current ripple is muchsmaller that the current hysteresis band with∆iH = 2 A.

Fig. 17. Stable periodic behavior using the proposed MSHCC withkp = 20,ki = 0.1, and∆iH = 1.2 A at 8 V input: Time scale is 10µs/div.

2) Stable operation using the proposed MSHCC:Figure 17shows that the proposed MSHCC technique achieves a stableperiodic operation. Because of using a fast comparator witha negligible time delay of nearly 4.5 ns,∆iL is more orless the same as that of∆iH with 1.2 A magnitude. Thefundamental component of the FFT trace shows that thesteady-state frequency varies a little bit around its nominalvalue of 200 kHz. This is primarily because of noise in thecurrent sensor and the D/A converter output. However, thesteady-state frequency variation was found to be within±1%.

B. Load step-transient response:

Figures 18 and 19 demonstrate load transient performanceof a synchronous buck converter using the proposed MSHCCscheme. Following design guidelines in Sec. IV-C and thestability requirement using (24), the controller gains are com-puted askp = 50 andki = 0.9. At 8.5 V input, Fig. 18 showsthat the proposed MSHCC results in8 µs settling time (nearly2 switching cycles) and 50 mV voltage undershoot/overshootfor both the step-up and step-down transients. At 4.5 V input,Fig. 19 shows that the proposed MSHCC results in15 µssettling time (3 switching cycles) and 120 mV voltage under-shoot/overshoot for both the step-up and step-down transients.

A further increase inkp would require a ramp compensationfor a stable operation. It is interesting to notice that the closed-loop buck converter under the MSHCC technique remains sta-ble for the both the load current and input voltage conditions.These are consistent with the analytical stability condition in(24) which is more or less insensitive to the input voltage andload current. Thus the improved performance can be retainedover a wide operating range.

C. Reference step-transient response:

Using a higher proportional gainkp = 100 and ki = 0.9,Fig. 20 shows the transient performance of a synchronous buckconverter using the proposed MSHCC technique. This showsnear time optimal recovery for both the step-up and step-downtransients. Moreover, the closed-loop converter remains stablefor both the operating conditions. When the output voltage



10

Fig. 18. Transient response of a synchronous buck converter using theproposed MSHCC technique for a step change in load current from 4.5 Ato 7.2 A, and back at 8.5 V input.

Fig. 19. The same test conditions as in Fig. 18 withvin = 4.5 V.

reaches close to the reference command, a real-time band-adaptation algorithm in (3) is activated. This uses the fixed-point implementation in (4), and closely regulates the steady-state switching frequency for both the cases.

D. Feasibility of EMI reduction using the MSHCC scheme

The proposed MSHCC scheme allows the designer to cus-tomize the current hysteresis bandiH. Recently, the proposedscheme has been extended to accommodate a periodic bi-frequency modulation technique in [40]. It was shown that theharmonic contents could be considerably attenuated by period-ically modulatingiH, while retaining the transient performanceof the closed-loop converter. Further, using simplified ESR-dominated models, it was found that the same ESR-dependentstability boundary using the unmodulated MSHCC schemewould be applicable for the modulated MSHCC scheme.Thus it provides opportunities for further EMI reductionwith the predictable ripple parameters. Also existing periodicand randomized modulation schemes in [41] can be easilyimplemented by modulating digitally codediH.

Fig. 20. Transient response of a synchronous buck converter using theproposed MSHCC technique for a step change in reference voltage from 3 Vto 4 V, and back at 8.5 V input.

VII. C ONCLUSIONS

In this paper, a mixed-signal hysteretic current controller(MSHCC) was proposed. This considers a digital voltagecontroller and a D/A converter to generate (multiplexed) cur-rent references which are compared with the inductor currentin analog domain. Robust stability and parameter-insensitivecurrent ripple were achieved by using an asynchronous error-voltage sampling along with a fixed switching frequency usingusing the real-time band adaptation. The MSHCC achieves afast recovery through tuning the digital voltage controller withinherent current limiting. The proposed scheme can be easilyextended to a multi-phase synchronous buck converter.

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Santanu Kapat (M’10-SM’16) received his M. Techand Ph.D. degrees in electrical engineering from theIIT Kharagpur, in 2006 and 2010, respectively.

From 2009 to 2010, he was a visiting scholarin the Department of Electrical and Computer En-gineering, University of Illinois at Urbana- Cham-paign. From 2010 to 2011, he was a research engi-neer at GE Global Research, Bangalore, India. Since2011, he has been with the Department of ElectricalEngineering, IIT Kharagpur, where he is an AssistantProfessor. His research interests include analysis and

design of digital and nonlinear control in switching power converters, andapplications to DVS, RFPA, LED drivers, and DC nano-grid.

Dr. Kapat is the recipient of the INSA Young Scientist Award and INAEYoung Engineering Award in 2016. He has been serving as an AssociateEditor in IEEE Transactions on Power Electronics since 2015.



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