Parallel JPEG2000 Parallel JPEG2000 Compression SystemCompression System

Performed by: Dmitry Sezganov, Vitaly SpectorInstructor: Stas Lapchev, Artyom Borzin

Abstract

• Imaging satellites are experiencing rapid growth in imaging capacity. This is leading to higher data rates, and driving an increase in on-board storage capacity and downlink capability.

• Image compression is an excellent solution for this problem. By reducing the size of the image data, the overall system performance is improved.

• It must be high rate, since compression must be done prior to storage to reduce storage capacity.

• Typical image data rates are several Gbits per second, so the compressor must operate at speeds on the order of several hundred Mbits per second.

Abstract

JPEG2000Encoder

JPEG2000Decoder

Environment

The system is implemented on the following platforms:

• Virtex-II Pro Development Board;

• ADV202 JPEG2000 Video Codec;

• PC Simulation;

Project Requirements

The purpose of this project is building a prototype of parallel JPEG2000 compression system. The following list outlines the highest abstraction level requirements:

• Minimal input data rate is about 1.5Gbps.

• A user can choose different data source for system input.

• Defining compression parameters:

1.Tile/Image size.

2.Reversible/Irreversible compression mode.

3.Bit rate control with user defined rate/quality levels.

Project Requirements

• The system should report progression status (percentage, errors, etc.).

• Debugging capabilities – system architecture must support debug modules on each abstraction level, gathering information from child units in run-time for statistical analysis (revealing system bottlenecks, debug information).

• The resulting compressed output stream have to be saved to disk for system verification purposes (compressed images may be displayed in GUI).

Architecture

Channel #1Channel #2TestingModule

Compression

Unit

•There is a need of simulation data input stream with defined high bit rate, which cannot be obtained directly from the PC.

•That’s why we are going to use another board that will provide this channel.

Architecture

• Channel #1 may be implemented using standard Ethernet PCI card.

• Channel #2 requires high data rates and therefore two boards must communicate through Rocket IO ports in two directions enabling 2.5 Gbps efficient throughput.

• Needed speeds are not achievable upon data Channel #1. To solve this problem one picture could be loaded to the Testing Module and then duplicated to generate a needed bit rate.

Channel #1Channel #2TestingModule

Compression

Unit

ArchitecturePC

Logic

Logic

Memory

ADV202 ADV202 ADV202

Testing Board

Compression Board

Codec Card

Loading image through Ethernet

Duplicating and sending image through Rocket I/O channel

Tiled image data

Bus

Data flow

ArchitectureFunction()

send_packet()

Ethernet driver

Ethernet card

PC

Ethernet Controller

PowerPC

SDRAM Controller

CallBack()

Testing Board

UART Controller

Application Console

COM Port

SDRAM

ArchitectureTesting Board

Rocket I/O

PowerPC

Codec Controller

Compression Unit

Rocket I/O Controller

ADV202

PowerPC

Rocket I/O Rocket I/O

SDRAM

SDRAM Controller

ADV202….

Testing Board Design

The Virtex-II Pro development board does not have built-in Ethernet port. Expansion communication card will be used.

Required signals are assigned to appropriate pins in Virtex-II Pro FPGA.

Testing Board Design

DRAM (external memory)

OPB Bus

PLB Bus

PPC405

BRAM_IF_CNTRL

BRAM

PLB2OPB_BRIDGE

GPIO

OPB2PLB_BRIDGE

UARTLITE ETHERNET

Interrupt ControllerRocket I/O

Current Status

• Learning ADV202 Codec: features, operation modes, etc.

• Tools for development of embedded systems.

• Learning Virtex-II Pro Development Board – modifying existing working program.

• Integrating Ethernet controller to existing project and writing source code which operates its driver.

Plans and Times

• Finish integrating the Ethernet Controller and establish full duplex connection between the PC and the Testing Board – 1 week.

• Designing the Compression Board + exact definition of all data protocols (Ethernet, Rocket I/O) – 2 weeks.

• Developing detailed Codec Card design – 1.5 weeks.

• Drawing Codec Card ORCAD layout – 2 weeks.

Total: 6.5 weeks at 50% confidence level (+ 2.5 weeks for unpredictable difficulties)