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Introduction

Information and telecommunication technology has been rapidly developing with advanced semiconductor devices. However, the power consumption of field-effect transistors (FETs) with nanoscale channel length is considerably high owing to off-state leakage current and operation voltage, which are difficult to scale down [1]. These power consump-tion issues result in temperature increase in semiconductor

chips, decrease in sustainment time in batteries, and degrada-tion in the reliability of electronic devices. To resolve power consumption problems, several efforts have been made for lowering operation voltage and off-state leakage current. In particular, the tunneling FET has attracted considerable atten-tion as a low-power device [2].

Quantum-mechanical band-to-band tunneling (BTBT) is the primary mechanism of the tunneling FET, which is different from the conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In the conventional MOSFET, slope, which can be represented by the subthreshold swing (SS), has

Journal of Physics D: Applied Physics

Vertical-tunneling field-effect transistor based on MoTe2/MoS2 2D–2D heterojunctionBondae Koo1,2,3, Gwang Hyuk Shin1,3, Hamin Park1, Hojn Kim1 and Sung-Yool Choi1,4

1 School of Electrical Engineering, Graphene/2D Materials Research Center, KAIST, Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea2 System LSI, Samsung Electronics, Samsung-ro, Giheung-gu, Yongin-Si, Gyeonggi-do 17113, Republic of Korea

E-mail: sungyool.choi@kaist.ac.kr

Received 11 July 2018, revised 30 August 2018Accepted for publication 17 September 2018Published 8 October 2018

AbstractWe demonstrate a vertical-tunneling field-effect transistor (FET) based on a MoTe2/MoS2 heterojunction. MoTe2 exhibits p-type characteristics, and it has a relatively small band gap and low electron affinity among 2D materials. On the contrary, MoS2 exhibits high electron affinity and n-type characteristics. Therefore, it is possible to improve the tunneling property by stacking two materials. X-ray photoelectron spectroscopy analysis was carried out to confirm the band alignment between MoTe2 and MoS2, and it was confirmed that the stack of MoTe2 and MoS2 forms a staggered structure suitable for band-to-band tunneling. To improve the electrical characteristics of the device, MoS2 with high conductivity was placed on the upper part of the heterojunction, on which the top gate was formed, and gate controllability was improved. In addition, when a source/drain was formed by considering the work function of MoTe2 and MoS2, Pd was deposited on MoTe2 and Ti was deposited on MoS2 to lower contact resistance and suppress the ambipolar characteristics of MoTe2. Consequently, the MoTe2/MoS2 heterojunction vertical tunneling FET achieved a low subthreshold swing of 34 mV/dec and a high on/off ratio of 106 at room temperature. In addition, we confirmed band-to-band tunneling through temperature dependent transfer characteristics.

Keywords: MOSFET, tunneling transistor, heterostructure, MoS2, MoTe2, low-power device

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3 These two authors contributed equally to this work.4 Author to whom any correspondence should be addressed.

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https://doi.org/10.1088/1361-6463/aae2a7J. Phys. D: Appl. Phys. 51 (2018) 475101 (7pp)

https://orcid.org/0000-0002-0960-7146mailto:sungyool.choi@kaist.ac.krhttps://doi.org/10.1088/1361-6463/aae2a7http://crossmark.crossref.org/dialog/?doi=10.1088/1361-6463/aae2a7&domain=pdf&date_stamp=2018-10-08publisher-iddoihttps://doi.org/10.1088/1361-6463/aae2a7

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a fundamental limit of 60 mV/dec at room temperature owing to the thermal diffusion mechanism. However, BTBT in the tunneling FET allows for steep-slope characteristics, which can reduce operation voltage and off-state leakage current [3–8]. Using these unique properties of the tunneling FET, the power consumption in transistors can be significantly reduced.

In recent years, 2D semiconductor materials, such as trans ition metal dichalcogenides (TMDs), have been utilized as channel materials in the tunneling FET owing to several advantages [9–17]. First, the ultra-thin layered structure with van der Waals bonds provides good electrostatics [18–20], which improve steep-slope characteristics. Second, the band gap of TMDs can be controlled depending on their thickness through the quantum-confinement effect [21–25] which is a useful property for engineering the tunneling FET. Third, the clean interface without dangling bonds reduces trap sites, and it can improve the SS [26]. Finally, flexibility and transpar-ency [27] allow for several applications [28–33] such as wear-able devices and smart windows.

In this study, we demonstrate a vertical tunneling transistor with only a 2D semiconductor channel of n-type MoS2 and p-type MoTe2. Through x-ray photoelectron spectroscopy (XPS) analysis, the band alignment between MoTe2 and MoS2 is confirmed to be a staggered structure suitable for tunneling. This combination of 2D materials can provide a low SS and suppress ambipolar behavior. In addition, the vertically stacked p-n junction geometry allows for a large tunneling current owing to wide tunneling area in the overlapped junc-tion. Furthermore, a Ti contact with MoS2 and a Pd contact with MoTe2 are utilized to reduce the contact resistance of the device. With these device designs, our tunneling FET shows excellent performance with a low SS of 34 mV/dec, a high

on/off ratio of 106, and the BTBT mechanism in temperature-dependent I–V measurement.

Experimental method

A p-type doped 4 inch 90 nm Si/SiO2 wafer is used as the sub-strate to fabricate the vertical tunneling FET with the MoTe2/MoS2 heterojunction. First, the wafer is divided into pieces with a size of 2 cm × 2 cm. Then, cleaning is performed to remove the defects present on the wafer. The cleaning solu-tion is prepared in a beaker at a ratio of H2SO4:H2O2 = 1:1, and the wafer is placed in the beaker for 10 min for cleaning. After cleaning, the wafer is washed with DI water. Next, a MoTe2 flake is transferred onto the Si/SiO2 wafer using a mechanical exfoliation method. Then, a MoS2 flake is trans-ferred onto another Si/SiO2 wafer using the same method. Thereafter, the wafer is annealed at a temperature of 300 °C for 2 h in a chamber of H2 gas at 200 Torr to remove the tape residue remaining on the upper side of the wafer. Then, three-layer MoS2 of 1.95 nm is heterobonded onto two-layer MoTe2 of 1.3 nm through a pick-up transfer process. The pick-up transfer method is described in detail in figure S1 (stacks.iop.org/JPhysD/51/475101/mmedia). After the heterojunc-tion is formed, source and drain regions are defined using a MA6 facility by employing a photolithography process. Then, the source/drain metal material is deposited using a thermal evaporation process. 15 nm Pd/30 nm Au are deposited on the MoTe2 side and 15 nm Ti/30 nm Au are deposited on the MoS2 side. 15 nm Al2O3 is deposited as a gate dielectric using an atomic layer deposition (ALD). Finally, a top gate region is defined using a photolithography process and 25 nm Ni/30 nm Au are deposited. The entire process is illustrated in figure S2.

Figure 1. Device image and band alignment of MoTe2/MoS2 heterojunction vertical tunneling FET. (a) Device illustration of MoTe2/MoS2 heterojunction vertical tunneling FET. (b) Optical image of MoTe2/MoS2 heterojunction vertical tunneling FET before top gate deposition. (c) TEM image of MoTe2/MoS2 heterojunction vertical tunneling FET. (d) Band alignment of MoTe2/MoS2 heterojunction.

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Result and discussion

Figure 1(a) is the vertical device image of the MoTe2/MoS2 heterojunction vertical tunneling FET. To improve gate con-trollability, MoS2 is placed on top of the heterojunction, on which the top gate is formed. Figure 1(b) is the optical image of the MoTe2/MoS2 heterojunction vertical tunneling FET before top gate deposition, and it can be confirmed that the heterojunction bonding between MoTe2 and MoS2 is well formed. The vertical heterojunction of MoTe2/MoS2 can pro-vide a higher on-state current because BTBT occurs on the entire overlapped heterojunction surface [10]. The optical image after the top gate is formed is shown in figure  S3. Transmission electron microscopy (TEM) and energy disper-sive spectroscopy (EDS) mapping were performed to confirm the stacking structure of the device. Samples for TEM mea-surements were prepared using the focused ion beam method. Figure 1(c) shows the result of TEM. It can be confirmed that MoS2 consists of three layers (1.95 nm) and MoTe2 consists of two layers (1.3 nm). In addition, the two materials are precisely bonded to each other, and they form a van der Waals inter-face. This van der Waals stack of MoTe2/MoS2 with nanoscale thickness exhibits good electrostatics and a short tunneling barrier width, which is determined by channel thickness, and hence, it can improve on-state current with a low SS [10]. EDS mapping results are shown in figure S4. XPS analysis was performed to confirm the band alignment of MoTe2 and MoS2. Al Kα (1486 eV) was used as an x-ray source for the analysis as shown in figure S5. The reference peak of C 1s of

the binding energy was 284.8 eV, and the binding energy peak of MoTe2 and MoS2 were aligned with the reference peak. As a result of aligning the reference peak and confirming band alignment, the heterojunction structure between MoTe2 and MoS2 was determined to be staggered, and it was confirmed that conduction band offset (CBO) and valence band offset (VBO) were 0.42 eV and 0.68 eV, respectively. Moreover, MoTe2 exhibited relatively low electron affinity (EA) with a band gap of 1.04 eV, and MoS2 exhibited relatively high EA with a band gap of 1.3 eV. This staggered heterojunction with small band overlap provides a low tunneling barrier height, which leads to large on-state current with a low SS [10]. Figure 1(d) shows the band alignment between the MoTe2 and MoS2 heterojunction.

The device was fabricated using different metal materials for the source and drain to lower the contact resistance of the device and to reduce the ambipolar characteristics of MoTe2. As shown in figure  2, two different transistor devices were fabricated by depositing different metal materials on the same MoTe2 channel, and electrical characteristics were confirmed. Pd and Ti were used for the experiment. Figure 2(a) shows the optical image of this device. On the same MoTe2 channel, there is a transistor with a Pd contact on the left and a tran-sistor with a Ti contact on the right. Channel length is 5 µm. Figure 2(b) shows transfer curves. The transistor with the Pd contact exhibits reduced ambipolar characteristics compared to the transistor with the Ti contact. The work function of Pd is located close to the valence band maximum of MoTe2, and the majority of carriers are transported by the hole.

Figure 2. MoTe2 contact characteristics. (a) Optical image of MoTe2 transistor. (b) Comparison of transfer characteristics between Pd and Ti contacts. (c) Comparison of output characteristics between Pd and Ti contacts. (d) Output characteristics of MoTe2 transistor with Pd contact. The contact resistance and the mobility of the MoS2 and the MoTe2 FETs are shown in figure S7.

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The work function of Ti is located in the middle of the band gap of MoTe2, and carriers are transported by the electrons and hole depending on gate voltage. For these reasons, ambi-polar characteristics are suppressed in the Pd contact com-pared to Ti contact. Figure 2(c) shows that the drain current of the transistor with the Pd contact increases by two orders of magnitude relative to that of the transistor with the Ti con-tact. Figure 2(d) shows the output characteristics of the MoTe2 transistor with the Pd contact. It shows that Pd and MoTe2 form an Ohmic contact. As a result, it is confirmed that the MoTe2 device with the Pd contact significantly increases the amount of cur rent and decreases ambipolar characteristics compared to the device with the Ti contact. This is because Pd metal has a large work function and thus a low Schottky barrier height when bonded to MoTe2 [34]. On the contrary, Ti metal has a small work function and forms a low Schottky barrier when bonded to MoS2. Therefore, to maximize these advantages, Pd metal was deposited on the MoTe2 side and Ti metal was deposited on the MoS2 side.

Figure 3 shows the electrical characteristics of the MoTe2/MoS2 heterojunction vertical tunneling FET at room temper-ature. Figure 3(a) shows the transfer curve under reverse drain bias conditions. It shows a minimum SS of 34 mV/dec and high on/off ratio of 106 at a drain voltage of −0.6 V. The SS

in the tunneling transistor can be lowered by several param-eters of the tunneling probability including effective mass (m*), band gap (Eg), elementary charge (q), reduced Planck constant (�), energetic difference (∆Φ), and screening tun-neling length (λ), according to the Wentzel–Kramer–Brillouin approximation [2].

TWKB ≈ exp(−4λ»

E3g√

2m∗

3q�(Eg +∆Φ)).

In particular, screening length (λ) can be reduced by designing the gate dielectric with high permittivity (high-k), the channel thickness and low effective oxide thickness [2]. Hence, we fab-ricated the tunneling FET using thin layer channel with MoS2 of 1.95 nm and MoTe2 of 1.3 nm in order to lower the λ. TWKB values of our device were estimated in figure S10. On the con-trary, under a drain voltage of 0.6 V in the forward bias con-dition, the minimum SS is 144 mV/dec, which is larger than that in the reverse bias condition. This is shown in figure 3(b). This is significant in that it achieves an SS of below 60 mV/dec, which is the limit of conventional MOSFETs, and simul-taneously provides a high on/off current ratio using a 2D mat-erial as a channel. The reason for the large difference between the SS for the reverse and forward bias conditions is that the charge transport mechanism under the two voltage conditions

Figure 3. Electrical characteristics of MoTe2/MoS2 heterojunction vertical tunneling FET. (a) Transfer characteristics under reverse drain bias. SSmin as a function of drain current is represented in figure S8. Gate leakage current is considerably smaller than drain current, as shown in figure S9. (b) Transfer characteristics under forward drain bias. (c) Output characteristics under reverse and forward drain bias. (d) Band diagrams under reverse and forward drain bias.

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is different. We calculated the majority and minority carriers of MoS2 and MoTe2 to confirm the p-n junction characteristic as shown in figure  S11. Under reverse bias, when the posi-tive gate bias is applied, the energy band of MoS2 descends and electrons are accumulated. The band alignment between MoTe2 and MoS2 is largely misaligned, which causes current to flow through BTBT, thereby achieving a low SS. On the contrary, under forward bias, even if the positive gate bias is applied, band alignment distortion is mitigated so that BTBT does not occur and current flows through a band hill owing to diffusion, resulting in a relatively large SS. However, when the negative gate bias is applied whether the reverse or the forward bias, the energy band of MoS2 ascends and electrons are depleted, which causes the suppression of the current flow. The abovementioned operating characteristics are shown in the band diagram in figure 3(d). Figure 3(c) shows the output char-acteristics of this device. Output characteristics were measured by varying gate voltage from 3 V to −3 V in 1 V increments, and drain current characteristics were confirmed according to the variation in the drain voltage at each gate voltage condition. As a result of the measurement, it was confirmed that drain current increases as gate voltage increases in the positive direc-tion. This is because the gate is located at the top of MoS2, and as gate voltage increases in the positive direction, a large number of electrons are accumulated in MoS2.

Temperature influence measurement was performed to verify that BTBT occurs in the MoTe2/MoS2 heterojunction vertical tunneling FET. Temperature was varied from 300 K to 180 K. Figure 4(a) shows the temperature-dependent transfer characteristics measured under the reverse bias condition. Figure 4(b) shows the SS as the function of temperature. The SS determined at each temperature was classified into an average value and a minimum value. As a result, it was con-firmed that there is almost no change in the SS with temper-ature in the reverse bias condition. This is because tunneling current is not affected by temperature. The change in the SS with temperature under the forward bias condition is shown in figure S6. The Arrhenius plot was created to further elucidate the influence of output characteristics owing to temperature change. Figures 4(c) and (d) show the results for the reverse and forward drain bias conditions, respectively. The temper-ature-dependent change in the forward bias condition is con-siderably large compared to that in the reverse bias condition.

Conclusions

We fabricated a MoTe2/MoS2 heterojunction vertical tun-neling FET and evaluated its characteristics. Through XPS analysis, we confirmed that the band alignment between MoTe2 and MoS2 is staggered, and CBO and VBO were

Figure 4. Temperature dependence of MoTe2/MoS2 heterojunction vertical tunneling FET. (a) Transfer characteristics according to temperature change under reverse drain bias. (b) Change in SS with temperature under reverse drain bias. (c) Arrhenius plot under reverse drain bias. (d) Arrhenius plot under forward drain bias.

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obtained. In addition, different metal materials were depos-ited on the source and drain to lower the contact resistance of MoTe2 and MoS2, respectively, resulting in increased current and reduced ambipolar characteristics of MoTe2. As a result, the device achieved a minimum SS of 34 mV/dec and a high on/off ratio of 106 at room temperature. In addition, transfer curves were obtained by changing the temperature from 300 K to 180 K. Tunneling current was verified by confirming the temperature-independent SS characteristics under the reverse bias condition. It was proved that a high performance tun-neling FET can be realized using a heterojunction between MoTe2 and MoS2. Based on these results, we expect that 2D materials will play an important role in developing tunneling devices.

Acknowledgment

This research was supported by grants from the Creative Materials Discovery Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Sci-ence, ICT, and Future Planning (NRF-2016M3D1A1900035), and the Global Frontier Research Center for Advanced Soft Electronics (Grant No. 2011-0031640).

The supporting information contains the following figures: pick-up transfer process of MoS2 and MoTe2 flakes; device fabrication process; optical image of MoTe2/MoS2 vertical tunneling FET; EDS mapping of the cross-sectional image in TEM; XPS data; temperature-dependent transfer characteristics of the MoTe2/MoS2 vertical tunneling FET.

The authors declare no competing financial interest.

ORCID iDs

Sung-Yool Choi https://orcid.org/0000-0002-0960-7146

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Vertical-tunneling field-effect transistor based on MoTe2/MoS2 2D–2D heterojunctionAbstractIntroductionExperimental methodResult and discussionConclusionsAcknowledgmentORCID iDsReferences