Panda PCB for prototype status report by D Malkevich on behalf of the ITEP group ITEP.
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Transcript of Panda PCB for prototype status report by D Malkevich on behalf of the ITEP group ITEP.
Panda PCB for prototype status report
by D Malkevich on behalf of the ITEP group
ITEP
ALICE TOF experience - module based on PCB
- Module design based on multi layer PCB both for mechanical construction and
signal routing
- Minimal Radiation Length, => no cooling and cabling inside module
- Signal transmission lines, HV and L.V. distribution “on board”
PANDA prototype design :
Strip consists of 8 th single cell DRPC
chambers fixed at 6 layers PCB and
merged into common gas volume.
4 gapsR=1010Ω
4 gapsR=1012Ω
4 gapsR=1011Ω
6 gapsR=5*1012Ω
6 gapsR=1010Ω
4 gapsR=5*1010Ω
4 gapsR=5*1011Ω
4 gapsR=5*1012Ω
PCB design (Capture)
R 3 7
2 0 0
C 2 8
1 0 0 n F
+
C 4 5
4 . 7 u F
C 5 3
1 0 0 n F
+5 V A
C 4 8
1 0 n F
J P 3
J U M P E R12
+5 V A
+
-
+
+
-
-
A D 8 1 4 6 / L F C S P V Q C P 2 4 1
U 4
1 2 3 4 5 6
7
8
9
1 0
1 1
1 2
2 4
2 3
2 2
2 1
2 0
1 9
18 17 16 15 14 13
OP
D
Vs-
_2
-IN
A
+IN
A
Vs-
_5
-OU
T A
+O U TA
V s +_ 8
+O U TB
-O U TB
V s +_ 1 1
+O U TC
V s +_ 2 4
-I N B
+I N B
V s -_ 2 1
V o c m A
V o c m B
Voc
mC
Vs+
_17
-IN
C
+IN
C
Vs-
_14
-OU
TC
R 2 0
1 1
TO T1 +
R 3 2
2 0 0
R 2 5
1 kC 3 2
1 0 0 n F
+5 V D
R 2 32 0 0
J 4
5 4
1
32
AGND
C 7
1 p F
+5 V A
+
C 5 7
4 . 7 u F
-5 V A
R 3 02 0 0
C 2 7 8
1 n F
-5 V A
AGND
C 4 4
1 0 0 n F
+
C 5 2
4 . 7 u F
C 8
1 0 0 n F
R 8
5 1
R 1 8
2 0 0
R 2 6
2 0 0
C 5 5
1 0 0 n F
C 3 6
1 0 0 n
R 1 7
2 0 0
AGND
-5 V D
C 2 4
1 0 n F
TO T2 +
L e m o
-5 V A
C 2 9
1 0 0 n F
R 1 4
2 0 0
C 2 11 n F
+5 V A
R 2 7
2 0 0
+
C 2 7
4 . 7 u F
R 3 5
1 1
C 1 1
1 0 0 n F
DGND
C 2 2
1 0 n F
Q 1
2 N 2 2 2 2
R 4
1 k
J 2
54
1
3 2
R 3 62 0 0
+
C 5 4
4 . 7 u F
AGND
J P 1J M P 9
132
+5 V A
R 3 12 0 0
U 5
A D 8 3 5 0
1
2
8
4
536 7
I N +
E N B L
I N -
O U T+
O U T-+V C CG N D G N D 2
J 1
5
4
1
3
2
Z0=2x100
-5 V A
J P 2
J U M P E R12
U 3 B
A D 8 0 5 6
75
6
84
O u tI n +
I n -
Vcc
Vee
+5 V A
C 1 3
4 . 7 u F
R 3 8
2 0 0
+
C 1 6
4 . 7 u F
C 2 5
1 0 0 n F
R 2
1 k
1 3
2
TO T2 -
-5 V A
R 3 3
5 1
J 354
1
3 2
D 1
B Z V 5 5 -B 3 V 3
R 1
5 1
CH1
C 1 8
1 0 n F
R 3
2 k
R 1 1
3 3 0
+
C 5 0
4 . 7 u F
C 5 8
1 0 0 n F
C 3 4
1 0 n F
C 2
1 0 0 n F
+
C 6 3
4 . 7 u F
Threshold
R 2 9
2 0 0
Z0=2x100
+
C 5
4 . 7 u F
C 4
1 0 n F
D 2
B A V 9 9 / S O T
3
1 2
R 1 9
1 k
+
C 1 2
4 . 7 u F
L e m o
R 6
1 k
C 1 5
1 0 0 n F
R 2 8
2 0 0
R 3 4
2 0 0
+
C 3 7
4 . 7 u F
+5 V A
C 3 11 p F
C 4 6
1 0 0 n F
C 2 3
1 0 n F
C 1 7
1 0 0 n F
R 2 2
2 0 0
R 7
2 0 0
Test
R 5
1 k
+
C 9
4 . 7 u F
C 4 7
1 0 p F
R 1 5
2 0 0
C 2 6
1 0 0 n F
+
C 3 0
4 . 7 u F
C 4 2
1 0 n F
C 4 01 n F
C 3 9
1 0 n F
CH2
+C 3
4 . 7 u F
-5 V A
C 5 6
1 0 0 n F
C 11 0 0 n F
+5 V A
U 1
A D 9 6 6 8 7
8
7
9
1 0
1
2
1 6
1 5
41 3
31 4
51 21 16
in 1 +
in 1 -
in 2 +
in 2 -
o u t 1 +
o u t 1 -
o u t 2 +
o u t 2 -
E N 1E N 2G N D 1G N D 2
E N I 1E N I 2
V c cV e e
C 4 3
1 0 n F
+5 V A
R 1 3
3 3 0
AGND
C 3 8
1 0 p F
R 1 0
3 3 0
+5 V A
U 2
A D 8 3 5 0
1
2
8
4
536 7
I N +
E N B L
I N -
O U T+
O U T-+V C CG N D G N D 2
R 2 4
2 0 0
C 6
1 0 0 n F
AGND
C 1 0
1 0 n F
U 3 AA D 8 0 5 6
13
2
84
O u tI n +
I n -
Vcc
Vee
+5 V AC 5 1
1 0 0 n F
C 4 1
1 0 n F
P G 1S o ld e r J u m p e r
12
+
C 3 3
4 . 7 u F
C 4 9
1 0 n F
R 2 1
2 0 0-5 V A
TO T1 -
C 2 7 9
1 n F
-5 V A
C 6 2
1 0 0 n F
R 1 2
3 3 0
C 3 5
1 0 n F
+
C 5 9
4 . 7 u F
R 1 4 5
1 0 0 k
J 1 4S u h n e r 3 / B 2 3 2 U N E F 2 A 1
2 R 1 4 6
1 M
HV
1
R 1 4 7
1 0 k
C 2 6 4
2 n F
C 2 5 8
2 n F
+H V
C 2 5 5
4 . 7 u F
+5 V D
C 2 5 6
1 0 n F
+5 V D
C 2 5 3
4 . 7 u F
C 2 5 4
1 0 n F
L 3
2 2 u H
DGNDPWRD
J 1 3
W F 3 R
123
-5 V D
C 2 5 7
4 . 7 u F
C 2 5 01 0 n F C 2 5 2
1 0 n F
L 4
2 2 u H
C 2 5 14 . 7 u F
-5 V D
We are going to do :
Differential transmission lines quality
Resistive coating optimization
Resolution, efficiency, rate dependence, and streamer fraction
using this prototype
Pre amplifier Main amplifier Amplitude buffers
Amplitude outputs
TOT outputs
Test input
Internal / ExternalThreshold
HV filter
LV filter
Differentialtransmission lines
HV, LV and test line
TOTs, fast “OR” + Amplitude
outputs
Discriminator
PCB design (Layout)
DiscriminatorsAD96687
Main amplifiers AD8146
Buffers AD8056
Fast “OR”
Test 50 Ohm line
H.V. connector
Test input
External Threshold connector
L.V. connectors
Amplitude outputs
TOTs + Fast “OR”
Last updates• Discriminator MAXIM 9600 changed to AD96687. Just to have both amplifier and
discriminator from one vendor.• PCB Stack up parameters for structure with 200 Ohm differential lines preliminary
estimated with respect to reality i.e. available materials of manufacture, compromise between possibility and prices. (We are still discussing with manufacture precision we can achieve)
Conclusion
•6 layers PCB for 8th channels prototype was design in ORCAD.•PCB stackup design parameters for 200 Ohm differential lines preliminary estimated. Calculation based on real available materials for some manufacture.•Transmission lines quality test will be taken ASAP when PCB already done. Test results could give conclusion about signal transmission possibilities up to 1,5 m (we want to produced PCB ASAP but we haven’t funding for the moment)•Schematic and PCB design for real size prototype will be make after confirmation final mechanical design. (PCB will be produced only after DIRC design will be fixed)