Pad Cratering: Prevention, Mitigation and Detection Strategies

Pad Cratering: Prevention,

Mitigation and Detection

Strategies

Cheryl Tulkoff

[email protected]

APEX EXPO 2013 Pad Cratering Tutorial

San Diego, CA

Pad Cratering Course Abstract

Pad cratering is defined as cracking which initiates within

the laminate during a dynamic mechanical event such as

In Circuit Testing (ICT), board depanelization, connector

insertion, and other shock and vibration inducing

activities.

During this tutorial, you'll learn about the key drivers,

measurement and detection protocols, and preventive

tactics for this serious but prevalent failure. Pad cratering

was first recognized in BGA packages but newer

leadless, bottom termination components are also

vulnerable.

Tutorial Outline

MODULE 1: Introduction

Pad Cratering Defined

Pad Cratering History

Pad Cratering Drivers

Is Pad Cratering a Pb-Free Issue?

At Risk components

MODULE 2: Testing Methodologies

Overview of IPC Industry Test Standards

Alternative Test Methods

MODULE 3: Detection Methods

ICT & Functional Test

Electrical Characterization

Alternative Test Methods

Acoustic Microscopy

MODULE 4: Failure Analysis Techniques

Failure Analysis Overview


Cross-Sectioning

Dye-N-Pry

X-ray

MODULE 5: Mitigation Techniques

Corner Glue

Component Practices

Pad Design & Layout

ICT Fixture Evaluation

Assembly Process Evaluation

New acceptance criteria for laminate materials

MODULE 6: Prevention Methods & Future

Work

Module 1: Introduction

Pad Cratering Defined

Pad Cratering: Strain & Flexure

o Cracking initiating within the PCB laminate during a

dynamic mechanical event

o In circuit testing (ICT), board depanelization, connector

insertion, shock and vibration, etc.

G. Shade, Intel (2006)

Laminate Cracking Leads to Trace

Fracture

Bending

Force

Functional failure

will occur

Trace routed externally

7

Pad Cratering

Drivers Finer pitch components

More brittle laminates

Stiffer solders (SAC vs. SnPb)

Presence of a large heat sink

Location

PCB thickness

Component size & rigidity

Temperatures & cooling rates

Difficult to detect using standard procedures X-ray, dye-n-pry, ball shear, and

ball pull

Intel (2006)

8

Is Pad Cratering a Pb-Free Issue? No,

but…

Paste Solder BallAverage Fracture

Load (N)Std Dev (N)

SnPb SnPb 692 93

SnPb 656 102

Sn4.0Ag0.5Cu 935 190Sn4.0Ag0.5Cu

35x35mm, 388 I/O BGA; 0.76 mm/min

Roubaud, HPAPEX 2001

Pad cratering has been around for a

while……

Module 2:Testing

Methodologies

Industry Standards

Industry Response

Alternative Testing Methodologies

Documents 3 test methods

Pin Pull

Ball pull

Ball shear

Each test has pros and cons

No pass or fail criteria

User must define what is acceptable

Base on design and reliability requirements

IPC-9708 Pad Cratering Test Methods

Weakest link in the system fails first

BGA Mechanical Loading Failure Modes

Choice of pad geometry affects BGA

failure rate and failure location

IPC 9708 – SMD versus NSMD Structures

Defined

Good for any pad geometry – no balls required

Most sensitive to board material and design variables

IPC 9708 Pin Pull Test

Requires

pins to be

soldered to

pads

IPC 9708 Ball Pull Test

Quick test after BGA ball attach

No expensive pins required

Almost as sensitive as pin pull

BGAs only

Highly dependent on

solder ball so process

control is critical

IPC 9708 Ball Shear Test

Quick test after BGA ball attach

Less control needed than ball pull test

BGAs only

Least sensitive to design and material variables

Cisco’s Analysis of Test Variables Impact

Category Variable Critical Factor

Assembly

&

Calibration

Pin Temperature High

Printed Solder Paste High

Printed Paste Volume Low

Testing Pad Size High

Pin Diameter High (larger than pad)

Multiple Reflows Medium (depends on PCB material

Pull Speed Medium (higher speed = cleaner results)

Pull Temperature Low

Pull Angle Low (if solder paste is printed)

PCB Material High

Resin Content/Glass

Style

Medium (depends on PCB material)

Pad Geometry Low

Universal Instruments Test Method

Comparison Results

HBP/HPP

Longer to run: 2-3 minutes

Can run as cyclic test

Paste deposit or solder ball

does not affect test result

Suited to universal test:

pad geometries & angles

Loading mode correlates to

warpage/bending


Comparison Results

Cold Bump Pull

Easy & fast: 15-30 seconds

per test

Limited to vertical pull

Loading correlates to

warpage/bending

Choice of sphere solder alloy

doesn’t affect strength

Speed dependence noted on

filled phenolics


Comparison Results

Easiest & quickest to run

Universal test

Lower strength than pull

Correlates to CTE

mismatch & shear modes

Different mode on

phenolic resins

Coupon-based testing

Allows direct comparison between design,

materials and process changes

Pin pull & ball pull characterize tensile

loading

Ball shear characterizes shear loading

Use at least 2 of the 3 tests so that both

tensile & shear loads are covered

Testing Recommendations

Details test & equipment required Measurement &

reporting for both strain & strain rate

SMT devices covered, no discretes

Measure all BGAs with a package body size =/> 27 mm x 27 mm Measure 3 largest

otherwise

IPC-9704 – Strain Gage Testing

Strain induced failures include ball cracking, trace damage, pad lifting and substrate damage

Rosette Strain Gages

Measures strain on several axes at the same time

Pre-wired with either two 3-ft. (1 m) leads or three 9-ft. (3 m) leads

Determine the magnitude and angle of stress

Strain Gages for both static and dynamic applications Broad Temperature Range

Grid strains e1 and e3 should be oriented parallel to the edges of the package.

Grid strain e2 should be oriented diagonally away from package with respect to the edges of the package.

Consistent and precise placement of gages is critical to correlation of data between test location and samples.

Strain Gage Placement

IPC 9704

No pass / fail limits

3 strain limit

approaches

Component

supplier provided

Customer specified

Rate limited

Maximum allowable

strain versus rate

and PCB thickness

IPC 9702

Used to characterize fracture strength of board level interconnects

Failure modes from this test are not easily differentiated High speed test

Short duration

Failures in quick succession

4 Point Bent Test

Module 3: Detection

Methods

Limited visual inspection options

Will cover more in failure analysis techniques


Critical for both detection & failure analysis

Functional and in circuit testing (ICT)

Acoustic Microscopy

Highly Accelerated Life Testing (HALT)

Detection Methods

30

Electrical Characterization: PCB

Assembly Level

Narrowing scope is critical to identifying the issue

A known good or reference component is often

required for comparison

Functional testing Most valuable

JTAG (joint task action group) boundary scan Allows for testing ICs and their interconnections using four I/O pins

(clock, input data, output data, and state machine mode control)

Allows for relatively accurate identification of failure site, but rarely

performed on failed units (primarily replacement for In Circuit Test-

ICT)

31

Electrical Characterization: PCB

Assembly Level Oscilloscope

Measures voltage fluctuations as a function of time (passive)

Useful in probing operational circuitry

Digital capture provides better documentation capability

Isolation of attached components

Attempt to perform as much electrical characterization without component removal

Consider trace isolation

Environmental stresses

Approach similar to bare board

Vibration

Induce Vibration on Assembly

A Dremel tool can be

used to induce local

vibration during

debugging

Can “force” intermittent

failures out of hiding at

benchtop debug

Replaces “finger

press” method with

some control

ICT is performed using vacuum and spring probes Can “compress” components & laminates into

making electrical contact

High rate of cratering escapes from this process

Depends on test coverage and access

Best at capturing complete fracture – small cracks not found

In Circuit Test (ICT)

Image Courtesy of Rematek

http://www.rematek.com/download_center/board_stress_analysis.pdf

CalPoly study showing failure of electrical testing to capture all defects

Pad Cratering & Electrical Test Detection

Board Level Failure Analysis of Chip Scale Package Drop

Test Assemblies, 2008 International Microelectronics And

Packaging Society.

Majority of failures occur at corners of packages:

locations of stress & strain concentrations

Electrical Failure Pareto from CalPoly

Study

Board Level Failure Analysis of Chip Scale Package Drop

Test Assemblies, 2008 International Microelectronics And

Packaging Society.

Cisco has developed a detection method based on Acoustic Microscopy

Referred to as Acoustic Emissions (AE)

Appears to detect onset earlier and with greater capture rate than electrical methods

Modified 4 point bend test

Full assembly based test rather than test vehicle

Intent is to capture partial/small cracks which could propagate to failure Some studies show 20% crack growth during thermal

cycling

Cisco Alternative Test Methodology

“A New Approach for Early Detection of PCB Pad Cratering Failures,” “COMPREHENSIVE METHODOLOGY TO

CHARACTERIZE AND MITIGATE BGA PAD CRATERING IN PRINTED CIRCUIT BOARDS”,

H2O or other

fluids

Transducer

Receiver

Inspect internal structures through

the use of high frequency (>20

kHz) sound waves

Requires immersion in water

(deionized) since acoustic signals

reflected by air

Allows for accurate detection of

voids and delaminations

Can be non destructive if no fluid

sensitive components are

present.

Process Options

Frequency

Transmission mode

Imaging

37

Acoustic Microscopy

Review

38

Acoustic Microscopy: Transducer

Frequency

High frequency

Short focus Low frequency

Long focus

1. Higher resolution

2. Shorter focal lengths

3. Less penetration

(Thinner packages)

1. Lower resolution

2. Longer focal lengths

3. Greater penetration

(Thicker packages)

General rules:

• Ultra High Frequency (200+ MHz) for flip chips and wafers.

• High Frequency (50-75 MHz) for thin plastic packages. (110MHz-UHF) for flip

chips.

• Low Frequency (15-30 MHz) for thicker plastic packages.

39

Acoustic Microscopy: Transmission Mode

Pulse-Echo: One Transducer

• Uses ultrasound reflected from the sample

• Can determine which interface is delaminated

• Requires scanning from both sides to inspect

all interfaces

• Provides images with high degree of spatial

detail

• Peak amplitude, time of flight (TOF), and phase

inversion measurement

Through Transmission: Two Transducers

• Uses ultrasound transmitted through the

sample

• One scan reveals delamination at all

interfaces

• No way to determine which interface is

delaminated

• Less spatial resolution than pulse-echo

• Commonly used to verify pulse-echo

results

Through Transmission Transmit

&

Receive

Transmit

Receive

Pulse-Echo

40

Acoustic Microscopy

Used when delamination or voiding is suspected

Electrical shorting within the package (delamination, electro-chemical migration)

Electrical opens (delamination, wire bond failure)

Insufficient thermal performance detected (i.e. die attach)

Some value for ceramic BGAs

Attenuation due to multiple interfaces prevents imaging of interconnects under PBGAs

10 MHz Data Acquisition Rate

Cisco Acoustic Emissions (AE) Test

Setup

Cisco Acoustic Emissions (AE) Test

Setup

Low speed and high speed testing performed to look at influence of strain rates along with total strain

Cisco Bend Test Parameters

Cisco Acoustic Emissions &

Electrical Failures

Cisco Acoustic Emission Study

Conclusions

Pad cratering identified at much lower strain levels than those detected electrically in other studies

Test method does not require custom daisy chained test vehicles

Potentially cheaper method for evaluating joints and laminates

Other failure mechanisms could potentially be detectable

Ceramic cracks, thermal cycling, shock, or vibration failures

Highly Accelerated Life Testing (HALT)

Series of environmental stress tests designed to understand the limitations of the design

Theory 1: The greater the margin between the limits of the design and the operating environment, the lower the probability of failure if defects are introduced during manufacturing

Theory 2: Not all field failures are due to wearout (motivation for accelerated life testing). Many failures due to introduction of “energy” into the system from multiple environmental stresses (thermal, vibration, power, humidity, etc.)

HALT

Phase One: Step Stress Testing

Increase the environmental stress (temperature, vibration,

electrical, etc.) until recoverable and non-recoverable

failures occur

Phase Two: Cyclic and Combinatorial Stress Testing

Thermal cycling (increasing ramp rates)

Thermal cycling + vibration

Requires understanding and analysis

Can’t “pass” HALT

Actions based upon failure mechanism and cost of fix

Step Stress Testing

Recommendations Perform Voltage Step Stress Test

Both high and low voltage

Test to recoverable and permanent failure

Perform Temperature Step Stress Test

High and low temperatures with 10 or 15C step

Dwell only long enough to test functionality

Pull max. and min. specified voltage at max. and min. specified

temperatures (“paint the corners”)

Perform for both hot and cold temperatures

Test to recoverable and permanent failure

Perform Vibration Step Stress Test

Starting at 5g and increasing in 5g increments

Finish at 30 or 40g’s

RoHS HALT Failure Analysis

Examples

Cracked Solder Joint:

BGA ball to BGA

substrate PCB Pad Cratering


Cracked traces to

BGA pads – outer

rows

BGA pads separated

from PCB


Pad Cratering in BGA

Laminate

Laminate Cracks -

Repair

Module 4: Failure

Analysis (FA) Techniques

Pad Cratering Failure Analysis

Difficult to detect using standard procedures

Companies frequently unaware of pad cratering until failure happens Recalls have been common and painful!

Potential warning signs:

Excessive BGA repair rate

High percentage of “defective” BGAs

High rate of “retest to pass” at in circuit test (ICT)

New X-ray potential with 3D m-CT inspection

Precision cross-sections are required to confirm

General Words of Wisdom on FA

Before spending time and money on Failure Analysis, consider the following:

Consider FA “order” carefully. Some tests will limit or eliminate the ability to perform further tests.

Understand the limitations and output of the tests selected.

Use partner labs who can help select and interpret tests for capabilities you don’t have. Don’t request a specific test. Describe the problem and

define the data and output needed.

General Words of Wisdom on FA…

Pursue multiple courses of action. There is rarely one test or one root cause that will solve the problem.

Don’t put other activities on hold while waiting for FA results. Understand how long it will take to get results

Consider how the data can help or be used. Information?

Change course, process, supplier?

Don’t pursue FA data if it won’t help or you have no control over the path it might take you down.

Some FA is just not worth doing!

Pad Cratering Failure Analysis

Techniques

Always start with Non-Destructive Evaluation (NDE)

Obtain maximum information with minimal risk of damaging or

destroying physical evidence

Emphasize the use of simple tools first

(Generally) non-destructive techniques:

Visual Inspection


Acoustic Microscopy

X-ray Microscopy

Thermal Imaging (Infra-red camera)

SQUID Microscopy

Known good or reference component is often required.

58

Failure Analysis Techniques

Destructive evaluation techniques

Dye N Pry

Cross-sectioning

Thermal imaging

Mechanical testing: wire pull, wire shear, solder ball shear, die shear

59

BGA Visual Inspection

BGA (Ball Grid Array)

Perimeter Inspection

Used to inspect solder

balls on the perimeter

of the package

Most common

failure site under

BGAs

Magnification up to

200x

60


Most critical step in the failure analysis process

Can the reported failure mode be replicated?

Persistent or intermittent?

Intermittent failures often incorrectly diagnosed as no trouble found (NTF)

Least utilized to its fullest extent

Equipment often shared with production and R&D

Sometimes performed in combination with environmental exposure

Characterization over specified or expected temperature range

Not designed to induce damage!

61

Electrical Characterization: PCB Assembly

Level

Functional is typically most valuable

JTAG (joint task action group) boundary scan

Allows for testing ICs and their interconnections using four I/O pins

Clock, input data, output data, and state machine mode control

Allows for relatively accurate identification of failure site, but rarely performed on failed units (primarily replacement for In Circuit Test)

Isolate components

Attempt to perform as much electrical characterization without component removal

Consider trace isolation (knife, low speed saw)

Environmental stresses can be added

Dye N Pry

Allows for quick, destructive

inspection for cracked or

fractured solder joints under

leadless components

(BGAs, BTCs)

http://www.electroiq.com/ind

ex/display/packaging-article-

display/165957/articles/adva

nced-packaging/volume-

12/issue-1/features/solder-

joint-failure-analysis.html

http://www.electroiq.com/index/display/packaging-article-display/165957/articles/advanced-packaging/volume-12/issue-1/features/solder-joint-failure-analysis.html



















Dye N Pry

Step 1: Apply dye along

the package edge so

that it can flow into

defective solder joints.

Step 2: Cure the dye

Step 3: Remove the

component

Where dye is,

solder/contact was not…

Cross-Sectioning

Standard method for confirming pad cratering

Method:

Saw to approximate area of interest

Pot in epoxy resins to aid polishing

Polish. medium dependent upon materials: typically diamond,

SiC, or alumina suspensions & embedded polishing cloths

Grind, Coarse to fine (600 grit to 0.05 um) to eliminate damage

from previous step, repeat

Final etch often used for microstructural relief

Optical/electron microscopy techniques used for inspection

High precision necessary – easy to grind through!

Typical Cross Sectioning Equipment

Inverted

Microscope

Polishing

Compounds,

Epoxies

Polishing & Grinding

Disks Precision Saw

Polishing

and

Grinding

Equipment

Specimen

Mounting

Nordson Dage X-Ray with

3D m-CT Inspection Option

Produces CT models for 3D sample analysis, virtual micro-sectioning and internal dimensional

Measurements for crack, void and reverse engineering

Potentially reduce the number of time-consuming micro-section analyses that are needed

Assist in identifying where to micro-section

Non-destructive

Module 5: Mitigation

Techniques

68

Potential Mitigations to Pad Cratering

Design Non-critical pads Solder mask defined vs. non-solder mask defined Pad Geometry Layout & PCB thickness

Limitations on board flexure

750 to 500 microstrain, component and layout dependent Process Control & Validation

Corner Glue

More compliant solder

SAC305 is relatively rigid, SAC105 and SNC are possible alternatives

New laminate acceptance criteria and materials

Component Supplier Practices

Intel Example

Pad design influences failure

Smaller pads result in higher stress under

a given load

Solder mask defined pads can provide

additional strength

Increases tolerable strain

But, moves failure location from pad crater

to intermetallic fracture

Pad Geometry

Connections to conductive

shape areas should have relief

to avoid solder mask defined

pads, allowing better adhesion

from ball to pad

The trace width is enlarged

to the width of the BGA

pad for a length of 1-2

diameters of the BGA pad.

The BGA pads enhanced

by wide traces are in the 3

x 3 corner array. Electrical

consideration may take

priority over trace

widening where

necessary.

Blue – BGA Pad

Green – Trace Routing

Pink – Solder Mask Clearance (2 mils)

Yellow - Via

BGA BALL LAYOUT IN SHAPE

AREA

Cisco Recommended Pad

Modifications

Optimized results

with “bullet”

geometry found

Largest

solderable area

Best lifetime in

drop

Failure shifted to

intermetallic

region

Universal Consortium Pad Geometry

Designed to provide additional metal at the critical

junction of the pad and trace.

Reduces solder joint stresses

Reduces risk of cracking

Improves resistance to thermal shock

Improves resistance to impact shearing.

Use of teardrops with NSMD pads provides additional

ball-to-land contact area

Makes them more mechanically robust.

Tear Drop Pads

To date, no published evidence on the topic

Industry quotes: “Filled vias can increase the likelihood of solder cracking,

because it is a more rigid foundation, but I would think it would do better for pad cratering in comparison to a pad with no filled via”, Craig Hillman, DfR Solutions

“We haven’t specifically used the AE technique on BGAs with via under pad, but there is circumstantial evidence that the vias have a reinforcing effect that should help to stop the crack. Interesting subject for future study.” Anurag Bansal, Cisco

“I don't have any work that provides insight. I have seen images of pad crater cracks that have propagated through the microvia in someone's paper but it was not filled. Intuitively I would expect better resistance from a filled microvia but I don't have any data. “ John McMahon, Celestica

Filled Vias in Pads & Impact on

Cratering

Areas of highest risk

In Circuit Test

Mechanical Assembly

Depanelization

Connector Insertion

Heat sink attach

Module assembly

Look for ways to assess and minimize flexure and strain throughout the process

Assembly Process Control is Key!

Corner Glue

Excessive shock, vibration, or bending will cause PCB

pad cratering.

When design rules are not sufficient, corner glue is the

second line of defense to combat this failure mechanism.

Pre-Reflow

Post-Reflow

Pre-Reflow Adhesive Process

*

BGA

Too Little Too Much Correct

Target approximately 50% of BGA substrate height

Corner Glue – Post Reflow Process To be most effective, length of bead should

be 4-6 solder balls in length.

Corner Glue – Mechanical Improvement

Post-Reflow Glue Failure Mech

Ref: M. Kochenowski et. al., Improved Shock and Bend with Corner Glue, SMTA, Chicago, 2006.

Review/perform ICT strain evaluation at fixture supplier and in process:

500 us rule of thumb, critical for BTCs, CSP, and BGA packages

To reduce the pressures exerted on the PCB:

First and simplest solution: reduce the probe forces when possible.

Secondly, optimize position of the fingers/stoppers to control probe forces.

Often difficult to achieve. Mechanically, the stoppers must be located exactly under the pressure fingers to avoid the creation of shear points

ICT Strain: Fixture & Process Analysis


Fixture revalidation should be periodically performed

When probes are replaced

When fixture is altered Supports are moved

Rewiring is done

ICT Strain: Fixture & Process

Analysis

82

http://www.rematek.com/download_center/board_stre

ss_analysis.pdf


Example of Failure in Test Fixture at 32G, 270ips 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

A X 3 4 4 4 4 4 3 3 XB 3 3 3 4 4 4 3C 3 3 3 4 3D 4 4 4 4E 4 4 4F 4G 4HJKLMNPRTUVW 4Y 4

AA 4AB 4 4 4 4AC 4 4 4 4AD 3 4 4 3 3 3AE 4 4 4 3 3 3AF X 3 4 4 4 4 4 3 X

Brd 001X ICH Dye and Pry fracture indications

Laminate Relationship to Cratering

M. A

hm

ad,

et a

l.,

Cis

co,

Apex,

2009.

Module 6: Prevention &

Future Work

Copper clad high Tg, CTE Z axis of 19

ppm/deg C. Fully cured dielectric.

Used with standard prepregs

Approved to IPC Slash sheet 4204/25

Integral Technology Zeta Cap –

What is it?

Requires no special processing or equipment. It simply replaces the outerlayer foil in the PCB construction.

When used as a cap layer (see below) it becomes the interface between the copper pad and the rest of the PCB.

The more pliant cap is intended to prevent or block fractures and protect copper connections (traces) to the pad.

How does Zeta Cap work?

Zeta

cap

Zeta Cap Evaluations Mechanical

Evaluations, Drop

Testing:

“Of the materials

evaluated and

described as lead-free

compatible, the

ZetaCap is the clear

favorite.”

Results courtesy of

Universal AREA

Consortium

Post- Drop Test Images

Zeta Cap Evaluations Thermal Cycling Evaluations:

0 to100C and -40C to 225C cycling

“For group A materials evaluated, ZetaCap appears to be the best.”

“All of our examples to date indicate that the ZetaCap results in better performance with respect to time to first failure and generally N63.2.”

Results courtesy of Universal AREA (Advanced Research & Electronic Activity) Consortium

Eliminate potential bed of nails damage by: Identifying components on the circuit card that

could experience cracking or failure during bed of nails testing.

Prior to the ICT, the designer can optimize the process: Change test points

Change pogo pin pressure, or

Add /move board supports

Sherlock analysis is component-specific, allowing for more precise identification of at-risk areas

Sherlock Software

Designers can identify potential bed of nails damage early in the layout process, before a bed of nails tester is ever designed

Allows for tradeoff analyses, saving costly board damage and redesign.

Sherlock – Automated Design

Analysis Software

Pad Cratering is an increasingly common failure mode Catastrophic and non-reworkable

Easy to avoid detection and difficult to diagnose Partial cracks riskiest since they escape and

expand in the field

Multiple paths for mitigation but few for true prevention

No hard, fast rules for avoidance Dependent on design, component, layout,

process…

Pad Cratering Conclusions

Maintain awareness in design & manufacturing

Evaluate each and every design

No one size fits all criteria but some “rules of thumb”

Validate results with destructive cross-sections

Test & Control are key

Use multiple testing strategies to maximize success at finding and preventing failures

Pad Cratering Recommendations

Boundary Scan: A Practical Approach http://www.ems007.com/pages/zone.cgi?a=83457

Impact Performance of Microvia and Buildup Layer Materials and Its Contribution to Drop Test Failures, Dongji Xie*, Jonathan Wang**, Him Yu+, Dennis Lau+ and Dongkai Shangguan* *Flextronics International

METHODOLOGY TO CHARACTERIZE PAD CRATERING UNDER BGA PADS IN PRINTED CIRCUIT BOARDS, Originally published in the Proceedings of the Pan Pacific Microelectronics Symposium, Kauai, Hawaii, January 22 – 24, 2008.

COMPREHENSIVE METHODOLOGY TO CHARACTERIZE AND MITIGATE BGA PAD CRATERING IN PRINTED CIRCUIT BOARDS, Originally published in SMTAnews & Journal of Surface Mount Technology, January –March 2009, Vol. 22, Issue 1.

VALIDATED TEST METHOD TO CHARACTERIZE AND QUANTIFY PAD CRATERING UNDER BGA PADS ON PRINTED CIRCUIT BOARDS Originally published at the IPC/APEX 2009 Conference held in Las Vegas, NV, April 2009.

Board Level Failure Analysis of Chip Scale Package Drop Test Assemblies, Nicholas Vickers, Kyle Rauen, Andrew Farris, Jianbiao Pan, Cal Poly State University.

Assessment of PCB Pad Cratering Resistance by Joint Level Testing Brian Roggeman1, Peter Borgesen1 Brian Roggeman1, Peter Borgesen1, Jing Li2, Guarav Godbole2, Pushkraj Tumne2, K. Srihari2, Tim Levo3, James Pitarresi3

1Unovis-Solutions, Binghamton, NY 13902, Jing Li2, Guarav Godbole2, Pushkraj Tumne2, K. Srihari2, Tim Levo3, James Pitarresi3 1Unovis-Solutions, Binghamton, NY 13902

MANUFACTURING QUALIFICATION FOR THE LATEST GAMING DEVICE

WITH Pb-FREE ASSEMBLY PROCESS Ding Wang Chen, Ph.D., Alex Leung, and Alex Chen Celestica China and Celestica Corporate Technology Suzhou, China; Dongguan, China; and Toronto, Canada

References

http://www.ems007.com/pages/zone.cgi?a=83457



Pad Cratering Evaluation of PCB Dongji Xie*, Ph.D., Dongkai Shangguan*, Ph.D. and Helmut Kroener**, *FLEXTRONICS, San Jose, CA, ** Multek, Schongau, Germany

Pad Cratering: Assessing Long Term Reliability Risks, Denis Barbini, Ph.D., AREA Consortium

A New Approach for Early Detection of PCB Pad Cratering Failures, Anurag Bansal, Gnyaneshwar Ramakrishna and Kuo-Chuan Liu, Cisco Systems, Inc., San Jose, CA

Validated Test Method to Characterize and Quantify Pad Cratering Under Bga Pads on Printed Circuit Boards, Mudasir Ahmad, Jennifer Burlingame, Cherif Guirguis, Technology and Quality Group, Cisco Systems, Inc.

COMPREHENSIVE METHODOLOGY TO CHARACTERIZE AND MITIGATE BGA PAD CRATERING IN PRINTED CIRCUIT BOARDS Mudasir Ahmad, Jennifer Burlingame, and Cherif Guirguis, Technology and Quality Group, Cisco Systems, Inc.

A New Method to Evaluate BGA Pad Cratering in Lead-Free Soldering, Dongji Xie, Ph.D.*, Clavius Chin, Ph.D.**, KarHwee Ang**, Dennis Lau+ and Dongkai Shangguan, Ph.D. *Flextronics International.

The Application of Spherical Bend Testing to Predict Safe Working Manufacturing Process Strains, John McMahon P.Eng, Brian Gray P.Eng, Celestica.

Investigation of Pad Cratering in Large Flip-Chip BGA using Acoustic Emission, Anurag Bansal, Cherif Guirguis and Kuo-Chuan Liu, Cisco Systems, Inc.,.

PAD CRATERING: THE INVISIBLE THREAT TO THE ELECTRONICS INDUSTRY, Presented by Jim Griffin, OEM Sales & Marketing Manage, Integral Technology

Pad Cratering Test Methods: AComparative Look Brian Roggeman & Wayne Jones, AREA Consortium

VALIDATED TEST METHOD TO CHARACTERIZE AND QUANTIFY PAD CRATERING UNDER BGA PADS ON

PRINTED CIRCUIT BOARD, Mudasir Ahmad, Jennifer Burlingame, Cherif Guirguis Component Quality and Technology Group, Cisco Systems, Inc

References

Instructor Biography • Cheryl Tulkoff has over 22 years of experience in electronics manufacturing with an

emphasis on failure analysis and reliability. She has worked throughout the electronics

manufacturing life cycle beginning with semiconductor fabrication processes, into printed

circuit board fabrication and assembly, through functional and reliability testing, and

culminating in the analysis and evaluation of field returns. She has also managed no clean

and RoHS-compliant conversion programs and has developed and managed comprehensive

reliability programs.

• Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech. She is a

published author, experienced public speaker and trainer and a Senior member of both ASQ

and IEEE. She has held leadership positions in the IEEE Central Texas Chapter, IEEE WIE

(Women In Engineering), and IEEE ASTR (Accelerated Stress Testing and Reliability)

sections. She chaired the annual IEEE ASTR workshop for four years and is also an ASQ

Certified Reliability Engineer.

• She has a strong passion for pre-college STEM (Science, Technology, Engineering, and

Math) outreach and volunteers with several organizations that specialize in encouraging pre-

college students to pursue careers in these fields.

Contact Information

Questions?

Contact Cheryl Tulkoff,

[email protected],

512-913-8624

[email protected]

www.dfrsolutions.com

Connect with me in LinkedIn as well!

http://www.dfrsolutions.com/

Pad Cratering: Prevention, Mitigation and Detection Strategies

Technology

Transcript of Pad Cratering: Prevention, Mitigation and Detection Strategies