Packaging Roadmap:

The impact of miniaturization

Juergen Wolf, Fraunhofer IZM for

Bill Bottoms/Bill Chen-Chairs

ProductronicaNovember 14, 2007

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MooreMoore’’s Law 40 Year Trends Law 40 Year Trend1,000,000 times improvement 1,000,000 times improvement

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Interacting with people          and environmentNon‐digital content  System‐in‐Package (SiP)

Beyond CMOS

Information Processing               Digital content System‐on‐Chip (SOC)

BiochipsFluidics

SensorsActuators

HVPower

Analog/RF Passives

More than Moore :          Functional Diversification

130nm

90nm

65nm

45nm

32nm

Λ...22nm

Mor

e M

oore

: Sc

alin

g

Combine SOC & SiP :

Higher Valu

e Sys

tem

Baseline CMOS:              CPU, Memory, Logic

Moore’s Law ScalingMoore’s Law Scalingalone can not maintain the Pace of Progress alone can not maintain the Pace of Progress

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Packaging is now a limiting factorbut its an enabler for More than

Moore

Packaging is now a limiting factorPackaging is now a limiting factorbut its an enabler for More than but its an enabler for More than

MooreMoorePackaging has become the limiting element in system

cost and performance The Assembly and packaging role is expanding to

include system level integration functionsAs traditional Moore’s law scaling become more

difficult innovation in assembly and packaging can take up the slack.

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The Pace of Change in Packaging isThe Pace of Change in Packaging isAcceleratingAccelerating

As traditional CMOS scaling nears it natural limits other technologies are needed to continue progressThis has resulted in an increase in the pace of innovation.Many areas has outpaced ITRS Roadmap forecasts. Among these are:– Wafer thinning and handling of thinned wafers/die– Wafer level packaging– Incorporation of new materials– 3D integrationThe consumerization of electronics is the primary driving force.

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New MaterialsNew Materials

In this decade most if not all packaging materials will change due to changing functional and regulatory requirements–Bonding wire–Molding compounds–Underfill–Thermal interface materials–Die attach materials–Substrates

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Definition for SystemDefinition for System--inin--PackagePackage

“System in Package is characterized by any combinationof more than one active electronic component of different functionality

plus optionally passives and other devices like MEMSor optical components assembled preferred into a single standard

packagethat provides multiple functions

associated with a system or sub-system.”

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Horizontal P lac ement

S tac kedS truc ture

Interpos er Type

Interpos er‐les s  Type

Wire Bonding  Type F lip  C hip  Type

Wire Bonding  Type

Wire B onding  +F lip  C hip  Type F lip  C hip  Type

Terminal Through  Via Type

Embedded  S truc tureC hip(WL P ) Embedded  +  C hip  on  S urface Type

3D  C hip  EmbeddedType

WL P  Embedded  +  C hip  on  S urface Type

System in Package (SiP) ApproachesSystem in Package (SiP) Approaches

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SiP SiP -- Situation AnalysisSituation Analysis

Market: In 2004, 1.89 Billion SiPs were assembled. By 2008, this number is expected to reach 3.25 Billion, growing at an average rate of about 12% per year.

Technology: SiP applications have become the technology driver for small components, packaging, assembly processes and for high density substrates.

Growth: System-in-Package (SiP) has emerged as the fastest growing packaging technology segment although still representing a relatively small percentage of the unit volume.

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3D 3D -- SiP RequirementsSiP Requirements

System-in-a-Package Requirements Year of Production 2007 2008 2009 2010 2011 2012 2013 2014 2015

Number of terminals—low cost handheld700 800 800 800 800 800 800 800 800

Number of terminals—high performance (digital) 3050 3190 3350 3509 3684 3860 4053 4246 4458

Number of terminals—maximum RF 200 200 200 200 200 200 200 200 200Low cost handheld / #die / stack* 7 8 9 10 11 12 13 14 14high performance / die / stack 3 3 3 4 4 4 5 5 5Low cost handheld / #die / SiP 8 8 9 11 12 13 14 14 14high performance / #die / SiP 6 6 6 7 7 7 8 8 8Minimum TSV pitch 10.0 8.0 6.0 5.0 4.0 3.8 3.6 3.4 3.3TSV maximum aspect ratio** 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0TSV exit diameter(um) 4.0 4.0 3.0 2.5 2.0 1.9 1.8 1.7 1.6TSV layer thickness for minimum pitch 50 20 15 15 10 10 10 10 8Minimum component size (micron) 1005 600x300 600x300 400x200 400x200 400x200 200x100 200x100 200x100

System-in-a-Package Requirements Year of Production 2007 2008 2009 2010 2011 2012 2013 2014 2015

Number of terminals—low cost handheld700 800 800 800 800 800 800 800 800

Number of terminals—high performance (digital) 3050 3190 3350 3509 3684 3860 4053 4246 4458

Number of terminals—maximum RF 200 200 200 200 200 200 200 200 200Low cost handheld / #die / stack* 7 8 9 10 11 12 13 14 14high performance / die / stack 3 3 3 4 4 4 5 5 5Low cost handheld / #die / SiP 8 8 9 11 12 13 14 14 14high performance / #die / SiP 6 6 6 7 7 7 8 8 8Minimum TSV pitch 10.0 8.0 6.0 5.0 4.0 3.8 3.6 3.4 3.3TSV maximum aspect ratio** 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0TSV exit diameter(um) 4.0 4.0 3.0 2.5 2.0 1.9 1.8 1.7 1.6TSV layer thickness for minimum pitch 50 20 15 15 10 10 10 10 8Minimum component size (micron) 1005 600x300 600x300 400x200 400x200 400x200 200x100 200x100 200x100

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Many variations of SiP packageMany variations of SiP package interconnect are in interconnect are in use or in development todayuse or in development today

POP (WB Type)

POP (FC Type + Interposer)

POP (Film Type)

POP (only for Memory)

PIP - Molded PIP - Spacer

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3D Stacked Die Package3D Stacked Die Package

Samsung TSV

TSV of Tezzaron

TSV of Ziptronix

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● ● ● ● ● ● ● ●

● ● ● ●

Substrate thickness: 0.16

Ball diameter: 0.4 mmBall pitch: 0.8 mm

1.0

Mold resin thickness on top of die: 0.10 mm

Die attach thickness 0.015

TSV

0.025mm

Embedded

Typical SiP in 2010Typical SiP in 2010

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Advantages:

extremely thin packaging

use of established PCB processes and materials

capability for 3D component stacking

very short interconnect between chips and substrate

Embedding of Thin Chips into Build-up Layers of PCB

chip RCC

core substrate adhesive

chip RCC

core substrate adhesive

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via to embedded chip

• generation of electrical contact to embedded chips by via metallization• chemical cleaning and dielectric activation by Pd solution• first metallization by electroless Cu deposition• deposition of thick Cu by electroplatng (DC or pulse plating)

Chip In Polymer - Via Metallization

Cu conductors to embedded chip

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Reliability Tests of Single Embedded Chips

• 2.5x2.5 mm² chips, 50 µm thickness, • 80µm RCC• chips bonded on 650 µm FR4 core substrate

Temperature storagecondition 125 °C

1000 hours passed

Thermal Cyclingcondition -55°C / +125 °C

2000 cycles passed

Humidity storagecondition 85 °C / 85 % RH

2000 hours passed

Jedec Level 3humidity soak, 192h @ 30°C/60% RH followed by 3 reflows peak temp. 260 °C (Pb-free)

test passed cross-section after Jedec level 3 test• no delamination after 3rd reflow• interconnection to chip survived

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Chip in Polymer - Realized Devices

process development module thermal test module chip stacking module

coreless MOSFET package chip card module sensor module

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3D Chip in Polymer

embedding of 4 layers of chips on a 500 µm FR4 core

module design first sample

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Si Interposer for WLSi Interposer for WL--SiPSiP

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Advanced PackagingAdvanced PackagingEmbedded Wafer Level Ball Grid ArrayEmbedded Wafer Level Ball Grid Array

Idea for an Embedded WLB:an Universal Package SolutionIdea for an Embedded WLB:Idea for an Embedded WLB:

an Universal Package Solutionan Universal Package Solution

Fan-out area

Fan-out area

Interconnects

Redistribution layer

Chip

courtesy of

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Infineons Approach to tackle the Interconnect GapInfineons Approach to tackle the Interconnect Gap

M. Brunnbauer et. al. EPTC 2006

Using mold compound to carry the fan-out areaand to protect the chip back-side

courtesy of

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Fraunhofer´s TCI Fraunhofer´s TCI -- ApproachApproach

• FE compatible processes• high interconnect density• short distance between neighboured devices• bumpless interconnects• passive device integration (R, L, C)• Impedance controlled wiring• multilayer 3D approach• stackable systems

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3 D WL Integration with TSV3 D WL Integration with TSV

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Process Technology needed:

• Robust and precise thinning process

• Handling concept for thin Si wafer

• ICVs (Inter-Chip-Vias) for electrical interconnects through thinned Si

- Deep via etching

- Deep via dielectric isolation

- Deep via metal filling

• Suitable high efficient bonding process

• Wafer level Assembly, Underfilling

• Encapsulation

RequirementsRequirements for 3D WL System Integration w TSVfor 3D WL System Integration w TSV

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Circuit Circuit

ViaPrior to CMOS

Via Post to CMOS

Grinding last(Via First)

Grinding First (Via Last)

•Filling mat. Limited: Poly Si•Isol. Thermal oxide•Small•Narrow annular trenches•High aspect ratio --> low ER

•Low aspect ratio --> High ER•Dedicated Si surface•Additional mask level

•Low aspect ratio --> High ER•Etching of stacked oxide(s)•Thin wafer handling

Si

SiO2

Via FormationVia Formation

Source: Alcatel

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Via Formation Via Formation –– Via Metal FillingVia Metal Filling

CVD of - copper- tungsten- TiN

Electroplating of - copper

1.0 µm 3.5 µm 5 µm 10 µm .... 100 µm Via-Diameter

Process for filling

70 µm .... 100 µm Via-Depth7:1 1:1 Aspect Ratio

10 µm10:1 3:1 2:1 ..

PVD of Seedlayer- Ti:W / Cu&

Electroplating of - copper

CVD of Seedlayer- tungsten&

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ICV-Dimensions: 3 µm x 10 µm x 50 µm

SACVD TEOSTiN CVDW CVD

TSV TSV -- FillingFilling

18 µm

35 µm

63 µ

m

CVD - W CVD - Cu ECD - Cu

Size: diam. 18/35 µm, depth> 60 µm; Seed layer Ti.W/Cu

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EMC-3D consortium created for the development of cost-effective 3D Through-Silicon-Via interconnect

Equipment providers, materials companies and researchers join inan international consortium to address complex integration of

Through-Silicon-Via (TSV) 3D chip interconnect.

EMC3D (Semiconductor 3D Equipment and Materials Consortium) was created in September 2006 to develop a new 3D market and technology by demonstrating a cost-effective, manufacturable, stackable TSV interconnection process. TSV processes will be developed for chip integration and MEMS/sensor packaging that are based on plated metal electrodes and thinned wafers.

www.EMC3D.org.

EMCEMC--3D Consortium 3D Consortium --MissionMission

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Press Release Oct. 11Press Release Oct. 11thth, 2006, 2006

EMC-3D consortium created for the development of cost-effective 3D Thru-Silicon-Via interconnect

Equipment providers, materials companies and researchers join in an international consortium to address complex integration of Thru-Silicon-Via (TSV) 3D chip interconnect.

SALZBURG, Austria, October 11th, 2006. EMC-3D is a new consortium created to address the technical and cost issues of creating 3D interconnects using TSV technology for chip stacking and MEMS/sensors packaging. Several major equipment manufactures have joined with material companies to work with key research groups to address the issues of cost-effective manufacturing and integration. Equipment companies initiating the consortium are Alcatel, EV Group, Semitool and XSiL. NXP acts as technical advisory .

Associate research members include Fraunhofer IZM, SAIT (Samsung Advanced Institute of Technology), KAIST (Korea Advanced Institute of Science and Technology) and TAMU (Texas A&M University). Material members include Rohm and Haas, Enthone, and AZ with wafer service support from Isonics.

The consortium will develop processes for creating micro vias between 5 and 30um on thinned 50um 300mm wafers using both via-first and via-last techniques. Major processes being integrated into the EMC-3D program are via etch and laser drill, insulator/barrier/seed deposition, micro via patterning with RDL capabilities, high aspect ratio Cu plating, carrier bonding, sequential wafer thinning, backside insulator/barrier/seed deposition, backside lithography, backside contact metal plating, chip-to-wafer placement and attach, and dicing. In addition, wafer-to-wafer attach, dicing and de-bonding will also be demonstrated. Cost of ownership goal for the integrated 3D process is $200usd per wafer.

EMCEMC--3D Consortium3D Consortium

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EMCEMC--3D 3D -- Industrial ConsortiumIndustrial Consortium

Equipment Materials Technology

Founders

Technical Advisor

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3D Integration Roadmap3D Integration Roadmap

CMOSImage Sensor

CMOSImage Sensor

CIS

Organic Interposer

CIS

Organic Interposer

CISLogic

Dram

Organic Interposer

CISLogic

Dram

Organic Interposer

High Speed

FlashFlashFlashFlashFlashFlashFlashFlash

FlashFlashFlashFlashFlashFlashFlashFlashFlashFlashFlashFlashFlashFlashFlashFlash

CIS

Si InterposerDSP

CISCIS

Si InterposerDSP

MemoryMemory

Si InterposerDram

Si InterposerDram

Via : 40umHole : <100

t=200um

Via : 40umHole : <100

t=200um

Via : 5-10umHole : >100K Logic

DramDram

Logic

Logic

DramDram

Logic

DramDram

Logic

Via : >20um by Laser Hole : <100t : <50um

Via : 1-5umHole : <1000t : 20-50um

MCP

POP

Multi Function

LogicLogic

Multi function OCMulti function OC

NAND

DRAM

SensorLogicAnalog

RFDRAMMPU

SensorLogicAnalog

RFDRAMMPU

CMOS image sensors, memories (NAND, DRAM & NOR + Logic are

requiring 3D stacking with TSVs (vias sizes are depending upon the application)

2006 2007 2008 2009 2010 2011 2012 2013 20142005 2006 2007 2008 2009 2010 2011 2012 2013 20142005

Thin waferMulti-layer

Small viasVias density

t=>50um

t=<200um

Source:Yole

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InterconnectsInterconnects

Interconnect requirements may be satisfied bywave guide optical solutions

Low temperature bonding process, e.g. Nano InterconnectsThin interconnect and small pitchRework

Small and thin active deviceSelf assembly

Low k ILD may require Improved underfill or compliant I/O connections

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Major ChallangesMajor Challanges to be Adressed by Packagingto be Adressed by Packaging

SIP - Chip Package Co-Design (all types of packages)electrical - thermal – thermo-mechanical

Thermal Management - Integrated cooling concepts

Testing - access, cost

Low temperature processing vs. High temperature reliability

Environmental friendly material and processes

Cost targets for new package

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SummarySummary

The pace of progress for the Semiconductor Industry will accelerate as

we enter the era of “More than Moore”3 dimensional integration

New device architectures

Incorporation of Nano materials

System in Package will be the solution of choice for a majority of products

3D integration concepts (different types) drive system performance, miniaturization and cost reduction …

Design for Reliability (construction, process, material, application)

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New Edition 2007 ITRS A&PNew Edition 2007 ITRS A&P

New Release in Dec. 2007New Release in Dec. 2007

www.itrs.orgwww.itrs.orgwww.inemi.orgwww.inemi.org

…… More tables, numbers, detailsMore tables, numbers, details

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www.inemi.orgEmail contacts:

Jim McElroy jmcelroy@inemi.org

Bob Pfahlbob.pfahl@inemi.org