Overview - guc-asic.com
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www.guc-asic.com 2019Q3 GUC HBM2(E) Controller and PHY IP Overview GUC HBM2(E) IP is a complete solution for SoC design targeting high bandwidth applications such as AI, HPC, data centers and networking. GUC HBM2(E) IP is fully compliant to JEDEC JESD235B. With fully optimized hardmacro PHY and manufactured on TSMC process technologies, GUC HBM2 PHY is currently silicon proven at up to 2.4 Gbps, making it the industry highest performance HBM2 PHY. Meanwhile the upcoming GUC HBM2E is targeting to achieve 3.2Gbps. Along with the eye-catching performance, GUC HBM2(E) PHY has the most optimal power/area balance and cost effectiveness among all HBM2(E) IP vendors. GUC provides HBM2(E) IP for a wide range of advanced process nodes including 16nm, 12nm, 7nm and 5nm. Essential to HBM2(E) IP solution, GUC is expert in TSMC HBM CoWoS flow, implementation and testing. GUC HBM2 IP has been proven in testchips and 2.5D IC packaging with dual sourcing (Samsung and Hynix). GUC HBM2(E) GUC provides HBM2(E) IP and 2.5D package/PCB design service with precise SI/PI to achieve targeted system performance cost effectively GUC HBM2(E) support memory BIST, internal loopback test, IO DC connectivity test and lane repair GUC HBM2(E) performance and process correlation is constantly monitored Reliable Production User Friendly GUC HBM2(E) equips with auto trainings to save evaluation and boot up time Cost Effective Quality
Transcript of Overview - guc-asic.com
GUC HEADQUARTERS, HSINCHU, TAIWAN [email protected]
GUC TAIPEI [email protected]
GUC NORTH [email protected]
GUC KOREA+82-10-4590-0975 [email protected]
GUC EUROPE [email protected]
5nm5nm
www.guc-asic.com
5nm
www.guc-asic.com
2019Q3
GUC HBM2(E) Controller and PHY IP
Overview
GUC HBM2(E) IP is a complete solution for SoC design targeting high bandwidth applications such as AI, HPC, data centers and networking. GUC HBM2(E) IP is fully compliant to JEDEC JESD235B. With fully optimized hardmacro PHY and manufactured on TSMC process technologies, GUC HBM2 PHY is currently silicon proven at up to 2.4 Gbps, making it the industry highest performance HBM2 PHY. Meanwhile the upcoming GUC HBM2E is targeting to achieve 3.2Gbps. Along with the eye-catching performance, GUC HBM2(E) PHY has the most optimal power/area balance and cost effectiveness among all HBM2(E) IP vendors.
GUC provides HBM2(E) IP for a wide range of advanced process nodes including 16nm, 12nm, 7nm and 5nm. Essential to HBM2(E) IP solution, GUC is expert in TSMC HBM CoWoS flow, implementation and testing. GUC HBM2 IP has been proven in testchips and 2.5D IC packaging with dual sourcing (Samsung and Hynix).
GUC HBM2(E)
GUC provides HBM2(E) IP and 2.5D package/PCB design service with precise SI/PI to achieve targeted
system performance cost effectively
GUC HBM2(E) support memory BIST, internal loopback test, IO DC connectivity test and lane repair
GUC HBM2(E) performance and process correlation is constantly monitored
ReliableProduction
User Friendly
GUC HBM2(E) equips with auto trainings to save evaluation and
boot up time
CostEffective
Quality
www.guc-asic.com
2019Q3
GUC HBM2(E) Controller IP
High Bandwidth Memory (HBM) DRAM controller, compliant with JESD235B
Support pseudo channel mode with 64DQ per pseudo channel
Support AXI 4.0 port
Support DFI 1:1 (DFI 1:2 is supported through a wrapper) for HBM2
Support DFI 1:2 for HBM2E
Support BL4
Support DQ/AC bus parity
Support DBI, DM, and ECC
Support single bank refresh
Support self-refresh
Support programmable mapping from AXI address to bank group, bank, row, and column
Support AXI read interleaving
Support QoS
Support BIST
HBM controller and PHY interfacing to HBM DRAM
MemoryController
HBM PHY IPMLB RTL Module
Miscellaneous Logic Block
( MLB)
HBM PHY IP(Hard Macro)
HBM DRAM
Loopback Test Mode
I / OPAD
PHY Register
PLL
PLL
Training Logic
PHY Registe Settings
HB
M D
RA
MIn
terface
DFI Interface
DFT(JTAG)
System
I2C
Intern
alIn
terface
MemoryController
HBM PHY IP
GUC HBM2(E) PHY IP
Support HBM2 for TSMC N16/N12/N7, up to 2.4Gbps with CoWos technology
Support HBM2E for TSMC N7/N5, up to 3.2Gbps with CoWos technology
Complete HBM IP solution including controller, PHY and I/O
Support IO PVT (process, voltage and temperature) automatic calibration function
Support multiple output driving capacities (1.5mA, 3mA, 4.5mA, 6mA, 9mA, 12mA, 15mA and 18mA)
Compliant with HBM DRAM standard (JEDEC JESD235B)
HBM2(E) 2.5D IC Package Side View
HBM2
SoC
HBM2
Heat Sink
SOCMCBIST
MBIST
Stiffe
ne
r
Substrate
Interposer
SoC HBM2
Interposer
TV-1 Substrate/Package View TV-2 Substrate/Package View
Stiffe
ne
r
GUC HEADQUARTERS, HSINCHU, TAIWAN [email protected]
GUC TAIPEI [email protected]
GUC NORTH [email protected]
GUC KOREA+82-10-4590-0975 [email protected]
GUC EUROPE [email protected]
www.guc-asic.com
2019Q3
GUC HBM/DDR/ONFI IP Portfolio
IP NAME MAX SPEED (Mbps) PROCESS STATUS IP CODE
HBM2E PHY 3200 N5 2020/ Q2 IGAHBMY01A
HBM2E PHY 3200 N7 2019 / Q4 IGAHBMX02A
HBM2 PHY 2400 N7 ● IGAHBMX01A
HBM2 PHY 2000 CLN12FFC/16FFC ● IGAHBMV03A
HBM2 PHY 2000 CLN16FF+ ● IGAHBMV02A
HBM2E Ctrl 3200 All 2019 / Q4 IGDHBM003A
HBM2 Ctrl 2400 All ● IGDHBM002A
(LP)DDR3/4 PHY (LP)DDR3 – 2133(LP)DDR4 – 4266 N7 Planning Planning
(LP)DDR3/4 PHY (LP)DDR3 – 2133(LP)DDR4 – 4266
CLN12FFC16FFC 2019 / Q4 IGADDRV10A
(LP)DDR3/4 PHY (LP)DDR3 – 2133(LP)DDR4 – 3200
CLN12FFC16FFC
● IGADDRV09A
LPDDR4(X) PHY LPDDR4(X) – 3200 CLN12FFC16FFC
● IGADDRV07A
(LP)DDR3/4 PHY (LP)DDR3 – 2133(LP)DDR4 – 2666 CLN28HPC+ ● IGADDRT12A
(LP)DDR3/4 PHY (LP)DDR3 – 1866DDR4 – 1866 CLN40LP ● IGADDRS06A
(LP)DDR3/4 Ctrl (LP)DDR3 – 2133(LP)DDR4 – 4266 All ● IGDDDR005A
ONFI 4.1 PHY 1200 CLN16FFCCLN12FFC
● IGAFLHV01A
ONFI 4.1 IO 1200 CLN16FFC ● IGIFLHV01A
ONFI 4.0 IO 800 CLN28HPC+ ● IGIFLHT07A
(*) Customization is available, if not in the above table.
● Production ● Pilot
