ABSTRACT

INTRODUCTION

Floating point numbers are one possible way of representing real numbers in binary format; the

IEEE 754 standard presents two different floating point formats, Binary interchange format and

Decimal interchange format. Multiplying floating point numbers is a critical requirement for

DSP applications involving large dynamic range. This paper focuses only on single precision

normalized binary interchange format. Fig. 1 shows the IEEE 754 single precision binary format

representation; it consists of a one bit sign (S), an eight bit exponent (E), and a twenty three bit

fraction (M or Mantissa). An extra bit is added to the fraction to form what is called the

significand1. If the exponent is greater than 0 and smaller than 255, and there is 1 in the MSB of

the significand then the number is said to be a normalized number; in this case the real number is

represented by

Figure 1. IEEE single precision floating point format

Bias = 127.

Multiplying two numbers in floating point format is done by 1- adding the exponent of the two

numbers then subtracting the bias from their result, 2- multiplying the significand of the two

numbers, and 3- calculating the sign by XORing the sign of the two numbers. In order to

represent the multiplication result as a normalized number there should be 1 in the MSB of the

result (leading one).Floating-point implementation on FPGAs has been the interest of many

researchers. In [2], an IEEE 754 single precision pipelined floating point multiplier was

implemented on multiple FPGAs (4 Actel A1280). In [3], a custom 16/18 bit three stage

pipelined floating point multiplier that doesn’t support rounding modes was implemented. In [4],

a single precision floating point multiplier that doesn’t support rounding modes was

implemented using a digit-serial multiplier: using the Altera FLEX 8000 it achieved 2.3 MFlops.

In [5], a parameterizable floating point multiplier was implemented using the software-like

language Handel-C, using the Xilinx XCV1000 FPGA; a five stages pipelined multiplier

achieved 28MFlops. In [6], a latency optimized floating point unit using the primitives of Xilinx

Virtex II FPGA was implemented with a latency of 4 clock cycles. The multiplier reached a

maximum clock frequency of 100 MHz.

II. FLOATING POINT MULTIPLICATION ALGORITHM

As stated in the introduction, normalized floating point numbers have the form of Z= (-1S) * 2

(E - Bias) * (1.M). To multiply two floating point numbers the following is done:

1. Multiplying the significand; i.e. (1.M1*1.M2)

2. Placing the decimal point in the result

3. Adding the exponents; i.e. (E1 + E2 – Bias)

4. Obtaining the sign; i.e. s1 xor s2

5. Normalizing the result; i.e. obtaining 1 at the MSB of the results’ significand

6. Rounding the result to fit in the available bits

7. Checking for underflow/overflow occurrence

Consider a floating point representation similar to the IEEE 754 single precision floating point

format, but with a reduced number of mantissa bits (only 4) while still retaining the hidden ‘1’

bit for normalized numbers:

A = 0 10000100 0100 = 40, B = 1 10000001 1110 = -7.5

To multiply A and B

1. Multiply significand: 1.0100 × 1.1110____________

00000 10100 10100 10100 10100 ____________________ 1001011000

2. Place the decimal point: 10.01011000

3. Add exponents:

10000100 + 10000001 _______________ 100000101The exponent representing the two numbers is already shifted/biased by the bias value (127) and

is not the true exponent; i.e. EA = EA-true + bias and EB = EB-true + bias And

EA + EB = EA-true + EB-true + 2 bias

So we should subtract the bias from the resultant exponent otherwise the bias will be added twice. 100000101

- 01111111 ________________ 10000110

4. Obtain the sign bit and put the result together:1 10000110 10.01011000

5. Normalize the result so that there is a 1 just before the radix point (decimal point). Moving the

radix point one place to the left increments the exponent by 1; moving one place to the right

decrements the exponent by 1.

1 10000110 10.01011000 (before normalizing)

1 10000111 1.001011000 (normalized)

The result is (without the hidden bit):

1 10000111 00101100

6. The mantissa bits are more than 4 bits (mantissa available bits); rounding is needed. If we

applied the truncation rounding mode then the stored value is: 1 10000111 0010.

In this paper we present a floating point multiplier in which rounding support isn’t implemented.

Rounding support can be added as a separate unit that can be accessed by the multiplier or by a

floating point adder, thus accommodating for more precision if the multiplier is connected

directly to an adder in a MAC unit. Fig. 2 shows the multiplier structure; Exponents addition,

Significand multiplication, and Result’s sign calculation are independent and are done in parallel.

The significand multiplication is done on two 24 bit numbers and results in a 48 bit product,

which we will call the intermediate product (IP). The IP is represented as (47 downto 0) and the

decimal point is located between bits 46 and 45 in the IP. The following sections detail each

block of the floating point multiplier.

Figure 2. Floating point multiplier block diagram

HARDWARE OF FLOATING POINT MULTIPLIER

A. Sign bit calculation

Multiplying two numbers results in a negative sign number

iff one of the multiplied numbers is of a negative value. By the

aid of a truth table we find that this can be obtained by XORing

the sign of two inputs.

B. Unsigned Adder (for exponent addition)

This unsigned adder is responsible for adding the exponent of the first input to the exponent of

the second input and subtracting the Bias (127) from the addition result (i.e. A_exponent +

B_exponent - Bias). The result of this stage is called the intermediate exponent. The add

operation is done on 8 bits, and there is no need for a quick result because most of the calculation

time is spent in the significand multiplication process (multiplying 24 bits by 24 bits); thus we

need a moderate exponent adder and a fast significand multiplier. An 8-bit ripple carry adder is

used to add the two input exponents. As shown in Fig. 3 a ripple carry adder is a chain of

cascaded full adders and one half adder; each full adder has three inputs (A, B, Ci) and two

outputs (S, Co). The carry out (Co) of each adder is fed to the next full adder (i.e each carry bit

"ripples" to the next full adder).

Ripple Carry Adder

The addition process produces an 8 bit sum (S7 to S0) and a carry bit (Co,7). These bits are

concatenated to form a 9 bit addition result (S8 to S0) from which the Bias is subtracted. The

Bias is subtracted using an array of ripple borrow subtractors. A normal subtractor has three

inputs (minuend (S), subtrahend (T), Borrow in (Bi)) and two outputs (Difference (R), Borrow

out (Bo)). The subtractor logic can be optimized if one of its inputs is a constant value which is

our case, where the Bias is constant (127|10 = 001111111|2).

Table shows the truth table for a 1-bit subtractor with the input T equal to 1 which we will call

“one subtractor (OS)”

The Boolean equations (2) and (3) represent this subtractor:

Figure 4. 1-bit subtractor with the input T = 1

Table II shows the truth table for a 1-bit subtractor with the input T equal to 0 which we will call

“zero subtractor (ZS)”

TABLE II. 1-BIT SUBTRACTOR WITH THE INPUT T = 0

The Boolean equations (4) and (5) represent this subtractor:

Figure 5. 1-bit subtractor with the input T = 0

Fig. 6 shows the Bias subtractor which is a chain of 7 one subtractors (OS) followed by 2 zero

subtractors (ZS); the borrow output of each subtractor is fed to the next subtractor. If an

underflow occurs then Eresult < 0 and the number is out of the IEEE 754 single precision

normalized numbers range; in this case the output is signaled to 0 and an underflow flag is

asserted.

Figure 6. Ripple Borrow Subtractor

C. Unsigned Multiplier (for significand multiplication)

This unit is responsible for multiplying the unsigned significand and placing the decimal point in

the multiplication product. The result of significand multiplication will be called the intermediate

product (IP). The unsigned significand multiplication is done on 24 bit. Multiplier performance

should be taken into consideration so as not to affect the whole multiplier’s performance. A

24x24 bit carry save multiplier architecture is used as it has a moderate speed with a simple

architecture. In the carry save multiplier, the carry bits are passed diagonally downwards (i.e. the

carry bit is propagated to the next stage). Partial products are made by ANDing the inputs

together and passing them to the appropriate adder. Carry save multiplier has three main stages:

1- The first stage is an array of half adders.

2- The middle stages are arrays of full adders. The number of middle stages is equal to the

significand size minus two.

3- The last stage is an array of ripple carry adders. This stage is called the vector merging stage.

The number of adders (Half adders and Full adders) in each stage is equal to the significand size

minus one. For example, a 4x4 carry save multiplier is shown in Fig. 7 and it has the following

stages:

1- The first stage consists of three half adders.

2- Two middle stages; each consists of three full adders.

3- The vector merging stage consists of one half adder and two full adders.

The decimal point is between bits 45 and 46 in the significand multiplier result. The

multiplication time taken by the carry save multiplier is determined by its critical path. The

critical path starts at the AND gate of the first partial products (i.e. a1b0 and a0b1), passes

through the carry logic of the first half adder and the carry logic of the first full adder of the

middle stages, then passes through all the vector merging adders. The critical path is marked in

bold in Fig. 7

Figure 7. 4x4 bit Carry Save multiplier

In Fig.

1- Partial product: aibj = ai and bj

2- HA: half adder

3- FA: full adder

D. Normalizer

The result of the significand multiplication (intermediate product) must be normalized to have a

leading ‘1’ just to the left of the decimal point (i.e. in the bit 46 in the intermediate product).

Since the inputs are normalized numbers then the intermediate product has the leading one at bit

46 or 47 1- If the leading one is at bit 46 (i.e. to the left of the decimal point) then the

intermediate product is already a normalized number and no shift is needed. 2- If the leading one

is at bit 47 then the intermediate product is shifted to the right and the exponent is Incremented

by 1. The shift operation is done using combinational shift logic made by multiplexers. Fig. 8

shows a simplified logic of a Normalizer that has an 8 bit intermediate product input and a 6 bit

intermediate exponent input.

Figure 8. Simplified Normalizer logic

UNDERFLOW/OVERFLOW DETECTION

Overflow/underflow means that the result’s exponent is too large/small to be represented in the

exponent field. The exponent of the result must be 8 bits in size, and must be between 1 and 254

otherwise the value is not a normalized one. An overflow may occur while adding the two

exponents or during normalization. Overflow due to exponent addition may be compensated

during subtraction of the bias; resulting in a normal output value (normal operation). An

underflow may occur while subtracting the bias to form the intermediate exponent. If the

intermediate exponent < 0 then it’s an underflow that can never be compensated; if the

intermediate exponent = 0 then it’s an underflow that may be compensated during normalization

by adding 1 to it. When an overflow occurs an overflow flag signal goes high and the result turns

to ±Infinity (sign determined according to the sign of the floating point multiplier inputs). When

an underflow occurs an underflow flag signal goes high and the result turns to ±Zero (sign

determined according to the sign of the floating point multiplier inputs). Denormalized numbers

are signaled to Zero with the appropriate sign calculated from the inputs and an underflow flag is

raised. Assume that E1 and E2 are the exponents of the two numbers A and B respectively;

the result’s exponent is calculated by (6)

Eresult = E1 + E2 - 127 (6)

E1 and E2 can have the values from 1 to 254; resulting in Eresult having values from -125 (2-

127) to 381 (508-127); but for normalized numbers, Eresult can only have the values from 1 to

254. Table III summarizes the Eresult different values and the effect of normalization on it.

PIPELINING THE MULTIPLIER

In order to enhance the performance of the multiplier, three pipelining stages are used to divide

the critical path thus increasing the maximum operating frequency of the multiplier.

The pipelining stages are imbedded at the following locations:

1. In the middle of the significand multiplier, and in the middle of the exponent adder (before the

bias subtraction).

2. After the significand multiplier, and after the exponent adder.

3. At the floating point multiplier outputs (sign, exponent and mantissa bits).

Fig. 9 shows the pipelining stages as dotted lines

Figure 9. Floating point multiplier with pipelined stages

Three pipelining stages mean that there is latency in the output by three clocks. The synthesis

tool “retiming” option was used so that the synthesizer uses its optimization logic to better place

the pipelining registers across the critical path.

CHAPTER-2

INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating integrated circuits by

combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s

when complex semiconductor and communication technologies were being developed. The

microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have

increased in complexity into the hundreds of millions of transistors.

Overview

The first semiconductor chips held one transistor each. Subsequent advances added more

and more transistors, and, as a consequence, more individual functions or systems were

integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten

diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic

gates on a single device. Now known retrospectively as "small-scale integration" (SSI),

improvements in technique led to devices with hundreds of logic gates, known as large-scale

integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved

far past this mark and today's microprocessors have many millions of gates and hundreds of

millions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale

integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge

number of gates and transistors available on common devices has rendered such fine distinctions

moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use.

Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are

VLSI or better.

As of early 2008, billion-transistor processors are commercially available, an

example of which is Intel's Montecito Itanium chip. This is expected to become more

commonplace as semiconductor fabrication moves from the current generation of 65 nm

processes to the next 45 nm generations (while experiencing new challenges such as increased

variation across process corners). Another notable example is NVIDIA’s 280 series GPU.

This microprocessor is unique in the fact that its 1.4 Billion transistor count,

capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor

count is largely due to the 24MB L3 cache). Current designs, as opposed to the earliest devices,

use extensive design automation and automated logic synthesis to lay out the transistors,

enabling higher levels of complexity in the resulting logic functionality. Certain high-

performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the

highest efficiency (sometimes by bending or breaking established design rules to obtain the last

bit of performance by trading stability).

What is VLSI?

VLSI stands for "Very Large Scale Integration". This is the field

which involves packing more and more logic devices into smaller and smaller areas.

VLSI

1. Simply we say Integrated circuit is many transistors on one chip.

2. Design/manufacturing of extremely small, complex circuitry using modified

semiconductor material

3. Integrated circuit (IC) may contain millions of transistors, each a few mm in size

4. Applications wide ranging: most electronic logic devices

History of Scale Integration

late 40s Transistor invented at Bell Labs

late 50s First IC (JK-FF by Jack Kilby at TI)

early 60s Small Scale Integration (SSI)

10s of transistors on a chip

late 60s Medium Scale Integration (MSI)

100s of transistors on a chip

early 70s Large Scale Integration (LSI)

1000s of transistor on a chip

early 80s VLSI 10,000s of transistors on a

chip (later 100,000s & now 1,000,000s)

Ultra LSI is sometimes used for 1,000,000s

SSI - Small-Scale Integration (0-102)

MSI - Medium-Scale Integration (102-103)

LSI - Large-Scale Integration (103-105)

VLSI - Very Large-Scale Integration (105-107)

ULSI - Ultra Large-Scale Integration (>=107)

Advantages of ICs over discrete components

While we will concentrate on integrated circuits , the properties of

integrated circuits-what we can and cannot efficiently put in an integrated circuit-largely

determine the architecture of the entire system. Integrated circuits improve system characteristics

in several critical ways. ICs have three key advantages over digital circuits built from discrete

components:

Size. Integrated circuits are much smaller-both transistors and wires are shrunk to

micrometer sizes, compared to the millimeter or centimeter scales of discrete

components. Small size leads to advantages in speed and power consumption,

since smaller components have smaller parasitic resistances, capacitances, and

inductances.

Speed. Signals can be switched between logic 0 and logic 1 much quicker within

a chip than they can between chips. Communication within a chip can occur

hundreds of times faster than communication between chips on a printed circuit

board. The high speed of circuits on-chip is due to their small size-smaller

components and wires have smaller parasitic capacitances to slow down the

signal.

Power consumption. Logic operations within a chip also take much less power.

Once again, lower power consumption is largely due to the small size of circuits

on the chip-smaller parasitic capacitances and resistances require less power to

drive them.

VLSI and systems

These advantages of integrated circuits translate into advantages at the system level:

Smaller physical size. Smallness is often an advantage in itself-consider

portable televisions or handheld cellular telephones.

Lower power consumption. Replacing a handful of standard parts with a

single chip reduces total power consumption. Reducing power consumption

has a ripple effect on the rest of the system: a smaller, cheaper power supply

can be used; since less power consumption means less heat, a fan may no

longer be necessary; a simpler cabinet with less shielding for electromagnetic

shielding may be feasible, too.

Reduced cost. Reducing the number of components, the power supply

requirements, cabinet costs, and so on, will inevitably reduce system cost. The

ripple effect of integration is such that the cost of a system built from custom

ICs can be less, even though the individual ICs cost more than the standard

parts they replace.

Understanding why integrated circuit technology has such profound influence on the design of

digital systems requires understanding both the technology of IC manufacturing and the

economics of ICs and digital systems.

Applications

Electronic system in cars.

Digital electronics control VCRs

Transaction processing system, ATM

Personal computers and Workstations

Medical electronic systems.

Etc….

Applications of VLSI

Electronic systems now perform a wide variety of tasks in daily life. Electronic

systems in some cases have replaced mechanisms that operated mechanically, hydraulically, or

by other means; electronics are usually smaller, more flexible, and easier to service. In other

cases electronic systems have created totally new applications. Electronic systems perform a

variety of tasks, some of them visible, some more hidden:

Personal entertainment systems such as portable MP3 players and DVD

players perform sophisticated algorithms with remarkably little energy.

Electronic systems in cars operate stereo systems and displays; they also

control fuel injection systems, adjust suspensions to varying terrain, and

perform the control functions required for anti-lock braking (ABS) systems.

Digital electronics compress and decompress video, even at high-definition

data rates, on-the-fly in consumer electronics.

Low-cost terminals for Web browsing still require sophisticated electronics,

despite their dedicated function.

Personal computers and workstations provide word-processing, financial

analysis, and games. Computers include both central processing units (CPUs)

and special-purpose hardware for disk access, faster screen display, etc.

Medical electronic systems measure bodily functions and perform complex

processing algorithms to warn about unusual conditions. The availability of

these complex systems, far from overwhelming consumers, only creates

demand for even more complex systems.

The growing sophistication of applications continually pushes the design and manufacturing of

integrated circuits and electronic systems to new levels of complexity. And perhaps the most

amazing characteristic of this collection of systems is its variety-as systems become more

complex, we build not a few general-purpose computers but an ever wider range of special-

purpose systems. Our ability to do so is a testament to our growing mastery of both integrated

circuit manufacturing and design, but the increasing demands of customers continue to test the

limits of design and manufacturing

ASIC

An Application-Specific Integrated Circuit (ASIC) is an integrated circuit

(IC) customized for a particular use, rather than intended for general-purpose use. For example, a

chip designed solely to run a cell phone is an ASIC. Intermediate between ASICs and industry

standard integrated circuits, like the 7400 or the 4000 series, are application specific standard

products (ASSPs).

As feature sizes have shrunk and design tools improved over the years, the

maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates

to over 100 million. Modern ASICs often include entire 32-bit processors, memory blocks

including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often

termed a SoC (system-on-a-chip). Designers of digital ASICs use a hardware description

language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.

Field-programmable gate arrays (FPGA) are the modern-day technology for building a

breadboard or prototype from standard parts; programmable logic blocks and programmable

interconnects allow the same FPGA to be used in many different applications. For smaller

designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC

design even in production.

1. An application-specific integrated circuit (ASIC) is an integrated circuit (IC)

customized for a particular use, rather than intended for general-purpose use.

2. A Structured ASIC falls between an FPGA and a Standard Cell-based ASIC

3. Structured ASIC’s are used mainly for mid-volume level designs

4. The design task for structured ASIC’s is to map the circuit into a fixed arrangement

of known cells

INTRODUCTION TO XILINX

Migrating Projects from Previous ISE Software Releases

When you open a project file from a previous release, the ISE® software prompts you to migrate

your project. If you click Backup and Migrate or Migrate Only, the software automatically

converts your project file to the current release. If you click Cancel, the software does not

convert your project and, instead, opens Project Navigator with no project loaded.

Note After you convert your project, you cannot open it in previous versions of the ISE

software, such as the ISE 11 software. However, you can optionally create a backup of the

original project as part of project migration, as described below.

To Migrate a Project

1. In the ISE 12 Project Navigator, select File > Open Project.

2. In the Open Project dialog box, select the .xise file to migrate.

Note You may need to change the extension in the Files of type field to display .npl

(ISE 5 and ISE 6 software) or .ise (ISE 7 through ISE 10 software) project files.

3. In the dialog box that appears, select Backup and Migrate or Migrate Only.

4. The ISE software automatically converts your project to an ISE 12 project.

Note If you chose to Backup and Migrate, a backup of the original project is created at

project_name_ise12migration.zip.

5. Implement the design using the new version of the software.

Note Implementation status is not maintained after migration.

Properties

For information on properties that have changed in the ISE 12 software, see ISE 11 to ISE 12

Properties Conversion.

IP Modules

If your design includes IP modules that were created using CORE Generator™ software or

Xilinx® Platform Studio (XPS) and you need to modify these modules, you may be required to

update the core. However, if the core netlist is present and you do not need to modify the core,

updates are not required and the existing netlist is used during implementation.

Obsolete Source File Types

The ISE 12 software supports all of the source types that were supported in the ISE 11

software.

If you are working with projects from previous releases, state diagram source files (.dia), ABEL

source files (.abl), and test bench waveform source files (.tbw) are no longer supported. For state

diagram and ABEL source files, the software finds an associated HDL file and adds it to the

project, if possible. For test bench waveform files, the software automatically converts the TBW

file to an HDL test bench and adds it to the project. To convert a TBW file after project

migration, see Converting a TBW File to an HDL Test Bench.

Migrating Projects from Previous ISE Software Releases

When you open a project file from a previous release, the ISE® software prompts you to migrate

your project. If you click Backup and Migrate or Migrate Only, the software automatically

converts your project file to the current release. If you click Cancel, the software does not

convert your project and, instead, opens Project Navigator with no project loaded.

Note After you convert your project, you cannot open it in previous versions of the ISE

software, such as the ISE 11 software. However, you can optionally create a backup of the

original project as part of project migration, as described below.

To Migrate a Project

1. In the ISE 12 Project Navigator, select File > Open Project.

2. In the Open Project dialog box, select the .xise file to migrate.

Note You may need to change the extension in the Files of type field to display .npl

(ISE 5 and ISE 6 software) or .ise (ISE 7 through ISE 10 software) project files.

3. In the dialog box that appears, select Backup and Migrate or Migrate Only.

4. The ISE software automatically converts your project to an ISE 12 project.

Note If you chose to Backup and Migrate, a backup of the original project is created at

project_name_ise12migration.zip.

5. Implement the design using the new version of the software.

Note Implementation status is not maintained after migration.

Properties

For information on properties that have changed in the ISE 12 software, see ISE 11 to ISE 12

Properties Conversion.

IP Modules

If your design includes IP modules that were created using CORE Generator™ software or

Xilinx® Platform Studio (XPS) and you need to modify these modules, you may be required to

update the core. However, if the core netlist is present and you do not need to modify the core,

updates are not required and the existing netlist is used during implementation.

Obsolete Source File Types

The ISE 12 software supports all of the source types that were supported in the ISE 11

software.

If you are working with projects from previous releases, state diagram source files (.dia), ABEL

source files (.abl), and test bench waveform source files (.tbw) are no longer supported. For state

diagram and ABEL source files, the software finds an associated HDL file and adds it to the

project, if possible. For test bench waveform files, the software automatically converts the TBW

file to an HDL test bench and adds it to the project. To convert a TBW file after project

migration, see Converting a TBW File to an HDL Test Bench.

Using ISE Example Projects

To help familiarize you with the ISE® software and with FPGA and CPLD designs, a set of

example designs is provided with Project Navigator. The examples show different design

techniques and source types, such as VHDL, Verilog, schematic, or EDIF, and include different

constraints and IP.

To Open an Example

1. Select File > Open Example.

2. In the Open Example dialog box, select the Sample Project Name.

Note To help you choose an example project, the Project Description field describes

each project. In addition, you can scroll to the right to see additional fields, which

provide details about the project.

3. In the Destination Directory field, enter a directory name or browse to the

directory.

4. Click OK.

The example project is extracted to the directory you specified in the Destination Directory

field and is automatically opened in Project Navigator. You can then run processes on the

example project and save any changes.

Note If you modified an example project and want to overwrite it with the original example

project, select File > Open Example, select the Sample Project Name, and specify the same

Destination Directory you originally used. In the dialog box that appears, select Overwrite the

existing project and click OK.

Creating a Project

Project Navigator allows you to manage your FPGA and CPLD designs using an ISE® project,

which contains all the source files and settings specific to your design. First, you must create a

project and then, add source files, and set process properties. After you create a project, you can

run processes to implement, constrain, and analyze your design. Project Navigator provides a

wizard to help you create a project as follows.

Note If you prefer, you can create a project using the New Project dialog box instead of the

New Project Wizard. To use the New Project dialog box, deselect the Use New Project wizard

option in the ISE General page of the Preferences dialog box.

To Create a Project

1. Select File > New Project to launch the New Project Wizard.

2. In the Create New Project page, set the name, location, and project type, and

click Next.

3. For EDIF or NGC/NGO projects only: In the Import EDIF/NGC Project page,

select the input and constraint file for the project, and click Next.

4. In the Project Settings page, set the device and project properties, and click Next.

5. In the Project Summary page, review the information, and click Finish to create

the project.

Project Navigator creates the project file (project_name.xise) in the directory you specified.

After you add source files to the project, the files appear in the Hierarchy pane of the Design

panel. Project Navigator manages your project based on the design properties (top-level module

type, device type, synthesis tool, and language) you selected when you created the project. It

organizes all the parts of your design and keeps track of the processes necessary to move the

design from design entry through implementation to programming the targeted Xilinx® device.

Note For information on changing design properties, see Changing Design Properties.

You can now perform any of the following:

Create new source files for your project.

Add existing source files to your project.

Run processes on your source files.

Modify process properties.

Creating a Copy of a Project

You can create a copy of a project to experiment with different source options and

implementations. Depending on your needs, the design source files for the copied project and

their location can vary as follows:

Design source files are left in their existing location, and the copied project

points to these files.

Design source files, including generated files, are copied and placed in a

specified directory.

Design source files, excluding generated files, are copied and placed in a

specified directory.

Copied projects are the same as other projects in both form and function. For example, you can

do the following with copied projects:

Open the copied project using the File > Open Project menu command.

View, modify, and implement the copied project.

Use the Project Browser to view key summary data for the copied project and

then, open the copied project for further analysis and implementation, as described in

Using the Project Browser.

Note Alternatively, you can create an archive of your project, which puts all of the project

contents into a ZIP file. Archived projects must be unzipped before being opened in Project

Navigator. For information on archiving, see Creating a Project Archive.

To Create a Copy of a Project

1. Select File > Copy Project.

2. In the Copy Project dialog box, enter the Name for the copy.

Note The name for the copy can be the same as the name for the project, as long as you

specify a different location.

3. Enter a directory Location to store the copied project.

4. Optionally, enter a Working directory.

By default, this is blank, and the working directory is the same as the project directory.

However, you can specify a working directory if you want to keep your ISE® project

file (.xise extension) separate from your working area.

5. Optionally, enter a Description for the copy.

The description can be useful in identifying key traits of the project for reference later.

6. In the Source options area, do the following:

o Select one of the following options:

o Keep sources in their current locations - to leave the design source files

in their existing location.

If you select this option, the copied project points to the files in their

existing location. If you edit the files in the copied project, the changes

also appear in the original project, because the source files are shared

between the two projects.

o Copy sources to the new location - to make a copy of all the design

source files and place them in the specified Location directory.

If you select this option, the copied project points to the files in the specified

directory. If you edit the files in the copied project, the changes do not appear in

the original project, because the source files are not shared between the two

projects.

o Optionally, select Copy files from Macro Search Path directories to copy files

from the directories you specify in the Macro Search Path property in the Translate Properties

dialog box. All files from the specified directories are copied, not just the files used by the

design.

Note If you added a netlist source file directly to the project as described in

Working with Netlist-Based IP, the file is automatically copied as part of Copy

Project because it is a project source file. Adding netlist source files to the project

is the preferred method for incorporating netlist modules into your design,

because the files are managed automatically by Project Navigator.

o Optionally, click Copy Additional Files to copy files that were not included in

the original project. In the Copy Additional Files dialog box, use the Add Files and Remove

Files buttons to update the list of additional files to copy. Additional files are copied to the

copied project location after all other files are copied.

7. To exclude generated files from the copy, such as implementation results and

reports, select Exclude generated files from the copy.

When you select this option, the copied project opens in a state in which processes have

not yet been run.

8. To automatically open the copy after creating it, select Open the copied project.

Note By default, this option is disabled. If you leave this option disabled, the original

project remains open after the copy is made.

Click OK.

Creating a Project Archive

A project archive is a single, compressed ZIP file with a .zip extension. By default, it contains all

project files, source files, and generated files, including the following:

User-added sources and associated files

Remote sources

Verilog `include files

Files in the macro search path

Generated files

Non-project files

To Archive a Project

1. Select Project > Archive.

2. In the Project Archive dialog box, specify a file name and directory for the ZIP

file.

3. Optionally, select Exclude generated files from the archive to exclude

generated files and non-project files from the archive.

4. Click OK.

A ZIP file is created in the specified directory. To open the archived project, you must first

unzip the ZIP file, and then, you can open the project.

Note Sources that reside outside of the project directory are copied into a remote_sources

subdirectory in the project archive. When the archive is unzipped and opened, you must either

specify the location of these files in the remote_sources subdirectory for the unzipped project, or

manually copy the sources into their original location.

INTRODUCTION TO VERILOG HDL

What is HDL

A typical Hardware Description Language (HDL) supports a mixed-level description in

which gate and netlist constructs are used with functional descriptions. This mixed-level

capability enables you to describe system architectures at a high level of abstraction, then

incrementally refine a design’s detailed gate-level implementation.

HDL descriptions offer the following advantages:

• We can verify design functionality early in the design process. A design written as an HDL

description can be simulated immediately. Design simulation at this high level — at the

gate-level before implementation — allows you to evaluate architectural and design decisions.

• An HDL description is more easily read and understood than a netlist or schematic description.

HDL descriptions provide technology-independent documentation of a design and its

functionality. Because the initial HDL design description is technology independent, you

can use it again to generate the design in a different technology, without having to

translate it from the original technology.

• Large designs are easier to handle with HDL tools than schematic tools.

Verilog Overview :

Introduction

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description

Language is a language used to describe a digital system, for example, a microprocessor or

a memory or a simple flip-flop. This just means that, by using a HDL one can describe any

hardware (digital ) at any level.

Verilog provides both behavioral and structural language structures. These structures allow

expressing design objects at high and low levels of abstraction. Designing hardware with a

language such as Verilog allows using software concepts such as parallel processing and

object-oriented programming. Verilog has a syntax similar to C and Pascal.

Design Styles

Verilog like any other hardware description language permits the designers to create a design in

either Bottom-up or Top-down methodology.

Bottom-Up Design

The traditional method of electronic design is bottom-up. Each design is performed at the

gate-level using the standard gates. With increasing complexity of new designs this

approach is nearly impossible to maintain. New systems consist of ASIC or

microprocessors with a complexity of thousands of transistors. These traditional bottom-up

designs have to give way to new structural, hierarchical design methods. Without these new

design practices it would be impossible to handle the new complexity.

Top-Down Design

The desired design-style of all designers is the top-down design. A real top-down design

allows early testing, easy change of different technologies, a structured system design and

offers many other advantages. But it is very difficult to follow a pure top-down design. Due

to this fact most designs are mix of both the methods, implementing some key elements of

both design styles.

Complex circuits are commonly designed using the top down methodology. Various

specification levels are required at each stage of the design process.

Abstraction Levels of Verilog

Verilog supports a design at many different levels of abstraction. Three of them are very

important:

Behavioral level

Register-Transfer Level

Gate Level

Behavioral level

This level describes a system by concurrent algorithms (Behavioral). Each algorithm itself is

sequential, that means it consists of a set of instructions that are executed one after the other.

Functions, Tasks and Always blocks are the main elements. There is no regard to the structural

realization of the design.

Register-Transfer Level

Designs using the Register-Transfer Level specify the characteristics of a circuit by operations

and the transfer of data between the registers. An explicit clock is used. RTL design contains

exact timing possibility; operations are scheduled to occur at certain times. Modern definition

of a RTL code is "Any code that is synthesizable is called RTL code".

Gate Level

Within the logic level the characteristics of a system are described by logical links and

their timing properties. All signals are discrete signals. They can only have definite logical

values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (AND, OR,

NOT etc gates). Using gate level modeling might not be a good idea for any level of logic

design. Gate level code is generated by tools like synthesis tools and this Netlist is used for gate

level simulation and for backend.

vlsi design flow

Introduction

Design is the most significant human endeavor: It is the channel through which creativity is

realized. Design determines our every activity as well as the results of those activities; thus it

includes planning, problem solving, and producing. Typically, the term "design" is applied

to the planning and production of artifacts such as jewelry, houses, cars, and cities. Design is

also found in problem-solving tasks such as mathematical proofs and games. Finally,

design is found in pure planning activities such as making a law or throwing a party.

More specific to the matter at hand is the design of manufacturable artifacts. This

activity uses all facets of design because, in addition to the specification of a producible

object, it requires the planning of that object's manufacture, and much problem solving

along the way. Design of objects usually begins with a rough sketch that is refined by

adding precise dimensions. The final plan must not only specify exact sizes, but also include a

scheme for ordering the steps of production. Additional considerations depend on the

production environment; for example, whether one or ten million will be made, and how

precisely the manufacturing environment can be controlled.

A semiconductor process technology is a method by which working circuits can be

manufactured from designed specifications. There are many such technologies, each of

which creates a different environment or style of design.

SOURCE CODE AND RESULTS

CONCLUSIONS ANS FUTURESCOPE

This paper presents an implementation of a floating point multiplier that supports the IEEE 754-

2008 binary interchange format; the multiplier doesn’t implement rounding and just presents the

significand multiplication result as is (48 bits); this gives better precision if the whole 48 bits are

utilized in another unit; i.e. a floating point adder to form a MAC unit. The design has three

pipelining stages and after implementation on a Xilinx Virtex5 FPGA it achieves 301 MFLOPs.