Overall controller design
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![Page 1: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/1.jpg)
Overall controller design
1. Draw R.L.for G(s)
2. Draw desired region for closed-loop poles based on specs
3. If R.L. goes through region, pick pd on R.L. and in region. Go to step 7.
![Page 2: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/2.jpg)
4. Pick pd in region (leave some safety flex)
5. Compute angle deficiency:
6. a. PD control, choose zpd such that
then
dpG
pdd zp
pdzssC
![Page 3: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/3.jpg)
6. b. Lead control: choose zlead, plead such that
You can select zlead & compute plead.Or you can use the “bisection”
method to compute z and p.
Then
leadd
leadd
pp
zp
lead
lead
ps
zssC
![Page 4: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/4.jpg)
7. Compute overall gain:
8. If there is no steady-state error requirement, go to 14.
9. With K from 7, evaluate error constant. You already have:
dps
sGsCK
1
sGsCKsKs
a *lim
0avp ,,
2,1,0
![Page 5: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/5.jpg)
The 0, 1, 2 should match p, v, a
This is for lag control.
For PI:
s
zssGsCKsK i
sa
*lim0
control. PI theis wheres
zs i
![Page 6: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/6.jpg)
10. Compute desired error const. from specs:
11. For PI : set K*a = K*d & solve for zi
For lag : pick zlag & let
advdpdss KKK
e1
or , 1
or 1
1
d
alaglag K
Kzp
lag
lagi
ps
zs
s
zssC
or
![Page 7: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/7.jpg)
12. Re-compute K
13.
14. Get closed-loop T.F. Do step response analysis.
15. If not satisfactory, go back to 3 and redesign.
dps
sGsCsCK
1
sCsCKsC
![Page 8: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/8.jpg)
If we have both PI and PD we have PID control:
s
KsKKsC I
DP
KKD :where
ipdP zzKK
ipdI zKzK
![Page 9: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/9.jpg)
Lead-lag design example
Too much overshoot, too slow & ess to ramp is too large.
984.125.0at poles loop-closed ,1With jsC
125.0
![Page 10: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/10.jpg)
%16 :Want pM
sec36.0rt%2ramp to sse
5.0%16 :Sol pM
cone 60 i.e.
58.1
sec36.0 r
nr tt
%21
%2 vd
ss Ke
50let vdK 1 Type
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Draw R.L. for G(s) & the desired region
3.45.2 jpd
![Page 12: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/12.jpg)
Clearly R.L. does not pass through desired region.
need PD or lead.
Let’s do lead.Pick pd in region
3.43 picked have could j
3.45.2 jpd
![Page 13: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/13.jpg)
: Compute
Now choose zlead & plead.
Could use bisection.
Let’s pick zlead to cancel plant pole s + 0.5
dpG 235
55235180
5.0let leadz
![Page 14: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/14.jpg)
Use our formula to get plead
Now compute K :
Now evaluate error constant Kva
021.5leadp
26.6
1
dlead
lead
pspszs sG
K
sGpszs
sKKlead
lead
sva
0lim
![Page 15: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/15.jpg)
spss leadKs
41
0lim
021.526.644
leadpK
1.050021.526.64
vd
va
KK
20~5
5.2
20~5
RePick
dp
z
2.0Pick z
02.0then vd
va
K
Kzp
![Page 16: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/16.jpg)
Should re-compute K, but let’s skip:
do step response.
02.0
2.0
021.5
5.026.6
s
s
s
ssC
02.0021.5
2.026.6
sss
ssGsC
2.026.602.0021.5
2.026.6..
ssss
ssGr
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Op-amp controller circuit:
1. Proportional:
eKeRR
RRu P
13
24
13
24
RR
RRKP
![Page 19: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/19.jpg)
2. Integral:
131
4
CRR
RK I
ses
K I
sesCRR
Rsu
113
4 1
![Page 20: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/20.jpg)
3. Derivative control:
123
4 CRR
RKD
sseKD
sesCRR
Rsu 12
3
4
![Page 21: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/21.jpg)
4. PD controller:
123
4
13
24 , CRR
RK
RR
RRK DP
sesKK DP
sesCRR
R
R
Rsu 111
1
2
3
4
![Page 22: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/22.jpg)
5. PI controller:
213
4
13
24 1,
CRR
RK
RR
RRK IP
ses
KK I
P
sesCR
sCR
R
R
R
Rsu
22
22
1
2
3
4 1
![Page 23: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/23.jpg)
6. PID controller:
213
412
3
4
22
11
13
24 ,,1CRR
RKCR
R
RK
CR
CR
RR
RRK IDP
ses
KsKK I
DP
sesCR
sCRsCR
R
R
R
Rsu
22
2211
1
2
3
4 11
![Page 24: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/24.jpg)
7. Lead or lag controller:
221123
14 1,
1,
CRp
CRz
CR
CRK
seps
zsKse
sCR
sCR
RR
RRsu
1
1
22
11
13
24
seCRs
CRs
CR
CR
22
11
23
14
1
1
![Page 25: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/25.jpg)
If R1C1 > R2C2
then z < pThis is lead controller
If R1C1 < R2C2
then z > pThis is lag controller
![Page 26: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/26.jpg)
8. Lead-lag controller:
se
sCRR
sCR
sCR
sCRR
RR
RRsu
lag
242
22
lead
11
131
35
46
1
1
1
1
11131 CRCRR 24222 CRRCR
![Page 27: Overall controller design](https://reader035.fdocuments.net/reader035/viewer/2022062221/56812c61550346895d90f398/html5/thumbnails/27.jpg)
seps
zs
ps
zsK
2
2
1
1
42
2
1
31
35
46
RR
R
R
RR
RR
RRK
lead11
111
1311 CR
pCRR
z
lag11
2422
222 CRR
pCR
z