Optical Front-End System Reference Design · Laser driver Optical attenuator 10- to 60-V supply...

Laser driver Optical

attenuator

10- to 60-Vsupply

OPA857

+

- VOCM

THS4541

ADC34Jx

TSWJ1456controller board

Trigger anddata capture

Pulse trigger

TI DesignsOptical Front-End System Reference Design

TI Designs Design FeaturesTI Designs provide the foundation that you need • Optical Front-End Design With Demonstratedincluding methodology, testing and design files to System Performancequickly evaluate and customize the system. TI Designs • High-Speed Amplifier Signal Path With Bandwidthhelp you accelerate your time to market. Greater Than 120 MHz

• High-Speed 14-Bit ADC With JESD204B InterfaceDesign Resources• Ultrafast Laser-Diode Driver and Laser Diode to

Design FolderTIDA-00725 Generate Tx SignalOPA857 Product Folder • Avalanche Photodiode (APD) Front-End WithTHS4541 Product Folder Onboard High-Voltage SupplyADC34J45 Product Folder • High-Speed Transimpedance Amplifier for I-to-VADC34J45EVM Product Folder ConversionTINA-TI™ Tools Folder • A Fully Differential Amplifier (FDA) to Drive theHSDC PRO Tools Folder ADC

• Flexibility to Easily Change Components in theOptical, Amplifier, or Data-Converter Signal-Path

ASK Our E2E ExpertsFeatured Applications• OTDR• Optical Amplifiers• CAT-Scanner Front Ends• Photodiode Monitoring• Machine Vison• Distance Measurement• Missle Guidance• 3D Scanning

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and otherimportant disclaimers and information.

TINA-TI is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

1TIDUAZ1–November 2015 Optical Front-End System Reference DesignSubmit Documentation Feedback

Copyright © 2015, Texas Instruments Incorporated

http://www.ti.com/tool/TIDA-00725

http://www.ti.com/product/OPA857

http://www.ti.com/product/ths4541

http://www.ti.com/product/ADC34J45

http://www.ti.com/tool/adc34j45evm?keyMatch=ADC34J45&tisearch=Search-EN-Everything

http://www.ti.com/tina-ti

http://www.ti.com/tool/dataconverterpro-sw?keyMatch=hsdc%20pro%20software&tisearch=Search-EN-Everything

http://e2e.ti.com/support/applications/ti_designs/

http://e2e.ti.com

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=TIDUAZ1

Key System Specifications www.ti.com

1 Key System Specifications

Parameter SpecificationSupply voltage 5-V external supplyAnalog bandwidth 120 MHzADC sampling rate 160 MSPSMaximum system gain 100 kΩProgrammable transimpedance gain 5 kΩ/20 kΩMaximum signal swing 1 VPP

Noise performance ≥ 60-dB SNRAveraged noise performance < 10-µVRMS

2 Optical Front-End System Reference Design TIDUAZ1–November 2015Submit Documentation Feedback


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iC-HB 155-MHz laser driver board

IBIAS

ISIG

10- to 60-VSupply

OPA857

+

-

VREF2

THS4541

+

VREF1

5 K to 20 K Gain = 5 V/V

Amplifier signal chain board

50

50

ADC34J45

Clocking + FPGA + memory

50

50 VREF2

Controller + ADC3K board

Optical attenuator and optical fiber

Op

tica

l pu

lse

trig

ger

Trigger anddata capture

www.ti.com System Description

2 System DescriptionFigure 1 is a detailed block diagram of the evaluation system and subblocks. The system is an interface ofthe following four different PCBs.• Laser-diode driver + laser-diode board• Amplifier signal-chain board• ADC34J45, analog-to-digital converter (ADC) board• TSW14J56 digital-capture board

A high-speed laser driver pulses the laser diode that transmits an optical pulse through the fiber. Theoptical attenuator controls the strength of the optical pulse incident on the photo-diode without changingthe operating point of the laser diode or its driver. A high-speed photodiode placed in close proximity tothe transimpedance amplifier converts the optical energy into an output current. The transimpedanceamplifier converts the current into a pseudo-differential output voltage. The subsequent fully differentialamplifier (FDA) stage converts the signal to a fully differential signal and level-shifts the output common-mode to match the ADC. The FDA drives the ADC through a doubly terminated 50-Ω resistor.

Figure 1. Block Diagram of System for Evaluation

The TSW1456 digital-capture board generates triggers to pulse the laser diode while simultaneouslysending a signal to the ADC to convert data. The firmware allows multiple triggers with a programmablerepetition rate. The firmware can also control the time-delay between the trigger that fires the laser and thetrigger to the ADC that converts data. The ADC results are buffered into memory and the average result iscomputed on the PC. In test and measurement systems such as optical time-domain reflectometry(OTDR), this averaging feature can lower the noise floor of the entire system, which improves SNR. Thesystem block diagram in Figure 1 is a loop-back system to enable evaluation of the electrical signal chainin a controlled environment.



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+3.3 V

6.7k

20k

25

25

OUTP

OUTN

IN

VCM = (5/9)* VCC

System Description www.ti.com

2.1 OPA857 Transimpedance AmplifierThe OPA857 is a high-bandwidth, programmable gain, integrated-transimpedance amplifier (TIA).Standard operational amplifiers have a gain-bandwidth relationship, where bandwidth decreases as gain isincreased. In the case of the OPA857, switching the transimpedance gain also changes the internalcompensation of the amplifier. The closed-loop bandwidth does not follow convention and optimizes thebandwidth of amplifiers.

The OPA857 also has a pseudo-differential output that makes it easier to interface to the subsequent FDAstage. The pseudo-differential output also reduces the common-mode noise of the TIA stage. TheOPA857 close to the photodiode on the amplifier signal-chain board minimizes parasitic capacitance. Theboard is powered off a 5-V DC supply, which is plugged into the AC mains. A TPS79901 adjustable-linearregulator converts the 5-V input into a 3.3-V output that drives the OPA857. The output common-mode ofthe OPA857 is VCC × 5/9 = 1.83 V. The photodiode is biased and only sources an output current, which isimportant because the OPA857 output is optimized to swing less than its common-mode voltage. Formore information, see Figure 2.

Figure 2. OPA857 Transimpedance Amplifier

2.2 THS4541 Differential-Amplifier StageThe THS4541 is a high-bandwidth, low-noise FDA used to provide additional gain to the output of the TIAstage. The THS4541 also converts the pseudo-differential output of the OPA857 into a fully differentialsignal to drive the next ADC stage. The THS4541 level-shifts the output common-mode of the OPA857 tomatch the specified input common-mode of the ADC. An onboard resistor divider connected between theFDA power supply and GND sets the output common-mode of the THS4541. The FDA stage is poweredby 3.3 V from its TPS79901 linear regulator. The THS4541 is configured in a gain of 5 V/V, which resultsin an estimated closed-loop bandwidth of 170 MHz.

Increasing the closed-loop gain increases the phase margin of the amplifier and reduces the overshoot toa pulsed input. A smooth-settling transient response reduces blind-spots and other test artifacts inapplications like OTDR systems. Increasing the RG value improves the response of the OPA857 becausethe bandwidth of the OPA857 decreases as the output loading is reduced. The gain resistor (RG) forms theoutput load of the OPA857. A large value of RF drives up the value of RG, which reduces the output loadon the OPA857.



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+

-

3.3 V

0.95 V

2k

2k

374

374 50

50

From OPA857TIA stage

To ADC34J45Evaluation module


A large RF may reduce the phase-margin of the amplifier. The feedback resistance with the inputcapacitance of the amplifier creates a zero in the noise-gain response of the amplifier. This zero canreduce the phase-margin. Add an appropriately sized feedback capacitance (CF) in parallel with RF tocompensate for the zero in the noise-gain response. The combination of RF and CF creates a pole in theresponse. The pole in the response helps shape the final closed-loop response of the amplifier.

The FDA and ADC are on separate PCBs connected through SMA connectors. The placement of the FDAand ADC creates some physical separation between the two devices and a suboptimal layout. To reducethe effects of reflections, each output of the THS4541 is doubly terminated with 50-Ω resistors. Becausethe THS4541 is doubly terminated with 50-Ω resistors, the 6-dB output attenuation reduces the overallamplifier gain to 2.5 V/V. In a dedicated single-board system, the THS4541 and ADC34J45 can be placedclose to each other to remove the requirement for the output termination.

Another effect to consider is the output swing of the THS4541. In standard CW applications, each outputof the FDA swings symmetrically about its output common-mode with equal magnitude and oppositephase. In the case of a transimpedance application, the photo-diode can either source or sink currentresults in a unipolar output swing from the transimpedance amplifier stage. When the output signal isapplied to the FDA stage, each output swings either higher or lower than its common-mode using only halfthe available swing of the amplifier. The ADC also uses only half its available signal swing. For moreinformation, see Figure 3.

Figure 3. THS4541 FDA Block Diagram

2.3 ADC34J45 High-Speed ADCThe ADC34J45 is a highly linear, low-power, 14-bit ADC that can sample at up to 160 Msps. Toaccommodate many different applications, this family of devices comes in configurations that include dualor quad channels, 12 bits or 14 bits, and sample rates from 50 to 160 Msps. The JESD204B data interfaceallows a simple, flexible SERDES interface to many FPGAs and processors. This device also supportsJESD204B subclasses 0, 1, and 2. The support for these subclasses provides various options forsynchronizing the multiple devices in phased-array applications.



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CLKP,

CLKM

Configuration Registers

SC

LK

SE

N

SD

ATA

SD

OU

T

RE

SE

T

Common

ModeVCM

DAP,

DAM

SYSREFP,

SYSREFM

Divide

by 1,2,4

INAP,

INAM

PLL

SYNCP,

SYNCM

DDP,

DDM

12-Bit

ADC

12-Bit

ADC

INDP,

INDM

Digital

Encoder and

JESD204B

OVRA

Digital

Encoder and

JESD204B

OVRD

PD

N

DBP,

DBMINBP,

INBM12-Bit

ADCOVRB

Digital

Encoder and

JESD204B

DCP,

DCM12-Bit

ADC

INCP,

INCM

Digital

Encoder and

JESD204B OVRC


With an input range of 2 Vpp, SNR of 72 dBFS, and SFDR greater than 86 dBc, TI designed theADC34J45 family for demanding high-frequency signals with a large dynamic range. A 3-dB inputbandwidth of 450-MHz enables this device to subsample systems with frequencies up to three timesgreater than the maximum sample rate. In this application, a 14-bit ADC channel digitizes a repetitive,synchronous optical pulse. For more information, see Figure 4 and Figure 5.

Figure 4. ADC34Jxx Functional Block Diagram



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Figure 5. ADC34J45EVM Top View



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2.4 TSW14J56 Digital-Capture BoardThe TSW14J56 is an FPGA-based digital-capture card for ADCs that uses the JESD204B digital interface.The TSW14J56 provides up to 10 lanes running at 12.5 Gbps to support the fastest converters that use aJESD204B interface. The board has 2 Gsamples of memory in which to store samples from the ADC. TheUSB3.0 interface on this capture platform enables fast data transfers from the sample memory.

HSDC Pro software controls the TSW14J56. This software lets you capture data from the ADC andprocess it in the time domain or frequency domain using a fast Fourier transform (FFT). The TSW14J56captures more than 10,000 triggered ADC34Jxx conversions. These successive conversions are thenextracted for averaging and further analysis. See Figure 6 and Figure 7 for more information.

Figure 6. TSW14J56 Digital Capture Card



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Figure 7. HSDC Pro Software GUI

2.5 Optical Components

2.5.1 Laser Driver and Laser DiodeThe laser-diode driver and laser diode are on a separate PCB with a 5-V supply. The laser driver is an iC-HB, 155-MHz triple-laser switch from iC-Haus. See Laser-Diode Driver, iC-HB datasheet for the datasheet for the laser driver. The laser diode is a 1550-nm DFB LDM5S515-015. In a pulsed high-speedapplication, toggling a laser on and off causes suboptimal performance. Rather than turning the laser off,configure the laser just less than its turnon threshold when it is inactive to ensure a smoother and quickerturnon. This configuration minimizes the effects of parasitic capacitances that require charging anddischarging during transient operation.

Figure 6 shows a simplified schematic of the laser setup. See Figure 15 for the complete PCB schematic.Consider each channel of the laser-diode driver a voltage-controlled current source (VCCS) with anenable and disable switch. The three parallel channels are as follows:• The bias channel sets the laser at its threshold condition.• Channel 1 drives the signal current that toggles the laser on or off.• Channel 2 is unused in this application.



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3.74 k

VDD

EN1

Signal drive

806

VDD

ENB

Bias drive

Trigger from TSW14J56

CIB

CI13.01 k

1.50 k


Using the onboard resistor divider and potentiometer subcircuit connected between the 5-V supply andground, set the bias voltage to control the VCCS. Set the bias supply to 1.15 V and the signal supply onchannel 1 to 1.65 V. Use the jumper to statically control the bias channel state, while the trigger generatedby the TSW14J56 controls the signal channel. The adjustable linear regulator (U3) is configured to drivean output voltage of 1.8 V on the VDIG line. This voltage drives the primary side of the SN74LVC1T45logic-level translator to shift the 0- to 1.8-V logic level from the trigger signal of the TSW14J56 to a 0- to 5-V digital signal required to drive the iC-HB chip. For more information, see Figure 8.

Figure 8. Laser Diode Block Diagram

2.5.2 PhotodiodeTI used a low-voltage InGaAs photodiode (NR-7500) and high-voltage avalanche photodiode (NR8300) toevaluate the system. TI used an LT3995-integrated APD supply to bias the photodiodes. The LT3995 cansupply a bias voltage from 10 to 60 V. This range covers the operating range of both photodiodes duringevaluation.



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Frequency (Hz)

Out

put N

oise

(nV

/ H

z)

1

10

100

100k 1M 10M 100M

D001

5-k: TIA Gain20-k: TIA Gain

www.ti.com Simulations

3 Simulations

3.1 Noise SimulationFigure 9 shows the schematic that simplifies the noise of the amplifier signal chain. A current source in thecircuit represents the photodiode.

Figure 9. TINA Schematic For Noise Simulation

Figure 10 shows the output noise of the amplifier system measured at the Vd_Out node. The totalsimulated output noise for the 5-kΩ and 20-kΩ transimpedance-gain setting is 303 µVRMS and 888 µVRMS,respectively, assuming a 135-MHz brick-wall filter. The 900-fF capacitance is an estimate of the sum ofthe diode capacitance, PCB parasitic capacitance, and diode package parasitic capacitance.

Figure 10. Simulated Output Noise of the Amplifier Chain



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Simulations www.ti.com

3.2 THS4541 Loop-Gain and Phase Margin SimulationTo get a pulse-response with minimal overshoot and ringing on the rising and falling edges of the pulse,the phase-margin of the FDA circuit must be greater than 70°. To simulate the loop-gain of the THS4541,use the circuit in Figure 11. The voltage-controlled voltage source (VCVS1) converts the single-endedsource signal into a full-differential output that subsequently drives the inputs of the amplifiers.

To measure loop-gain, break the loop of the amplifier at its summing-junctions. The differential input signaldrives the inputs of the amplifier forward through C1 and C2, and the L1 and L2 inductors isolate thefeedback signal from the amplifiers input pins and the source. This method is similar to the loop-gainanalysis in single-ended operational amplifiers. C3 and C4 show the approximate parasitic capacitance inthe amplifiers feedback path. C_diff models the input common-mode and differential capacitance of theamplifier because the actual input capacitance of the amplifier has been isolated from the feedbacknetwork due to the inductors.

Figure 11. THS4541 Loop-Gain Analysis TINA Schematic



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Frequency (Hz)

Loop

Gai

n P

hase

(q)

Loop

Gai

n M

agni

tude

(dB

)

-225 -20

-180 0

-135 20

-90 40

-45 60

0 80

45 100

10 100 1k 10k 100k 1M 10M 100M 1G

D002

Loop Gain Phase (q)Loop Gain Magnitude (dB)

www.ti.com Simulations

The simulated loop-gain magnitude and phase plotted in Figure 12 predict a phase-margin ofapproximately 79°. Control-loop theory estimates the pulse-overshoot for 79° of phase-margin to less than0.001%. The simulated closed-loop bandwidth of the FDA circuit is 150 MHz.

Figure 12. Simulated Loop Gain of THS4541



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Signal-enable jumper

Trigger in from

TSW14J56

Bias-control potentiometer

Bias-enable

Signal-control potentiometer

PCB Schematic and Layout www.ti.com

4 PCB Schematic and LayoutFigure 13 and Figure 15 show the PCB layout and schematic for the laser-driver board. Section 9.1contains the bill of materials (BOM). Minimize trace lengths to reduce parasitic trace resistance andcapacitance. Match the trace lengths wherever possible. To create low-impedance paths from the ICs totheir respective power supplies, place bypass capacitors close to the supply pins of the amplifiers, laserdriver, and APD supply.

Figure 13. Laser-Driver Circuit PCB



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TIA gain control switch

20% APDoutput current

www.ti.com PCB Schematic and Layout

Figure 14 and Figure 16 show the PCB layout and schematic for the signal-driver board. The amplifiersignal chain occupies 38.7 mm2 of PCB area. This area includes the two amplifiers and the surroundingresistors and capacitors. Both the OPA857 and THS4541 are available in a 3-mm × 3-mm VQFNpackage. The area consumed by the amplifiers is 18 mm2.

Figure 14. Signal-Chain Circuit PCB



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VDD

LD CathodeLD Cathode

LD_Anode1

LD_Cathode2

PD_Cathode3

PD_Anode4

LD1

NC8 VDD

VDD

NC13

NC11

VDD

VDD

VDD

VDD

NC20

VDD

NC22

NC23

VDD

VDD

NE

R20

AGND21

LDK22

LDKB3

AGNDB4

LDK15

AGND16

EP

17

EN

18

SY

N1

9

VT

TL

10

SY

NB

11

CI1

12

ENB13

EPB14

VDD15

GND16

CIB17

IMON18

CI2

19

TT

L21

SY

N2

22

EN

223

EP

224

Pw

rPa

d25

U1iC-HB

Monitor Diode

IMON

BIAS IN

SIGNAL IN

SIGNAL EN

GND

1

2345

J1

0.1µFC1

100pFC11

4.02KW

R8

1

2

3

JP1

GND

1

2 3 4 5

J2

1µFC8

GND

1

2345

J4

49.9W

R9

1

2

3

JP31µFC10

4.02KW

R5

GND

1

2345

J6GND

1

2345

J5

VDD

1µFC9

1

3

2

+5V

RAPC722X

1

4

3

D1

MBRB2515LT4G

5V

GND

4

7,8 1,2,3

5,6,

Q1CSD18532Q5B

47µFC2

22µFC3

10µFC4

1µFC5

0.1µFC6

1.00KW

R11

21 Green

+5LTST-C150KGKT

GND

IN1

2

EN3

FB4

OUT5

U3

TPS79901DDCTVDD

0.1µFC7

4.99KW

R12

10.0KW

R13

1000pFC12

2.2µFC13

0.1µFC14

VDIG

VDDVDIG

GND

VDIG

1.00KW

R15

GND0W

R16 SYNC

GND

1

2345

J3

GND

R18

1.00KW

R19

GND

R21

0W

R20

VDD VDIG VDD

31

2

CW

VR1

3299Y-1-501LF

3.01KW

R1

1.50KW

R2

R22

R23

VDD

31

2

CW

VR2

3299Y-1-501LF

R24

R25

0W

R4

0.1µFC15

0.1µFC16

VDIG VDD

0.1µFC18

0.1µFC17

VDIG

VDD

SH-JP1_2-3

SH-JP3_2-3

0.1µFC19

VDD

0.1µFC20

VDD

0.1µF

C21

VDD

0.1µFC22

VDIG

60 ohm

L1

CIB

CI1

F1

1206SFF200F/63-2

A3

VCCA1

B4

DIR5

GND2

VCCB6

U4

SN74LVC1T45DBVR

A3

VCCA1

B4

DIR5

GND2

VCCB6

U5

SN74LVC1T45DBVR

NC

1

GN

D2

NC

3G

AT

E4

VIN

5

U2TPS2400DBVR

3.74KW

R6

806WR7

DNI

DNIDNI

DNI

DNI

0W

R26

1.00KW

R27

DNI 1.00KW

R3

DNI

DNI

DNI

DNI

DNI

1.00KW

R10

DNI

DNI

DNI

DNI

DNI

DNI

DNI

49.9W

R17

0W

R14

PCB Schematic and Layout www.ti.com

4.1 Circuit SchematicFigure 15 and Figure 16 show the circuit schematics.

Figure 15. TIDA-00725 Laser-Driver Circuit Schematic



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1

3

2

+5V

RAPC722X

1

4

3

D1

MBRB2515LT4G

5V

GND

4

7,8 1,2,3

5,6,

Q1CSD18532Q5B

L1A1

VINA2

ENA3

GNDB1

ILIM0B2

ILIM1B3

L2C1

PFM/PWMC2

PGC3

VOUTD1

FBD2

SSD3

U2

TPS63050YFF

47µFC2

10µFC3

21 Green

+5LTST-C150KGKT

1.00KW

R1

L1 1286AS-H-1R5M

10µFC1

1000pFC4

1.05MW

R2

200KW

R3

22µFC5

FLT1NFM41PC204F1H3L

10µFC6

VAMP5.0

0.1µFC7

VAMP_5P0

GND

IN1

2

EN3

FB4

OUT5

U3

TPS79901DDCTVAMP_5P0

0.1µFC8

10.0KW

R5

1000pFC9

2.2µFC10

0.1µFC11

V3p3_1V3p3_1

17.4KW

R4

GND

IN1

2

EN3

FB4

OUT5

U4TPS79901DDCT

VAMP_5P0

0.1µFC12

10.0KW

R7

1000pFC13

2.2µFC14

0.1µFC15

V3p3_2V3p3_2

17.4KW

R6

VIN

10

ILIM1

MON4

LOS_MON2

ILIM_MON3

CT

RL

12

EN

/UV

LO

11

LO

S13

AP

D5

SW

7

LO

S_A

DJ

14

GND9

fSE

L16

FB15

MONIN6

VOUT8

DA

P17

U5LT3905EUD#PBF

5VIN L2SD3110-100-R

1.0µFC16VAMP_5P0

100KW

R8

VAMP_5P0

*ILIM

0WR910% APD

49.9KW

R10

ILIM_MON

MON

5% APD

20% APD

0.1µF

100V

C17

0R12+VAPD

VAMP_5P0

LOS

100KW

R13

VAMP_5P0

2

1

3

fSEL

CL-SB-12B-01T

VAMP_5P0

2 MHz

1 MHz

0.22µFC18

487KW

R14

15.0KWR15

PD_Anode1

PD_Cathode2

NC3

PD1

TO5-3pin

+VAPD

GND1

CTRL2

GND3

GND4

OU

T-

5

GN

D6

GN

D7

OU

T+

8

VCC9

VCC10

VCC11

GND12

TE

ST

SD

13

TE

ST

IN1

4

VIN

15

DN

I1

6

PP17

U6

OPA857

V3p3_1

GND

V3p3_1GND

Vin1_N Vin1_P

20KW

4.99KW

R17

2

1

3

Gain Control

CL-SB-12B-01T

V3p3_1

5KW

IN-3

OUT+10

FB+4

VOCM9

OUT-11

IN+2

FB-1

PD12

VS

+7

VS

+6

VS

+5

VS

+8

VS

-1

3

VS

-1

4

VS

-1

5

VS

-1

6

EP

17

U7THS4541IRGT

0.1µFC21

Vin1_N

Vin1_P

V3p3_2

49.9W

R21

49.9W

R220.1µFC22

10.0KW

R23

V3p3_2

0.1µFC23

0.1µFC24

1.00KW

1%

R24

V3p3_2

1

2345

OUT-142-0801-801

1

2345

OUT+142-0801-801

1000pFC25

0.01µF

100V

C19

R28

1

2345

VOCM

1000pFC20

F1

1206SFF200F/63-2

NC

1

GN

D2

NC

3G

AT

E4

VIN

5

U1TPS2400DBVR

Vout

Vout

0W

R30

0W

R29

20.0KW

R11

374W

R16374W

R18

2.00KWR19

2.00KWR20

0W

R25

464W

1%

R262.00KW

1%

R27

LDO for Amplifier Supplies

DNI

DNI

DNI

APD Power Supply

OPA857 Transimpedance Amplifier Stage THS4541 FDA Stage

DNI

DNI

DNI

DNI DNIDNI

www.ti.com Getting Started–System Setup

Figure 16. TIDA-00725 Signal-Chain Circuit Schematic

5 Getting Started–System SetupTo prevent damage to the sensitive optical components and ensure the software is operating in the correctmode, connect the 5-V supplies to the boards in the following order:1. TSW14J56 and ADC3k2. Laser driver3. Amplifier signal chain

5.1 Laser-Driver Board Setup1. Ensure jumpers JP1 and JP3 are grounded (JP2 is unused in this application).2. Use the VR2 potentiometer to set the voltage on CIB (pin 17) to 1.15 V ±25 mV.

NOTE: This adjustment drives approximately 10 mA of current into the LDM5S515-015 laser diode.This current puts the laser diode at its lasing threshold.

3. Use the VR1 potentiometer to set the voltage on CI1 (pin 12) to 1.65 V ±25 mV.

NOTE: This adjustment drives approximately 40 mA of signal current into the laser diode.

4. Adjust the threshold and signal-bias voltages if using another laser diode.5. Connect a short cable between J7 (TRIG OUT A) on the TSW controller board and J2 (SIGNAL EN)

on the laser-driver board to trigger the lazer diode.6. Use a short cable to minimize the delay between the ADC trigger initiating a conversion and the optical

pulse generated by the laser.



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IMONAPD

VI 5

20k= ´

W

Getting Started–System Setup www.ti.com

7. Connect JP3 to VDD to set the laser at its threshold.

5.2 Signal-Chain Board SetupPhotodiode Protection: The APD power supply self-limits its output voltage if the voltage on the ILIM_MONpin exceeds 1.248 V. For this design, the maximum current through the photodiode is limited to 500 µA bytying a 100-kΩ resistor from ILIM_MON to GND. See the LT3905 data sheet(http://cds.linear.com/docs/en/datasheet/3905fa.pdf) for more details on this function.1. Measure the output voltage on the IMON pin using a multi-meter to monitor the amount of input current

into the OPA857 transimpedance stage.

NOTE: The IMON pin sources a current proportional to 20% of the photo-diode current for externalcurrent monitoring. Tie a 20-kΩ resistor from IMON to GND to set the gain of the circuit. UseEquation 1 to calculate the photodiode current.

(1)2. Use the fSEL switch to select the frequency of the internal clock of the APD power supply (TI

performed this evaluation with f = 1 MHz; system performance was independent of the selectedfrequency).

3. Use the GAIN switch to set the transimpedance gain to 5 kΩ or 20 kΩ.4. Connect the OUT– and OUT+ SMA connectors on the signal-chain board to the SMA connectors on

the appropriate ADC3k channel.

NOTE: TI designed the connector spacing to be equal on the two boards to eliminate the need forcables thereby minimizing parasitics.

5.3 TSW14J56 + ADC3K Board and Software SetupThe ADC3k EVM accepts a single-ended signal that is converted to a differential signal using the onboardtransformers. See Table 1 for a list of BOM changes required to modify the EVM to accept the differentialoutput from the signal-chain board. The following changes are described for channel 2 of an ADC34J45EVM.

HSDC Pro software (available at http://www.ti.com/tool/dataconverterpro-sw?keyMatch=hsdc prosoftware&tisearch=Search-EN-Everything) controls the system. The firmware to perform averaging andhardware-generated triggering is proprietary and unavailable for general use. For additional firmwareinformation, contact the applications team at http://e2e.ti.com/support/amplifiers/high_speed_amplifiers/.

Table 1. BOM Modifications Required on ADC34J45 and Channel 2 to Accept Differential InputSignals

Reference Designator Default State Modified StateJ4 DNI InstallR21 DNI Install 0-Ω resistorR24 0 Ω DNIT3, T4 ADT1-1WT installed Replace the transformers with a 0-Ω shunt

across the terminals.C11, C19 0.1 µF Replace the capacitors with a 0-Ω shunt.R16, R17 49.9 Ω Replace the resistors with a 0-Ω shunt.R19, R26 29.9 Ω Replace the resistors with a 49.9-Ω shunt.R20, R27 49.9 Ω DNI



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http://cds.linear.com/docs/en/datasheet/3905fa.pdf

http://e2e.ti.com/support/amplifiers/high_speed_amplifiers/


www.ti.com Getting Started–System Setup

5.4 Setting Optical Power and Adjusting the Optical Attenuator1. Keep the optical power output from the laser diode constant during evaluation in compliance with the

settings in Section 5.1.2. Turn the knob on the variable optical attenuator (VOA) clockwise for maximum attenuation.

NOTE: This adjustment ensures there is minimal optical power incident on the APD.

See Variable Fiber Optical Inline Attenuator for details on the optical attenuator.

3. Connect a multimeter to the IMON test point on the amplifier board.4. Set jumper JP1 on the laser-diode board to VDD.

NOTE: The laser diode stays on.

5. Perform a DC measurement of the APD output current.6. Turn the knob on the VOA counterclockwise to reduce its attenuation.7. Observe the voltage reading on the multimeter.8. Use Equation 1 to calculate the APD output current.9. Remove JP1 to return control of the laser-diode driver to the trigger signal from the TSW digital-

capture card.

6 Verification and Measured PerformanceFigure 17 shows the bench setup to evaluate the performance of the system in the lab.

Figure 17. Laboratory Bench Setup of Optical Loop-Back System



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Frequency (Hz)

Out

put N

oise

(nV

/ H

z)

1

10

100

100k 1M 10M 100M

D003

5-k: TIA Gain20-k: TIA Gain

Verification and Measured Performance www.ti.com

6.1 Output Noise of Amplifier StageTI measured and compared the noise of the amplifier signal chain with the simulated measurements inFigure 10. TI found the total output noise of the system to be 365 µVRMS and 840 µVRMS for the 5-kΩand 20-kΩ transimpedance-gain settings, respectively. These findings correlate to the simulated values.The calculations assume a 135-MHz brick-wall filter. For more information, see Figure 18.

Figure 18. Measured Output Noise of Amplifier Signal Chain



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www.ti.com Verification and Measured Performance

6.2 System Output NoiseThe total output noise of the system and its components was measured using the ADC34J45. Table 2shows the results. The signal-chain noise correlates with the spectrum analyzer measurements. Becausethe photodiode is a significant contributor to the total noise of the system, TI also measured with anunilluminated photodiode.

Table 2. Output Noise of the System and Components

System Setup Output Noise (µVRMS)ADC34J45 260OPA857 (G = 5 kΩ) + THS4541 + ADC34J45 460OPA857 (G = 20 kΩ) + THS4541 + ADC34J45 1050NR7500 + OPA857 (G = 5 kΩ) + THS4541 + ADC34J45 525NR7500 + OPA857 (G = 20 kΩ) + THS4541 + ADC34J45 1300

TI measured the output noise of the system including the photodiode after averaging. Table 3 shows theresults.

Table 3. System Noise vs Number of Averages

Number of Averages Noise: 5-kΩ Gain (µVRMS) Noise: 20-kΩ Gain (µVRMS)10 165 405100 51 1271000 16.7 4110000 6 14100000 4 7.9



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Time (Ps)

Out

put V

olta

ge (

V)

0 1 2 3 4 5 6 7 8 9 10

D005

0

-50P

50P

100P

150P

200P

250P

300P

350P

400P125 mV250 mV500 mV1 V

Time (Ps)

Out

put V

olta

ge (

V)

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 410P

100P

1m

10m

100m

1

D004

125 mV250 mV500 mV950 mV


6.3 Pulse Response Measurements

6.3.1 Pulse Response vs Output VoltageTI measured the output pulse response as a function of the output voltage swing for both transimpedance-gain settings. Figure 19 plots the response with the output voltage plotted on a log-scale to accentuate thesettling performance. Figure 20 compares the settling responses for the different output voltages on alinear scale. The curves have been offset from each other by 50 µV to make comparisons easy.

Figure 19. Pulse Response vs Output Voltage, 20-kΩ Transimpedance Gain

Figure 20. Long-Term Settling Response vs Output Voltage, 20-kΩ Transimpedance Gain

Figure 21 and Figure 22 show the response for the 5-kΩ transimpedance-gain setting.



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Time (Ps)

Out

put V

olta

ge (

V)

0 1 2 3 4 5 6 7 8 9 10

D007

-50P

0P

50P

100P

150P

200P

250P

300P

350P

400P125 mV250 mV500 mV1 V

Time (Ps)

Out

put V

olta

ge (

V)

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 410P

100P

1m

10m

100m

1

D006

125 mV250 mV500 mV950 mV


Figure 21. Pulse Response vs Output Voltage, 5-kΩ Transimpedance Gain

Figure 22. Long-Term Settling Response vs Output Voltage, 5-kΩ Transimpedance Gain



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Time (Ps)

Out

put V

olta

ge (

V)

0 1 2 3 4 5 6 7 8 9 1010P

100P

1m

10m

100m

1

D012 Time (Ps)

Out

put V

olta

ge (

V)

0 1 2 3 4 5 6 7 8 9 1010P

100P

1m

10m

100m

1

D013

Time (Ps)

Out

put V

olta

ge (

V)

0 0.5 1 1.5 2 2.5 3 3.5 410P

100P

1m

10m

100m

1

D010 Time (Ps)

Out

put V

olta

ge (

V)

0 0.5 1 1.5 2 2.5 3 3.5 410P

100P

1m

10m

100m

1

D011

Time (Ps)

Out

put V

olta

ge (

V)

0 0.2 0.4 0.6 0.8 110P

100P

1m

10m

100m

1

D008 Time (Ps)

Out

put V

olta

ge (

V)

0 0.2 0.4 0.6 0.8 110P

100P

1m

10m

100m

1

D009


6.3.2 Pulse Response vs Output Pulse WidthFigures 23 through 28 show the pulse response as a function of the pulse width for the twotransimpedance-gain settings. TI adjusted the optical attenuator to drive an output voltage of 0.5 V.

Figure 23. 25-ns Pulse Width, 20-kΩ Gain Figure 24. 25-ns Pulse Width, 5-kΩ Gain

Figure 25. 250-ns Pulse Width, 20-kΩ Gain Figure 26. 250-ns Pulse Width, 5-kΩ Gain

Figure 27. 2.5-µs Pulse Width, 20-kΩ Gain Figure 28. 2.5-µs Pulse Width, 5-kΩ Gain



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Time (Ps)

Out

put V

olta

ge (

V)

0 4 8 12 16 20 24 28 32 36 4010P

100P

1m

10m

100m

1

D015

I IN = 200 PA, 1x OverloadI IN = 400 PA, 2x Overload

Time (Ps)

Out

put V

olta

ge (

V)

0 4 8 12 16 20 24 28 32 36 4010P

100P

1m

10m

100m

1

D014

I IN = 50 PA, 1x OverloadI IN = 100 PA, 2x OverloadI IN = 200 PA, 4x Overload


6.3.3 Overloaded Pulse ResponseTI also evaluated the system response for an overdriven output signal from the TIA in both gainconfigurations. TI adjusted the optical attenuator to vary the output current from the photodiode with thebias settings to the laser driver unchanged from the previous measurements and to set the pulse width to250 ns for the tests. See Figure 29 and Figure 30 for more information.

Figure 29. TIA Gain = 20 kΩ, Overloaded Response

Figure 30. TIA Gain = 5 kΩ, Overloaded Response



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Time (µs)

Out

put V

olta

ge (

V)

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 410P

100P

1m

10m

100m

1

D016

V OUT = 500 mV, No TerminationV OUT = 250 mV, 50 : TerminationV OUT = 500 mV, 50 : Termination


6.3.4 Pulse Response vs Output TerminationThe output of the THS4541 was doubly terminated at the ADC inputs through a 50-Ω resistor. Thisconfiguration creates a 6-dB loss in signal output resulting in an effective FDA gain of 2.5 V/V. TIconfigured the circuit to prevent signal reflections because of the distance between the THS4541 output,and the input of the ADC. When the THS4541 and ADC3K share the same PCB, you can eliminate thistermination. TI also measured the pulse response of the circuit without the 50-Ω termination at the ADCinput and compared the results with the earlier measurements. TI set the pulse width to 250 ns andconfigured the OPA857 in a gain of 20 kΩ. Figure 31 shows that the unterminated output does not affectthe settling performance of the system.

Figure 31. Effect of Output Termination on Settling Performance



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iC-HB 155-MHz Laser Driver Board

IBIAS

ISIG

10- to 60-VSupply

OPA857

+

-

VREF2

THS4541

+

VREF1

20 kGain = 5 V/V

Amplifier Signal Chain Board

50

50

ADC34J45

Clocking + FPGA + memory

1 N

1 NVREF2

Controller + ADC3K Board

Op

tica

l Pu

lse

Tri

gg

er

Trigger &Data Capture

Circulator

1 km Optical Fiber 1 km Optical Fiber

FiberConnector


6.4 OTDR System TestUsing the principle of Rayleigh scattering, TI used optical time-domain reflectometry (OTDR) to test andcharacterize optical cables. In a true OTDR system, light from the transmitter (usually a high-power laser)is injected into the optical fiber under test. The backscattered light from the test fiber is collected using aphoto detector that converts the optical signal into a current output, which is processed using a low-noise,high-speed signal chain. See Optical Time-Domain Reflectometer Wiki and Guide to Fiber Optics andPremises Cabling for more information on OTDR.

Figure 32 shows a block diagram of a test OTDR system. A 3-port, fiber-optic circulator (for example, seehttp://www.thorlabs.com/thorproduct.cfm?partnumber=6015-3-FC) is required for the measurement.1. Couple the output from the laser into port 1 of the circulator.2. Connect the optical fiber being tested to port 2.3. Connect port 3 to the photodiode.4. Allow light from port 1 to enter port 2 with minimal insertion loss while the light from port 1 to port

undergoes large attenuation.5. Allow the back-scattered light from port 2 to enter port 3 with minimal insertion loss but is greatly

attenuated at port-1.6. Attenuate light entering port 3 at port 1 and port 2.

For the tests in this section, the transimpedance gain was 20 kΩ. Based on the results in Section 6.3.4, TIdid not terminate the THS4541 with a 50-Ω resistor at the input of the ADC3K. This overall system gainwas 20 kΩ × 5 V/V = 100 kΩ.

Figure 32. OTDR Block Diagram



http://www.ti.com

http://www.thorlabs.com/thorproduct.cfm?partnumber=6015-3-FC


Time (Ps)

Out

put V

olta

ge (

V)

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 2510P

100P

1m

10m

100m

1

D017

2.5 Ps Pulse1.0 Ps Pulse250 ns Pulse


TI conducted several OTDR tests by varying the optical pulse-width with the results in figure 33.Increasing the pulse-width increases the amount of backscattered light incident on the photodiode. Thereare three distinct regions in the output response.• At t = 0.3 µsec, a discontinuity occurs in the backscatter due to Fresnel reflections occurring at the

opto-coupler between the laser diode and the first section of 1-km fiber. Based on the speed of light infiber (200,000 km/sec), the light takes 10 µsec to travel 1 km and return to the source.

• At t = 10.3 µsec, a second discontinuity occurs in the backscatter due to Fresnel reflections occurringat the opto-coupler between the two 1-km fibers.

• At t = 20.3 µsec, a large reflection occurs when the light encounters the unterminated end of thesecond fiber.

Figure 33. OTDR System Test vs Optical Pulse Width



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Time (Ps)

Out

put V

olta

ge (

V)

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 2510P

100P

1m

10m

100m

1

D018


With the pulse-width set at 2.5 µsec, TI retested the OTDR system. TI bent the second fiber at thecoupling between the two fibers. The increased optical attenuation at the fiber bend exists in the droop inbackscattered power at 10 µsec and in the reduced reflected power at the unterminated fiber end. SeeFigure 34 for more information.

Figure 34. OTDR Response With Bend in Optical Fiber



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O _DIFF F

I_DIFF D

V R

V R= -

ICMV 1.68 VÞ =

ICM ICM1.83 V V 0.95

40 20=

k

- -

W W

+

-

3.3 V

0.95 V

2 N

2 N

374

374

VCM = 1.83 V

RD

R'¶

VID

V,'¶

25

25

OPA857 VOUT1

VOUT2

System Enhancements www.ti.com

7 System EnhancementsIn this section, TI proposes two different methods of improving the system SNR performance.

7.1 THS4541 Level-Shift CircuitDepending on the direction of reverse-bias, a photodiode can either source or sink current. The output ofthe OPA857 swings in a negative direction from its common-mode reference voltage. When this signal isapplied to the THS4541, each of its differential outputs swings either higher or lower than its outputcommon-mode (VOCM). Due to this unipolar swing limitation, only half the input range of the ADC is used,which reduces the dynamic range of the system by 6 dB. To overcome this limitation, configure the FDAas shown in Figure 35.

Figure 35. THS4541 Level-Shift Circuit

The ADC3K has a specified maximum differential-input swing of 2 VPP on a 0.95-V common-mode input.This implies that each differential input to the ADC input can swing from 0.45 V to 1.45 V. To level-shiftthe output of the THS4541 to take advantage of the full dynamic range of the ADC, apply a differential DCinput signal (VI_DIFF = VID – VID’) to produce a 1-VPP differential output.

Calculate the input common-mode of the THS4541 from the OPA857 output as follows:

(2)

(3)

Calculate the gain of the level-shift circuit as follows:

(4)



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+

-

3.3 V

VOCMTo ADC Inputs

43 pF

40

40

300 nH

300 nH

5.2 pF 200

3rd Order, 80-MHz Bessel Filter

Time (ns)

Vol

tage

(V

)

0 25 50 75 100 125 150 175 200 225 250 275 3000.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

D019

VINPUTVOUT2VOUT1

www.ti.com System Enhancements

To reduce the noise-gain contribution from the level-shift circuit, keep its gain to a minimum. If a level-shiftcircuit gain of 0 dB is assumed, set RD = RD’ = 2 kΩ, VID = (1.68 V + 0.5 V), and VID’ = (1.68 V – 0.5 V).Figure 36 shows the simulated output for a 100-mV differential input to the THS4541 circuit. Fromsimulations, the increased noise due to the level-shift circuit is less than 6%.

Figure 36. Simulated Output Pulse of Level-Shift Circuit

7.2 Anti-Aliasing FilterTo reduce the total system noise, place a third-order, passive Bessel filter between the THS4541 andADC3K. Figure 37 shows one such implementation of the filter.

Figure 37. Anti-Alias Filter

The simulated system noise was reduced by 50% when using this anti-alias filter. The final shunt capacitorfilter (5.2 pF) must be tuned based on the differential input capacitance of the ADC. The filter introduces a3-dB insertion loss to the overall system gain.

8 ConclusionThis reference design describes a complete end-to-end optical front-end system and its performance.Various techniques to optimize the SNR performance of the signal chain are also discussed. Thisreference design provides a flexible platform, letting you change critical system components such as theamplifier chain, ADC, and the optical components.



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Design Files www.ti.com

9 Design FilesTo download the design files, see the files at TIDA-00725.

9.1 Bill of MaterialsTo download the bill of materials (BOM), see the design files at TIDA-00725.

10 References

1. Optical Time-Domain Reflectometer Wiki, https://en.wikipedia.org/wiki/Optical_time-domain_reflectometer

2. Guide to Fiber Optics and Premises Cabling, http://www.thefoa.org/tech/ref/testing/OTDR/OTDR.html3. Laser-Diode Driver, iC-HB data sheet (https://www.ichaus.de/upload/pdf/HB_datasheet_A4en.pdf)4. Laser Diode, LDM5S515 data sheet (https://www.oequest.com/getDatasheet/id/2165-

3255cfdc2f98b43.pdf)5. Variable Fiber Optical Inline Attenuator, http://www.fiberstore.com/fc-apc-to-fc-apc-variable-fiber-optic-

voa-in-line-attenuator-0-60db-p-13556.html



http://www.ti.com



http://www.thefoa.org/tech/ref/testing/OTDR/OTDR.html

https://www.ichaus.de/upload/pdf/HB_datasheet_A4en.pdf

https://www.oequest.com/getDatasheet/id/2165-3255cfdc2f98b43.pdf

https://www.oequest.com/getDatasheet/id/2165-3255cfdc2f98b43.pdf

http://www.fiberstore.com/fc-apc-to-fc-apc-variable-fiber-optic-voa-in-line-attenuator-0-60db-p-13556.html

http://www.fiberstore.com/fc-apc-to-fc-apc-variable-fiber-optic-voa-in-line-attenuator-0-60db-p-13556.html


www.ti.com About the Author

11 About the AuthorSAMIR CHERIAN is an applications engineer with TI in the high-speed amplifier division in Tucson, AZ.He validates the performance and specifications of high-speed amplifiers and provides customer supportthrough TI online forums, application notes, and reference designs.

KEN CHAN is an applications engineer with TI in the high-speed data converter product line based inDallas, TX. He supports data converter devices, systems, and solution in high-speed signal chainscovering communications and industrial applications.



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Optical Front-End System Reference Design · Laser driver Optical attenuator 10- to 60-V supply...

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