On the Model-centric Design and Development of an FPGA-based Spaceborne Downlink Board

MAPLD 2005 / 177Jones 1

On the Model-centric Design and DevelopmentOn the Model-centric Design and Developmentof an FPGA-based Spaceborne Downlink Boardof an FPGA-based Spaceborne Downlink Board

Rob Jones, Roman Machan, Tahsin Lin, and Ed Leventhal

ASRC Aerospace Corp.ASRC Aerospace Corp.

6303 Ivy Lane, Suite 8006303 Ivy Lane, Suite 800Greenbelt, MD 20770Greenbelt, MD 20770

{robert.jones, roman.machan, tahsin.lin, ed.leventhal}@akspace.com


Outline SMART Approach to Model-centric Engineering

Formal Modeling with Petri Nets

Application to an FPGA-based Downlink Design

Summary


General Petri nets

conflicts, decisions, concurrency, synchronization, …

Modern Formalisms

Finite automataFinite automata(state machines)(state machines)

conflicts/decisions but conflicts/decisions but no concurrencyno concurrency

Marked graphsMarked graphs

concurrency but no concurrency but no conflicts/decisions conflicts/decisions

Data, control, process flow graphs & queuing networks


Petri Net Bipartite graph, PN = (P, T, m0)

Set of places, P = {p1, p2, p3, p4, p5}

Set of transitions, T = {t1, t2, t3, t4, t5}

Arcs PT TP connecting Places to transitions Transitions to places

Tokens mark places and defines the notion of state

Transitions fire when sufficient tokens are present (or absent) from input places, thereby removing tokens from input places and depositing them to output places

t1

t2 t3t4

t5

p1

p2 p3

p4 p5


Reachability Graph The notion of time is introduced

with firing delays

SPNs sojourn in markings for some amount of time before transitions fire, thus movingthe net to the next marking

Firing delays may be deterministic or randomvariables

Movement of the net among markings with the passage of time gives rise to a stochastic process, which can be analyzed

p1

p2p3

p4p3 p2p5

p4p5

t1

t2 t3t4

t4t2

t2t3

t5

t3

Underlying State Machine


Model Equivalents

min(tk(p),m)·

Multi-server Queue

Petri Net

Markov Chain

n

n

2

m

1

…

0 1 2

2

3

m

m

…

m

m+1

m

…3

4

p

m


The SMART Approach

Capture – Well-defined system requirements and design specification

Validation – Modeling the right system

Verification – Modeling the system right

Analysis – Performance tradeoffs

Realization – Allocate functions to resources

Testing – Cases, coverage, and acceptance

Iteration – Repeat steps as necessary to refine modeling and design details

Integration – Aided by well-defined interfaces and architecture

Deployment – Preservation and maturation of models aid documentation, operation, and maintenance

Pet

ri N

et

Mo

del

An

alys

is a

nd

Tes

tin

g

Validation

Requirements

Sys

tem

C

VH

DL

FP

GA

Inte

grat

e

Model Checking

Exe

cutio

nS

imul

atio

nA

naly

tical

Low

-leve

lIn

term

edia

teH

igh-

leve

l

Stochastic Model-Checking Analyzer for Reliability and Timing

(SMART)


Benefits from Model Analysis

Exact state space analysis, verifies logical correctness to requirements specs

Design function and form Fault-tolerance and coverage Insight to design alternatives

Process scheduling, driven by data (control) flow and graphically embedded

Exploits hidden concurrency Determines correct, sufficient

synchronization and queuing Alternative schedules imposed via

artificial dependencies

Performability, measure of performance in the presence of faults (other “bad” events)

Availability, dependability User-defined QoS Reward (cost) of operating the

system over its mission time

Schedulability, computes graph-theoretic performance bounds of “embedded” schedule

Critical path end2end delay Critical circuit throughput Resource utilization

Qualitative Quantitative


Downlink Dataflow and Queuing

66 MW/s

VCDU Function

VCDU Function

CADUFunction

CADUFunction

Reed-Solomon Encoder

Reed-Solomon Encoder

OutputQueueOutputQueue

USESQueueUSESQueue

SerialBit

Stream

1K32

2K16 4K820 MS/s(S=samples)

20 MB/s 80 Mb/s

LSBsQueueLSBs

Queue

4K8

Input FunctionInput Function

InputQueueInput

Queue

10 MB/s

LVDS DRVRLVDS DRVR

32-bit Input Data from CompactPCI Bus

LSBs

15 bits

USESUSES

USES Bypass

Interrupt on Input Queue status or queuing errors High-speed High-speed Downlink Board Downlink Board Downlink Ready when Input Queue is at most 1/4 full

OutputData


VCDU Functional Dataflow

USESQueueUSESQueue


CounterCounter

USESUSES

Fill8

EOP

DataRdy

EndBits

Packet Word Length

16x8 bits

16x16 bits

mux

LSBsQueueLSBs

QueueInput

FunctionInput

Function

(10)

AuxiliaryQueue

AuxiliaryQueue

(1)

(5)

(8)

4Kx8 bits

4Kx8 bits

2Kx16 bits

20 MHz clock20 MB/s throughput

VCDU FunctionVCDU Functionwithin FPGAwithin FPGA

ControlControlHeadersHeaders

Idle dataIdle data

DataQueueData

Queue

Level < 1/4

(8)


BlockBufferDownlink

Input Queue

Access Bus

Input Arrival and Buffering Model

Write (32 bits)

Idle UseBus

BurstArrival

Other Use

Preempt

Resume

Busy

Active

Inactive

Downlink Ready

2

1K

Transfer Done

¼Bi + 1

State of PCI Bus

Delay

Transfers from Sensor

Module

Next Block

5 cycles 1 cycle16 Mw/s burst10 Mw/s average

(words)

word (w) = 16 bits


Input Processing Model

Each 2 KB of data is encoded into a compressed sourcepacket for CCSDS transport

16-bit words are unpacked from PCI input LSBs removed, queued, and later rejoined with packet data within

each Virtual Channel Data Unit (VCDU)

LSBsQueue

UnpackInput

Remove LSB USES

QueueInput

Queue¼Bi+1

2

2 cycles

1 cycle

Sample Data

¾Bu

LSBs

Word Data

8

USESUSES

20 Msamp/s

1 cycle

VCDU Function

VCDU Function

10 Mw/s

Write LSBs

Prevents USES Queue overflowProcess begins with sufficient data


Input Queuing Performance

High Entropy Nominal Entropy


Summary of Downlink Model Analysis

15

10

5

20

25

Maximum Entropy Rate14.7 bits/word

Ent

ropy

Rat

e (b

its p

er w

ord)

of I

R d

ata,

0.6

wav

e no

. ar

ound

ZP

D

Mea

n

(1) Input Queue

(2) USES Queue

(3) Output Queue

(4) Output to transmitter

5.9 bits/word mean

3.5 bits/word minimum


USES Entropy Encoding Model Based on the Universal Source Encoder for Space (USES) C(n) = (E(n) –1)J/16 code words per nth packet E(n) = mean entropy rate (bits/word) J = block size (samples/block)

C(n)

Block Count

SampleData

Aux Queue

USES Queue

Packet IndexRead

Sample

C(n)

1 cycle

EvaluateBlock

Encode Block

J cycles

Next Sample

2J

J

J

Word Count

n

tk tk tk

64

BlkRef·RefPac= 64 blocks/word


Detailed Functional Model of USES

Info

EvaluateBlock

Begin

RefBlock Count Insert

Code

Encoding

USES Queue

N·(J - #(Ref))

#(Ref)Reduce

Bit

Output

BlkRef

Data Ready

Write

16(b)

(1-b)

EndPac

cond(0 < #(Code) < 16, 1, 0)

Reference Count

RefPacEnd

PacketDelay

Samples

Read

J

Rice Block

IDbits

#(Code)N

#(EndPac)

#(EndPac)


USES Queuing Performance



VCDU Model

WriteVCDU

Header

StartNew

VCDU

8 cycles

Data SpaceOutputQueue

1 cycle

1092

WriteData

8

State ofWritingPackets

Start NewPacket

Writing Packet Primary

Header

1 cycle

AuxQueu

e

¾Bo

PacketLength

Data Queue

HeaderLength

Complete(variable-length)

Data PacketWrite

Header

Create(variable-length)

Data Packet

16x8 bits

6

tk tk 2tk

VCDUHeaderVCDU

Header

PacketPrimaryHeader

PacketPrimaryHeader

PacketSecondar

yHeader

PacketSecondar

yHeader

Packet Data SpacePacket Data Space

8 bytes 6 bytes 1 byte 1,085 bytes


Data Packet Creation Model

WritePacket

SecondaryHeader

128

WriteLSBs

tk(Packet Length)

WriteUSESPacket

Packet Length tk(Packet Length)

DataQueue

USESQueue

LSBsQueue

AuxQueue

2

2 cycles¾Bd

¾Bd

StartNew

Packet

¾Bd 1 cycle1 cycle

Complete(Compressed)Data Packet

#

First

Second

Third

Last

2

#


Synchronous CADU Model

Channel Access Data Units(CADUs) are RS protected, sync prefixed, and 1264 bytes long

Output Queueis demand drivenby synchronous CADUs to maintain80 Mb/s output bit-data stream

VCDU Function

VCDU Function


Standard FIFO

(4Kx8 bits)

20 MHz20 MBps throughput

10 MHz10 MBps input rate80 Mbps output rateAdds 4 byte Attached Sync Marker1264 clock cycles of work

Data

ClockCADU Function

CADU Function

Reed-SolomonEncoder

Reed-SolomonEncoder

10 MHzAdds 160 byte RS code1 cycle per byte delay,1100 + 160 cycles total

80 Mbps80 MHz nom

WriteRS Code and ASM

ReadVCDU

Output Queue 1100

1100

VCDU Length (bytes)

1 cycle

164 cycles

Demands steady supply

of VCDUs


Output Queuing Performance



Summary Petri net modeling with the SMART tool provides a

formal (mathematical and therefore unambiguous) description of a system throughout its development

The engineering process therefore benefits from

Ensuring precise requirements specification

Model checking to ensure logical correctness

Quantified QoS measures that facilitate trade studies

Rapid, model-based prototyping before committing to hardware or software

Successfully applied to an FPGA-based downlink system designed for space applications

On the Model-centric Design and Development of an FPGA-based Spaceborne Downlink Board

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