On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming Petr...
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Transcript of On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming Petr...
On Logic SynthesisOn Logic Synthesisof Conventionally Hard of Conventionally Hard
to Synthesize Circuits Using to Synthesize Circuits Using Genetic ProgrammingGenetic Programming
Petr Fišer, Jan SchmidtFaculty of Information Technology, Czech Technical University in
[email protected], [email protected]
Zdeněk Vašíček, Lukáš SekaninaFaculty of Information Technology, Brno University of Technology
DDECS’10DDECS’10 22
OutlineOutline
Motivation
Hard to Synthesize Circuits
Cartesian Genetic Programming
Experimental Results
Conclusions
DDECS’10DDECS’10 33
MotivationMotivation
Target: synthesis (minimization) of combinational circuits – multi-level networks
Problem: conventional synthesis tools “fail” on some circuits. Synthesized networks are sometimes orders of
magnitude larger the expected size Synthesis fails even for very small circuits
There is a class of hard to synthesize circuits
Genetic programming could help
DDECS’10DDECS’10 44
Hard to Synthesize CircuitsHard to Synthesize Circuits
Several classes of such:
LEKO and LEKU benchmarks
Realistic LEKU benchmarks
Difficult standard benchmark circuits
Parity benchmark circuits
Tautology and near-tautology circuits
DDECS’10DDECS’10 55
LEKO and LEKU BenchmarksLEKO and LEKU BenchmarksLogic Examples with Known Optimum (LEKO)Logic Examples with Known Upper Bound (LEKU)
Published inJ. Cong and K. Minkovich, “Optimality study of logic synthesis for LUT-based FPGAs”, IEEE Trans. CAD, vol. 26, pp. 230–239, Feb. 2007
Originally for testing LUT mappersConstruction:
1. Small artificial circuit (7 LUTs)is replicated (e.g. 10-times)
2. The network is collapsed into a two-levelrepresentation
3. It is mapped into 2-input gates Large circuit is obtained
Both commercial and academic tools produce results 500-times the optimum size!
synthesis fails, because of the circuit is large
DDECS’10DDECS’10 66
Realistic LEKU BenchmarksRealistic LEKU Benchmarks
Cong’s benchmarks are artificial
However, the same benchmark generation process (collapsing & mapping) may be applied to any circuit
For most of real circuits, collapsing & mapping produces large networks as well
… and the consequences are the same:
synthesis fails, because of the circuit is large
DDECS’10DDECS’10 77
Difficult Standard Benchmark Difficult Standard Benchmark CircuitsCircuits
Some circuits from standard banchmark sets (LGSynth, ISCAS, IWLS, MCNC) are hard to synthesize as well
Mostly because XOR decomposition is needed
In most of available synthesis tools it is not supported
synthesis fails, even for small circuits
DDECS’10DDECS’10 88
Parity Benchmark CircuitsParity Benchmark Circuits
The above-mentioned problem can be artificially induced for any circuit:
1. A parity tree is appended to the circuit2. The network is collapsed into
a two-level representation3. It is mapped into 2-input gates Sometimes a large circuit is obtained, sometimes not
XOR decomposition capability is necessary to obtain good results
synthesis fails, for both small and big circuits
x1
corecircuit
xn
y1
ym
XOR
DDECS’10DDECS’10 99
Tautology and Near-Tautology Tautology and Near-Tautology CircuitsCircuits
Artificially large representations of small circuits:
Random SOP with many terms is generated This SOP is tautology, or near-tautology (only few
minterms missing to tautology) This SOP is mapped into 2-input gates
The circuit is a constant (or just a few gates). Synthesis tools are not able to discover it, because of the representation is too large
synthesis fails, because of the circuit is large
DDECS’10DDECS’10 1010
Motivation, cont.Motivation, cont.
Common properties of all these classes: We know the complexity upper bound, which is rather
small Standard synthesis fails
There is a need for universal synthesis process able to efficiently handle any kind of circuits, regardless their nature, structure, etc.
Genetic programming becomes a candidate, since all synthesis processes are
being done implicitly
DDECS’10DDECS’10 1111
Cartesian Genetic Programming (CGP)Cartesian Genetic Programming (CGP)
The circuit is modeled as a 2-dimensional array of programmable elementsThe chromosome describes the interconnection and element (gate) types its size is fixedThe size of the phenotype is variable
DDECS’10DDECS’10 1212
Cartesian Genetic Programming (CGP)Cartesian Genetic Programming (CGP)
The algorithm
1. The initial population of 1+ individuals is generated (randomly or using a conventional synthesis)
2. Evaluate the population3. Select the highest scored individual – parent4. Use mutation to create offspring of the parent
individual5. Create the new population using the parent and its
offspring6. If the termination criterion is not satisfied, go to step 2.
DDECS’10DDECS’10 1313
Cartesian Genetic Programming (CGP)Cartesian Genetic Programming (CGP)
Mutation
DDECS’10DDECS’10 1414
Cartesian Genetic Programming (CGP)Cartesian Genetic Programming (CGP)
Fitness
Should reflect the circuit (phenotype) size
Must reflect, if the circuit is functionally equivalent to the original
Could reflect the “distance” to the original
DDECS’10DDECS’10 1515
Cartesian Genetic Programming (CGP)Cartesian Genetic Programming (CGP)
Fitness
Should reflect the circuit (phenotype) size The number of gates is subtracted from the fitness value
Must reflect, if the circuit is functionally equivalent to the original
Could reflect the “distance” to the original
DDECS’10DDECS’10 1616
Cartesian Genetic Programming (CGP)Cartesian Genetic Programming (CGP)
Fitness
Should reflect the circuit (phenotype) size The number of gates is subtracted from the fitness value
Must reflect, if the circuit is functionally equivalent to the original Invalid individuals are assigned zero fitness
Could reflect the “distance” to the original
DDECS’10DDECS’10 1717
Cartesian Genetic Programming (CGP)Cartesian Genetic Programming (CGP)
Fitness
Should reflect the circuit (phenotype) size The number of gates is subtracted from the fitness value
Must reflect, if the circuit is functionally equivalent to the original Invalid individuals are assigned zero fitness
Could reflect the “distance” to the original fitness = B + (u.v - g)
B – number of correct bits, out of 2n
u, v – dimensions of the array
g – number of gates
DDECS’10DDECS’10 1818
ExperimentsExperimentsExperimental setup
ABC is used for conventional synthesis Extended “choice” script used for the circuit optimization Iterated 1000-times Mapping into 2-input gates (AND, NAND, OR, NOR, NOR,
XNOR)
Cartesian Genetic Programming v = 1 (number of rows) u = L (number of columns / levels) Fitness = number of gates, invalid individuals are assigned zero
fitness. SAT-based equivalence checking is used = 2 (offsprings) Run for 5 hours
DDECS’10DDECS’10 1919
ExperimentsExperimentsCGP Used as a Primary Optimization Process
Name ni no original ABC CGP CGP vs. ABC
9sym 9 1 329 280 27 10%
9sym_p_c 9 1 217 214 37 17%
alu1_p_c 12 1 1085 795 52 7%
big_pla 25 1 15744 14940 24 0%
c8_p_c 28 1 1605 486 71 15%
cc_p_c 21 1 799 347 36 10%
count_p_c 35 1 1608 921 78 8%
in6_p_c 33 1 5046 2386 798 33%
rd84 8 4 713 395 31 8%
s1238_p_c 32 1 66633 52590 35116 67%
s298_p_c 17 1 2294 1483 52 4%
s344_p_c 24 1 3387 1910 76 4%
s349_p_c 24 1 3619 1950 79 4%
s420_p_c 35 1 2535 1175 141 12%
signet_p_c 39 1 49167 36974 45143 122%
t481 16 1 1263 420 21 5%
taut1 25 1 15397 14583 1 0%
term1_p_c 34 1 2397 918 80 9%
DDECS’10DDECS’10 2020
ExperimentsExperimentsCGP Used as a Primary Optimization Process
0 200 400 600 800 10000
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
5500
in6_p_c
Gat
es
Iteration
0 1M 2M 3M 4M 5M 6M 7M0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
5500
in6_p_c
Gat
es
Iteration
ABC CGP
Convergence curves
DDECS’10DDECS’10 2121
ExperimentsExperimentsCGP Used for a Post-Synthesis Optimization
First, the circuit was synthesized using conventional synthesis tools, the “best” conventional synthesis process possible was used
Then it was optimized by CGP
Name ni nogates Best conv. Best conv. + CGP Impr.
9sym 9 1 329 57 48 16%
9sym_p_c 9 1 217 57 46 19%
b4_p_c 33 1 9645 279 98 65%
big_pla 25 1 15744 29 24 17%
cc_p_c 21 1 799 54 36 33%
in6_p_c 33 1 5046 118 106 10%
LEKU-CB 25 25 759 235 181 23%
rd84 8 4 713 85 32 62%
s1238_p_c 32 1 66633 1916 897 53%
s420.1_p_c 34 1 4098 80 80 0%
s420_p_c 35 1 2535 123 108 12%
signet_p_c 39 1 49167 8304 7453 10%
term1_p_c 34 1 2397 136 95 30%
DDECS’10DDECS’10 2222
ConclusionsConclusions
A circuit optimization method based on Cartesian genetic programming (CGP) was proposedCGP is able to implicitly discover “good” circuit structures it is the sought universal synthesis processCGP significantly outperforms conventional synthesis toolsThis is especially apparent for hard-to-synthesize circuitsCGP may be advantageously used for post-synthesis optimizationThe CGP iterative strength is much higher than the iterative strength of the ABC iterative synthesis process
CGP can produce better and better results for a cost of a runtime, whereas ABC gets quickly stuck in a local optimum