OMAP35x Technical Reference Manual

OMAP35x Applications Processor

Technical Reference Manual

Literature Number: SPRUF98L April 2010 Revised November 2010

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SPRUF98L April 2010 Revised November 2010 Submit Documentation FeedbackCopyright 2010, Texas Instruments Incorporated

ContentsPreface 1

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.................................................................................................................................... Introduction .................................................................................................................... 1.1 Overview .................................................................................................................. 1.1.1 OneDRAM Implementation .................................................................................... 1.2 Environment .............................................................................................................. 1.3 Description ................................................................................................................ 1.3.1 MPU Subsystem ................................................................................................ 1.3.2 IVA2.2 Subsystem .............................................................................................. 1.3.3 On-Chip Memory ................................................................................................ 1.3.4 External Memory Interfaces ................................................................................... 1.3.5 DMA Controllers ................................................................................................. 1.3.6 POWERVR SGX Graphics Accelerator subsystem (GPU) ............................................. 1.3.7 Multimedia Accelerators ........................................................................................ 1.3.8 Comprehensive Power Management ......................................................................... 1.3.9 Peripherals ....................................................................................................... 1.4 Package-On-Package Concept ........................................................................................ 1.5 OMAP35x Family ........................................................................................................ 1.5.1 Device Features ................................................................................................. 1.5.2 Device Identification ............................................................................................ 1.5.2.1 720MHz Device Identification ........................................................................... 1.5.2.1.1 Procedure for Calculation of SmartReflex nValue for OPP6 ................................... 1.5.3 General Recommendations Relative to Unavailable Features/Modules ................................. Memory Mapping ............................................................................................................. 2.1 Introduction ............................................................................................................... 2.2 Global Memory Space Mapping ....................................................................................... 2.3 L3 and L4 Memory Space Mapping ................................................................................... 2.3.1 L3 Memory Space Mapping ................................................................................... 2.3.2 L4 Memory Space Mapping ................................................................................... 2.3.2.1 L4-Core Memory Space Mapping ...................................................................... 2.3.2.2 L4-Wakeup Memory Space Mapping .................................................................. 2.3.2.3 L4-Peripheral Memory Space Mapping ................................................................ 2.3.2.4 L4-Emulation Memory Space Mapping ................................................................ 2.3.3 Register Access Restrictions .................................................................................. 2.4 IVA2.2 Subsystem Memory Space Mapping ......................................................................... 2.4.1 IVA2.2 Subsystem Internal Memory and Cache Allocation ............................................... 2.4.1.1 IVA2.2 Subsystem Memory Hierarchy ................................................................. 2.4.1.2 IVA2.2 Cache Allocation ................................................................................. 2.4.2 DSP Access to L2 Memories .................................................................................. 2.4.2.1 DSP Access to L2 ROM ................................................................................. 2.4.2.2 DSP Access to L2 RAM ................................................................................. 2.4.3 DSP and EDMA Access to Memories and Peripherals .................................................... 2.4.4 L3 Interconnect View of the IVA2.2 Subsystem Memory Space ......................................... 2.4.5 DSP View of the IVA2.2 Subsystem Memory Space ....................................................... 2.4.6 EDMA View of the IVA2.2 Subsystem Memory Space .................................................... MPU Subsystem ..............................................................................................................Contents

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3.1

3.2

3.3

3.4

MPU Subsystem Overview ............................................................................................. 3.1.1 Introduction ...................................................................................................... 3.1.2 Features .......................................................................................................... MPU Subsystem Integration ............................................................................................ 3.2.1 MPU Subsystem Clock and Reset Distribution ............................................................. 3.2.1.1 Clock Distribution ......................................................................................... 3.2.1.2 Reset Distribution ......................................................................................... 3.2.2 ARM Subchip .................................................................................................... 3.2.2.1 ARM Overview ............................................................................................ 3.2.2.2 ARM Description .......................................................................................... 3.2.2.2.1 Public ARM Cortex-A8 Instruction, Data, and Private Peripheral Port ........................ 3.2.2.2.2 MPU Subsystem Features .......................................................................... 3.2.2.3 Clock, Reset, and Power Management ................................................................ 3.2.2.3.1 Clocks .................................................................................................. 3.2.2.3.2 Reset ................................................................................................... 3.2.2.3.3 Power Management ................................................................................. 3.2.3 AXI2OCP and I2Async Bridges ............................................................................... 3.2.3.1 Bridges Overview ......................................................................................... 3.2.3.2 AXI2OCP Description .................................................................................... 3.2.3.3 Clocks, Reset, and Power Management .............................................................. 3.2.3.3.1 Clocks .................................................................................................. 3.2.3.3.2 Reset ................................................................................................... 3.2.3.3.3 Power Management ................................................................................. 3.2.4 Interrupt Controller .............................................................................................. 3.2.4.1 Clocks ...................................................................................................... 3.2.4.2 Reset ....................................................................................................... 3.2.4.3 Power Management ...................................................................................... MPU Subsystem Functional Description .............................................................................. 3.3.1 Interrupts ......................................................................................................... 3.3.2 Power Management ............................................................................................ 3.3.2.1 Power Domains ........................................................................................... 3.3.2.2 Power States .............................................................................................. 3.3.2.3 Power Modes .............................................................................................. 3.3.2.4 Transitions ................................................................................................. MPU Subsystem Basic Programming Model ......................................................................... 3.4.1 Clock Control .................................................................................................... 3.4.2 MPU Power Mode Transitions ................................................................................ 3.4.2.1 Basic Power-On Reset ................................................................................... 3.4.2.2 MPU to Standby Mode ................................................................................... 3.4.2.3 MPU Out of Standby Mode .............................................................................. 3.4.2.4 MPU Power-On from a Powered-Off State ............................................................ 3.4.3 Neon Power Mode Transition ................................................................................. 3.4.4 ARM Programming Model ..................................................................................... Introduction to Power Management ................................................................................... 4.1.1 Goal of Power Management ................................................................................... 4.1.2 Power-Management Techniques ............................................................................. 4.1.2.1 Dynamic Voltage and Frequency Scaling ............................................................. 4.1.2.2 Dynamic Power Switching ............................................................................... 4.1.2.3 Standby Leakage Management ......................................................................... 4.1.2.4 DPS Versus SLM ......................................................................................... 4.1.2.5 Combining Power-Management Techniques ......................................................... 4.1.3 Architectural Blocks for Power Management ................................................................

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Power, Reset and Clock Management4.1

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4.2

4.3

4.4

4.5

4.1.3.1 Clock Domain ............................................................................................. 4.1.3.2 Power Domain ............................................................................................ 4.1.3.3 Voltage Domain ........................................................................................... 4.1.4 Device Power-Management Architecture .................................................................... 4.1.4.1 Module Interface and Functional Clocks ............................................................... 4.1.4.2 Autoidle Clock Control ................................................................................... PRCM Overview ......................................................................................................... 4.2.1 Introduction ...................................................................................................... 4.2.2 PRCM Features ................................................................................................. PRCM Environment ...................................................................................................... 4.3.1 External Clock Signals ......................................................................................... 4.3.2 External Reset Signals ......................................................................................... 4.3.3 External Power Signals ........................................................................................ PRCM Integration ........................................................................................................ 4.4.1 Power-Management Scheme, Reset, and Interrupt Requests ............................................ 4.4.1.1 Power Domain ............................................................................................ 4.4.1.2 Resets ...................................................................................................... 4.4.1.3 Interrupt Requests ........................................................................................ PRCM Reset Manager Functional Description ....................................................................... 4.5.1 Overview ......................................................................................................... 4.5.2 General Characteristics of Reset Signals .................................................................... 4.5.2.1 Scope ....................................................................................................... 4.5.2.2 Occurrence ................................................................................................ 4.5.2.3 Source Type ............................................................................................... 4.5.3 Reset Sources ................................................................................................... 4.5.3.1 Global Reset Sources .................................................................................... 4.5.3.2 Local Reset Sources ..................................................................................... 4.5.4 Reset Distribution ............................................................................................... 4.5.5 Power Domain Reset Descriptions ........................................................................... 4.5.5.1 MPU Power Domain ...................................................................................... 4.5.5.2 NEON Power Domain .................................................................................... 4.5.5.3 IVA2 Power Domain ...................................................................................... 4.5.5.4 CORE Power Domain .................................................................................... 4.5.5.5 DSS Power Domain ...................................................................................... 4.5.5.6 CAM Power Domain ...................................................................................... 4.5.5.7 USBHOST Power Domain ............................................................................... 4.5.5.8 SGX Power Domain ...................................................................................... 4.5.5.9 WKUP Power Domain .................................................................................... 4.5.5.10 PER Power Domain ...................................................................................... 4.5.5.11 DPLL Power Domains .................................................................................... 4.5.5.12 EFUSE Power Domain ................................................................................... 4.5.5.13 BANDGAP Logic .......................................................................................... 4.5.5.14 External Warm Reset Assertion ........................................................................ 4.5.6 Reset Logging ................................................................................................... 4.5.6.1 PRCM Reset Logging Mechanism ..................................................................... 4.5.6.2 SCM Reset Logging ...................................................................................... 4.5.7 Reset Management Overview ................................................................................. 4.5.8 Reset Summary ................................................................................................. 4.5.9 Reset Sequences ............................................................................................... 4.5.9.1 Power-Up Sequence ..................................................................................... 4.5.9.2 Global Warm Reset Sequence .......................................................................... 4.5.9.3 IVA2.2 Subsystem Power-Up Sequence .............................................................. 4.5.9.4 IVA2 Software Reset Sequence ........................................................................Contents

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4.7

4.5.9.5 IVA2 Global Warm Reset Sequence ................................................................... 4.5.9.6 IVA2 Power Domain Wake-Up Cold Reset Sequence ............................................... PRCM Power Manager Functional Description ...................................................................... 4.6.1 Overview ......................................................................................................... 4.6.1.1 Introduction ................................................................................................ 4.6.1.2 Device Partitioning ........................................................................................ 4.6.1.3 Memory and Logic Power Management ............................................................... 4.6.1.4 Power Domain States .................................................................................... 4.6.1.5 Power State Transitions ................................................................................. 4.6.1.6 Device Power Modes ..................................................................................... 4.6.1.7 Isolation Between Power Domains ..................................................................... 4.6.2 Power Domain Implementation ............................................................................... 4.6.2.1 Device Power Domains .................................................................................. 4.6.2.2 Power Domain Memory Status ......................................................................... 4.6.2.3 Power Domain State Transition Rules ................................................................. 4.6.2.4 Power Domain Dependencies .......................................................................... 4.6.2.5 Power Domain Controls .................................................................................. 4.6.2.5.1 Power Domain Hardware Control .................................................................. 4.6.2.5.2 Power Domain Software Controls .................................................................. PRCM Clock Manager Functional Description ....................................................................... 4.7.1 Overview ......................................................................................................... 4.7.1.1 Interface and Functional Clocks ........................................................................ 4.7.2 External Clock I/Os ............................................................................................. 4.7.2.1 External Clock Inputs ..................................................................................... 4.7.2.1.1 32-kHz Always-On Clock ............................................................................ 4.7.2.1.2 High-Frequency System Clock ..................................................................... 4.7.2.1.3 Alternate Clock ....................................................................................... 4.7.2.2 External Clock Outputs .................................................................................. 4.7.2.3 Summary ................................................................................................... 4.7.3 Internal Clock Generation ...................................................................................... 4.7.3.1 PRM ........................................................................................................ 4.7.3.2 CM .......................................................................................................... 4.7.3.3 DPLLs ...................................................................................................... 4.7.3.3.1 DPLL1 (MPU) and DPLL2 (IVA2) .................................................................. 4.7.3.3.2 DPLL3 (CORE) ....................................................................................... 4.7.3.3.3 DPLL4 (Peripherals) ................................................................................. 4.7.3.3.4 DPLL5 (Peripherals) ................................................................................. 4.7.3.3.5 DPLL Clock Summary ............................................................................... 4.7.3.4 Summary ................................................................................................... 4.7.4 Clock Distribution ............................................................................................... 4.7.4.1 Power Domain Clock Distribution ....................................................................... 4.7.4.1.1 MPU Power Domain ................................................................................. 4.7.4.1.2 IVA2 Power Domain ................................................................................. 4.7.4.1.3 SGX Power Domain ................................................................................. 4.7.4.1.4 CORE Power Domain ............................................................................... 4.7.4.1.5 EFUSE Power Domain .............................................................................. 4.7.4.1.6 DSS Power Domain .................................................................................. 4.7.4.1.7 CAM Power Domain ................................................................................. 4.7.4.1.8 USBHOST Power Domain .......................................................................... 4.7.4.1.9 WKUP Power Domain ............................................................................... 4.7.4.1.10 PER Power Domain ................................................................................. 4.7.4.1.11 DPLL Domains ....................................................................................... 4.7.4.2 Clock Distribution Summary .............................................................................

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4.9 4.10

4.7.4.2.1 Power Domain Source Clocks ...................................................................... 4.7.4.2.2 Peripheral Module Clocks ........................................................................... 4.7.5 External Clock Controls ........................................................................................ 4.7.5.1 Clock Request (sys_clkreq) Control .................................................................... 4.7.5.2 System Clock Oscillator Control ........................................................................ 4.7.5.3 External Output Clock1 (sys_clkout1) Control ........................................................ 4.7.5.4 External Output Clock2 (sys_clkout2) Control ........................................................ 4.7.6 DPLL Control .................................................................................................... 4.7.6.1 DPLL Multiplier and Divider Factors .................................................................... 4.7.6.2 DPLL Modes ............................................................................................... 4.7.6.3 DPLL Low-Power Mode .................................................................................. 4.7.6.4 DPLL Clock Path Power Down ......................................................................... 4.7.6.5 Recalibration .............................................................................................. 4.7.6.6 DPLL Programming Sequence ......................................................................... 4.7.7 Internal Clock Controls ......................................................................................... 4.7.7.1 PRM Source-Clock Controls ............................................................................ 4.7.7.2 CM Source-Clock Controls .............................................................................. 4.7.7.3 Common Interface Clock Controls ...................................................................... 4.7.7.4 DPLL Source-Clock Controls ............................................................................ 4.7.7.5 SGX Power Domain Clock Controls .................................................................... 4.7.7.6 CORE Power Domain Clock Controls ................................................................. 4.7.7.7 EFUSE Power Domain Clock Controls ................................................................ 4.7.7.8 DSS Power Domain Clock Controls .................................................................... 4.7.7.9 CAM Power Domain Clock Controls ................................................................... 4.7.7.10 USBHOST Power Domain Clock Controls ............................................................ 4.7.7.11 WKUP Power Domain Clock Controls ................................................................. 4.7.7.12 PER Power Domain Clock Controls .................................................................... 4.7.8 Clock Configurations ............................................................................................ 4.7.8.1 Processor Clock Configurations ........................................................................ 4.7.8.2 Interface and Peripheral Functional Clock Configurations .......................................... PRCM Idle and Wake-Up Management .............................................................................. 4.8.1 Overview ......................................................................................................... 4.8.2 Sleep Transition ................................................................................................. 4.8.3 Wakeup ........................................................................................................... 4.8.4 Device Wake-Up Events ....................................................................................... 4.8.5 Sleep and Wake-Up Dependencies .......................................................................... 4.8.5.1 Sleep Dependencies ..................................................................................... 4.8.5.2 Wake-Up Dependencies ................................................................................. 4.8.6 USBHOST/USBTLL Save-and-Restore Management ..................................................... 4.8.6.1 USBHOST SAR Sequences ............................................................................ 4.8.6.1.1 Save Sequence on Sleep Transition .............................................................. 4.8.6.1.2 Restore Sequence on Wake-Up Transition ....................................................... 4.8.6.2 USB TLL SAR Sequences ............................................................................... 4.8.6.2.1 Save Sequence on Sleep Transition .............................................................. 4.8.6.2.2 Restore Sequence on Wake-Up Transition ....................................................... PRCM Interrupts ......................................................................................................... PRCM Voltage Management Functional Description ............................................................... 4.10.1 Overview ........................................................................................................ 4.10.2 Voltage Domains ............................................................................................... 4.10.3 Voltage Domain Dependencies .............................................................................. 4.10.4 Voltage-Control Architecture ................................................................................. 4.10.5 VDD1 and VDD2 Control ..................................................................................... 4.10.5.1 Direct Control With VMODE Signals ...................................................................Contents

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4.12

4.10.5.2 Direct Voltage Control With I C Interface .............................................................. 4.10.5.3 Voltage Controller and Dedicated I2C Interface ....................................................... 4.10.6 Analog Cells, LDOs, and Level Shifter Controls ........................................................... 4.10.6.1 SRAM Voltage Control ................................................................................... 4.10.6.2 Wake-Up and Emulation Voltage Control ............................................................. PRCM Off-Mode Management ......................................................................................... 4.11.1 Overview ........................................................................................................ 4.11.2 Device Off-Mode Configuration .............................................................................. 4.11.2.1 Overview ................................................................................................... 4.11.2.2 I/O Wake-Up Mechanism ................................................................................ 4.11.3 CORE Power Domain Off-Mode Sequences ............................................................... 4.11.3.1 Sleep Sequences (Transition From On to Retention/Off) ........................................... 4.11.3.2 Wake-Up Sequences (Transition From Retention/Off to On) ....................................... 4.11.4 Device Off-Mode Sequences ................................................................................. 4.11.4.1 Sleep Sequences ......................................................................................... 4.11.4.1.1 Device Off-Mode Transition Without Using the SYS_OFF_MODE Signal ................... 4.11.4.1.2 Device Off-Mode Transition Using Only the SYS_OFF_MODE Signal ....................... 4.11.4.2 Wake-Up Sequences ..................................................................................... 4.11.4.2.1 Device Wakeup from Off Mode Without Using the SYS_OFF_MODE Signal ............... 4.11.4.2.2 Device Wakeup From Off Mode Using Only the SYS_OFF_MODE Signal .................. PRCM Basic Programming Model ..................................................................................... 4.12.1 Global Registers ............................................................................................... 4.12.1.1 Revision Information Registers ......................................................................... 4.12.1.2 PRCM Configuration Registers ......................................................................... 4.12.1.3 Interrupt Configuration Registers ....................................................................... 4.12.1.3.1 MPU Interrupt Event Sources ...................................................................... 4.12.1.3.2 MPU Interrupt Registers ............................................................................ 4.12.1.3.3 IVA2.2 Interrupt Event Sources .................................................................... 4.12.1.3.4 IVA2 Interrupt Registers ............................................................................. 4.12.1.4 Event Generator Control Registers ..................................................................... 4.12.1.5 Output Signal Polarity Control Registers .............................................................. 4.12.1.5.1 CM_POLCTRL (CM Polarity Control Register) .................................................. 4.12.1.5.2 PRM_POLCTRL (PRM Polarity Control Register) ............................................... 4.12.1.6 SRAM Precharge Time Control Register .............................................................. 4.12.1.6.1 PRM_SRAM_PCHARGE (Voltage SRAM Precharge Counter Register) .................... 4.12.2 Clock Management Registers ................................................................................ 4.12.2.1 System Clock Control Registers ........................................................................ 4.12.2.1.1 PRM_CLKSRC_CTRL (Clock Source Control Register) ....................................... 4.12.2.1.2 PRM_CLKSETUP (Source-Clock Setup Register) .............................................. 4.12.2.1.3 PRM_CLKSEL (Source-Clock Selection Register) .............................................. 4.12.2.2 External Clock Output Control Registers .............................................................. 4.12.2.2.1 PRM_CLKOUT_CTRL (Clock Out Control Register) ............................................ 4.12.2.2.2 CM_CLKOUT_CTRL (Clock Out Control Register) ............................................. 4.12.2.3 DPLL Clock Control Registers .......................................................................... 4.12.2.3.1 CM_CLKSELn_PLL_ (Processor DPLL Clock Selection Register) ... 4.12.2.3.2 CM_CLKSELn_PLL (DPLL Clock Selection Register) .......................................... 4.12.2.3.3 CM_CLKEN_PLL_ (Processor DPLL Clock Enable Register) ......... 4.12.2.3.4 CM_CLKEN_PLL (DPLL Enable Register) ....................................................... 4.12.2.3.5 CM_AUTOIDLE_PLL_ (Processor DPLL Autoidle Register) ........... 4.12.2.3.6 CM_AUTOIDLE_PLL (DPLL Autoidle Register) ................................................. 4.12.2.3.7 CM_AUTOIDLE1_PLL (DPLL5 Autoidle Register) .............................................. 4.12.2.3.8 CM_IDLEST_CKGEN (Source-Clock Idle-Status Register) .................................... 4.12.2.3.9 CM_IDLEST2_CKGEN (DPLL5 Source-Clock Idle-Status Register) .........................2

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4.13

4.12.2.3.10 CM_IDLEST_PLL_ (Processor DPLL Idle-Status Register) .......... 398 4.12.2.4 Power-Domain Clock Control Registers ............................................................... 398 4.12.2.4.1 CM_CLKSEL_ (Clock Select Register) ...................................... 398 4.12.2.4.2 CM_FCLKEN_ (Functional Clock Enable Register) ........................ 399 4.12.2.4.3 CM_ICLKEN_ (Interface Clock Enable Register) ........................... 399 4.12.2.4.4 CM_AUTOIDLE_ (Autoidle Register) ......................................... 400 4.12.2.4.5 CM_IDLEST_ (Idle-Status Register) ......................................... 400 4.12.2.4.6 CM_CLKSTCTRL_ (Clock State Control Register) ......................... 401 4.12.2.4.7 CM_CLKSTST_ (Clock State Status Register) ............................. 402 4.12.2.4.8 CM_SLEEPDEP_ (Sleep Dependency Control Register) ................. 402 4.12.2.5 Domain Wake-Up Control Registers ................................................................... 403 4.12.2.5.1 PM_WKEN_ (Wake-Up Enable Register) ................................... 403 4.12.2.5.2 PM_WKST_ (Wake-Up Status Register) .................................... 404 4.12.2.5.3 PM_WKDEP_ (WakeUp Dependency Register) .......................... 404 4.12.2.5.4 PM_ GRPSEL_ (Processor Group Selection Register) .......................................................................................................... 405 4.12.3 Reset Management Registers ................................................................................ 406 4.12.3.1 Reset Control .............................................................................................. 406 4.12.3.1.1 PRM_RSTTIME (Reset Time Register) ........................................................... 406 4.12.3.1.2 RM_RSTCTRL_ (Reset Control Register) ................................... 406 4.12.3.1.3 RM_RSTST_ (Reset Status Register) ....................................... 406 4.12.4 Power Management Registers ............................................................................... 408 4.12.4.1 PM_PWSTCTRL_ (Power State Control Register) .............................. 408 4.12.4.2 PM_PWSTST_ (Power State Status Register) .................................. 410 4.12.4.3 PM_PREPWSTST_ (Previous Power State Status Register) ................. 411 4.12.5 Voltage Management Registers ............................................................................. 411 4.12.5.1 External Voltage Control Register Descriptions ...................................................... 411 4.12.5.1.1 PRM_VOLTSETUP (Voltage Setup Time Register) ............................................. 411 4.12.5.1.2 PRM_VOLTOFFSET (Voltage Offset Register) .................................................. 412 4.12.5.1.3 PRM_VOLTCTRL (Voltage Source Control Register) .......................................... 413 4.12.5.2 Voltage Controller Registers ............................................................................ 413 4.12.5.2.1 PRM_VC_SMPS_SA (Voltage Controller SMPS Slave Address Register) .................. 414 4.12.5.2.2 PRM_VC_SMPS_VOL_RA (Voltage Controller SMPS Voltage Register Address Register) .......................................................................................................... 414 4.12.5.2.3 PRM_VC_SMPS_CMD_RA (Voltage Controller SMPS Command Register Address Register) .......................................................................................................... 414 4.12.5.2.4 PRM_VC_CMD_VAL_0 and PRM_VC_CMD_VAL_1 (Voltage Controller Command and Voltage Value Register 0 and 1) ................................................................... 414 4.12.5.2.5 PRM_VC_CH_CONF (Voltage Controller Channel Configuration Register) ................. 414 4.12.5.2.6 PRM_VC_I2C_CFG (Voltage Controller I2C Interface Configuration Register) .............. 414 4.12.5.2.7 PRM_VC_BYPASS_VAL (Voltage Controller Bypass Command Register) ................. 415 4.12.6 Generic Programming Examples ............................................................................ 415 4.12.6.1 Clock Control .............................................................................................. 415 4.12.6.1.1 Enabling and Disabling the Functional Clocks ................................................... 415 4.12.6.1.2 Enabling and Disabling the Interface Clocks ..................................................... 417 4.12.6.1.3 Enabling and Disabling the Inactive State ........................................................ 418 4.12.6.1.4 Processor Clock Control ............................................................................ 419 4.12.6.2 Reset Management ....................................................................................... 422 4.12.6.3 Wake-Up Control ......................................................................................... 422 4.12.6.4 Voltage Controller Initialization Basic Programming Model ......................................... 423 4.12.6.5 Event Generator Programming Examples ............................................................. 426 PRCM Use Cases and Tips ............................................................................................ 427 4.13.1 Voltage Control Using VMODE .............................................................................. 427 4.13.1.1 Introduction ................................................................................................ 427Contents 9


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4.14

4.13.1.2 Programming Sequence ................................................................................. 4.13.1.2.1 Initialization Procedure .............................................................................. 4.13.1.2.2 VMODE Signals Toggling ........................................................................... 4.13.1.2.3 Summary Flow Chart ................................................................................ PRCM Register Manual ................................................................................................. 4.14.1 CM Module Registers ......................................................................................... 4.14.1.1 CM Module Summary .................................................................................... 4.14.1.2 IVA2_CM Registers ...................................................................................... 4.14.1.3 OCP_System_Reg_CM Registers ..................................................................... 4.14.1.4 MPU_CM Registers ...................................................................................... 4.14.1.5 CORE_CM Registers .................................................................................... 4.14.1.6 SGX_CM Registers ....................................................................................... 4.14.1.7 WKUP_CM Registers .................................................................................... 4.14.1.8 Clock_Control_Reg_CM Registers ..................................................................... 4.14.1.9 DSS_CM Registers ....................................................................................... 4.14.1.10 CAM_CM Registers ..................................................................................... 4.14.1.11 PER_CM Registers ..................................................................................... 4.14.1.12 EMU_CM Registers ..................................................................................... 4.14.1.13 Global_Reg_CM Registers ............................................................................. 4.14.1.14 NEON_CM Registers ................................................................................... 4.14.1.15 USBHOST_CM Registers .............................................................................. 4.14.2 PRM Module Registers ........................................................................................ 4.14.2.1 PRM Module Summary .................................................................................. 4.14.2.2 IVA2_PRM Registers ..................................................................................... 4.14.2.3 OCP_System_Reg_PRM Registers .................................................................... 4.14.2.4 MPU_PRM Registers .................................................................................... 4.14.2.5 CORE_PRM Registers ................................................................................... 4.14.2.6 SGX_PRM Registers ..................................................................................... 4.14.2.7 WKUP_PRM Registers .................................................................................. 4.14.2.8 Clock_Control_Reg_PRM Registers ................................................................... 4.14.2.9 DSS_PRM Registers ..................................................................................... 4.14.2.10 CAM_PRM Registers ................................................................................... 4.14.2.11 PER_PRM Registers .................................................................................... 4.14.2.12 EMU_PRM Registers ................................................................................... 4.14.2.13 Global_Reg_PRM Registers ........................................................................... 4.14.2.14 NEON_PRM Registers ................................................................................. 4.14.2.15 USBHOST_PRM Registers ............................................................................ Interconnect Overview ................................................................................................... 5.1.1 Terminology ...................................................................................................... 5.1.2 Architecture Overview .......................................................................................... 5.1.3 Module Distribution ............................................................................................. 5.1.3.1 L3 Interconnect Agents .................................................................................. 5.1.3.2 L4-Core Agents ........................................................................................... 5.1.3.3 L4-Per Agents ............................................................................................. 5.1.3.4 L4-Emu Agents ............................................................................................ 5.1.3.5 L4-Wakeup Agents ....................................................................................... 5.1.4 Connectivity Matrix .............................................................................................. L3 Interconnect ........................................................................................................... 5.2.1 Overview ......................................................................................................... 5.2.2 L3 Interconnect Integration .................................................................................... 5.2.2.1 Clocking, Reset, and Power-Management Scheme ................................................. 5.2.2.1.1 Clocks ..................................................................................................

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5.3

5.2.2.1.2 Resets ................................................................................................. 5.2.2.1.3 Power Domain ........................................................................................ 5.2.2.1.4 Power Management ................................................................................. 5.2.2.2 Hardware Requests ...................................................................................... 5.2.2.2.1 Interrupt Requests ................................................................................... 5.2.3 L3 Interconnect Functional Description ...................................................................... 5.2.3.1 Initiator Identification ..................................................................................... 5.2.3.2 Register Target ............................................................................................ 5.2.3.3 L3 Protection and Firewalls ............................................................................. 5.2.3.3.1 Protection Region .................................................................................... 5.2.3.3.2 Priority Level Overview .............................................................................. 5.2.3.3.3 Read and Write Permission ......................................................................... 5.2.3.3.4 REQ_INFO_PERMISSION Configuration ......................................................... 5.2.3.3.5 L3 Firewall Registers Overview .................................................................... 5.2.3.3.6 L3 Firewall Error-Logging Registers ............................................................... 5.2.3.3.7 L3 Firewall and System Control Module .......................................................... 5.2.3.4 Error Handling ............................................................................................. 5.2.3.4.1 Error Detection and Logging ........................................................................ 5.2.3.4.2 Time-Out .............................................................................................. 5.2.3.4.3 Error Steering ......................................................................................... 5.2.3.4.4 Global Error Reporting ............................................................................... 5.2.4 L3 Interconnect Basic Programming Model ................................................................. 5.2.4.1 General Recommendation ............................................................................... 5.2.4.2 Initialization ................................................................................................ 5.2.4.3 Error Analysis ............................................................................................. 5.2.4.3.1 Time-Out Handling ................................................................................... 5.2.4.3.2 Acknowledging Errors ............................................................................... 5.2.4.4 Typical Example of Firewall Programming Example ................................................. 5.2.5 L3 Interconnect Register Manual ............................................................................. 5.2.5.1 L3 Initiator Agent (L3 IA) ................................................................................. 5.2.5.1.1 L3 Initiator Agent (L3 IA) Registers Description .................................................. 5.2.5.2 L3 Target Agent (L3 TA) ................................................................................. 5.2.5.2.1 L3 Target Agent (L3 TA) Registers Description .................................................. 5.2.5.3 Register Target (RT) ..................................................................................... 5.2.5.3.1 Register Target (RT) Registers Description ...................................................... 5.2.5.4 Protection Mechanism (PM) ............................................................................. 5.2.5.4.1 Protection Mechanism (PM) Registers Description .............................................. 5.2.5.5 Sideband Interconnect (SI) .............................................................................. 5.2.5.5.1 Sideband Interconnect (SI) Registers Description ............................................... L4 Interconnects ......................................................................................................... 5.3.1 Overview ......................................................................................................... 5.3.1.1 L4-Core Interconnect ..................................................................................... 5.3.1.2 L4-Per Interconnect ...................................................................................... 5.3.1.3 L4-Emu Interconnect ..................................................................................... 5.3.1.4 L4-Wakeup Interconnect ................................................................................. 5.3.2 L4 Interconnects Integration ................................................................................... 5.3.2.1 Clocking, Reset, and Power-Management Scheme ................................................. 5.3.2.1.1 Clocks .................................................................................................. 5.3.2.1.2 Resets ................................................................................................. 5.3.2.1.3 Power Domain ........................................................................................ 5.3.2.1.4 Power Management ................................................................................. 5.3.3 L4 Interconnects Functional Description ..................................................................... 5.3.3.1 L4-Interconnects Initiator Identification ................................................................Contents

623 623 623 624 624 624 624 624 624 626 628 630 631 632 633 633 635 635 637 638 639 643 643 643 643 645 646 646 650 650 651 656 658 662 662 665 666 674 674 677 677 679 679 680 681 682 682 682 682 682 683 683 68311


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5.3.3.2 Endianness Management ................................................................................ 5.3.3.3 L4 Protection and Firewalls ............................................................................. 5.3.3.3.1 Protection Mechanism ............................................................................... 5.3.3.3.2 Protection Group ..................................................................................... 5.3.3.3.3 Segments and Regions .............................................................................. 5.3.3.3.4 L4 Firewall Address and Protection Registers Setting .......................................... 5.3.3.4 Error Handling ............................................................................................. 5.3.3.4.1 Overview .............................................................................................. 5.3.3.4.2 Error Logging ......................................................................................... 5.3.3.4.3 TA Software Reset ................................................................................... 5.3.3.4.4 Error Reporting ....................................................................................... 5.3.4 L4 Interconnect Programming Guide ......................................................................... 5.3.4.1 L4 Interconnect Low-Level Programming Models .................................................... 5.3.4.1.1 Global Initialization ................................................................................... 5.3.4.1.2 Operational Modes Configuration .................................................................. 5.3.5 L4 Interconnects Register Manual ............................................................................ 5.3.5.1 L4 Iniator Agent (L4 IA) .................................................................................. 5.3.5.1.1 L4 Iniator Agent (L4 IA) Registers Description ................................................... 5.3.5.2 L4 Target Agent (L4 TA) ................................................................................. 5.3.5.2.1 L4 Target Agent (L4 TA) Registers Description .................................................. 5.3.5.3 L4 Link Register Agent (LA) ............................................................................. 5.3.5.3.1 L4 Link Register Agent (LA) Registers Description .............................................. 5.3.5.4 L4 Address Protection (AP) ............................................................................. 5.3.5.4.1 L4 Address Protection (AP) Registers Description ..............................................

683 683 683 684 685 690 692 692 692 694 694 694 694 695 695 699 701 702 707 713 717 717 722 723

6

Interprocessor Communication6.1 6.2

6.3

6.4

......................................................................................... 733 IPC Overview ............................................................................................................. 734 IPC Integration ........................................................................................................... 734 6.2.1 Clocking, Reset, and Power-Management Scheme ........................................................ 735 6.2.1.1 Clocks ...................................................................................................... 735 6.2.1.1.1 Module Clocks ........................................................................................ 735 6.2.1.2 Resets ...................................................................................................... 735 6.2.1.2.1 Hardware Reset ...................................................................................... 735 6.2.1.2.2 Software Reset ....................................................................................... 735 6.2.1.3 Power Domains ........................................................................................... 735 6.2.1.4 Power Management ...................................................................................... 736 6.2.1.4.1 System Power Management ........................................................................ 736 6.2.1.4.2 Module Power Management ........................................................................ 736 6.2.2 Hardware Requests ............................................................................................. 737 6.2.2.1 Interrupt Requests ........................................................................................ 737 6.2.2.2 Idle Handshake Protocol ................................................................................. 737 IPC Mailbox Functional Description ................................................................................... 738 6.3.1 Block Diagram ................................................................................................... 738 6.3.2 Mailbox Assignment ............................................................................................ 739 6.3.2.1 Description ................................................................................................. 739 6.3.3 Sending and Receiving Messages ........................................................................... 739 6.3.3.1 Description ................................................................................................. 739 6.3.4 16-Bit Register Access ......................................................................................... 740 6.3.4.1 Description ................................................................................................. 740 IPC Mailbox Basic Programming Model .............................................................................. 741 6.4.1 Initialization Flow for the Mailbox Module .................................................................... 741 6.4.1.1 Software Reset ............................................................................................ 741 6.4.1.2 Idle Mode and Clock Configuration ..................................................................... 741 6.4.2 Mailbox Assignment ............................................................................................ 741SPRUF98L April 2010 Revised November 2010 Submit Documentation FeedbackCopyright 2010, Texas Instruments Incorporated

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6.5

6.6

6.4.3 Mailbox Communication Preparation ......................................................................... 6.4.4 Mailbox Communication Sequence ........................................................................... 6.4.5 Example of Communication ................................................................................... 6.4.5.1 Sending a Message (Polling Method) .................................................................. 6.4.5.2 Sending a Message (Interrupt Method) ................................................................ 6.4.5.3 Receiving Messages (Interrupt Method) ............................................................... IPC Mailbox Use Cases and Tips ...................................................................................... 6.5.1 Camcorder Use Case: How to Configure the Mailbox Module for Communication Between the MPU and the IVA2.2 Subsystems ............................................................................ 6.5.1.1 Overview ................................................................................................... 6.5.1.2 Programming Flow ....................................................................................... 6.5.1.2.1 Initial Configuration ................................................................................... 6.5.1.2.2 Operational Mode .................................................................................... IPC Mailbox Register Manual .......................................................................................... 6.6.1 Mailbox Register Mapping Summary ......................................................................... 6.6.2 Register Description ............................................................................................ SCM Overview ........................................................................................................... SCM Environment ........................................................................................................ 7.2.1 Functional Interfaces ........................................................................................... 7.2.1.1 Basic SCM Pins ........................................................................................... 7.2.1.2 SCM Interface Description ............................................................................... SCM Integration .......................................................................................................... 7.3.1 Clocking, Reset, and Power-Management Scheme ........................................................ 7.3.1.1 Clock ....................................................................................................... 7.3.1.2 Resets ...................................................................................................... 7.3.1.3 Power Domain ............................................................................................ 7.3.1.4 Power Management ...................................................................................... 7.3.1.4.1 System Power Management ........................................................................ 7.3.1.4.2 Module Power Saving ............................................................................... 7.3.2 Hardware Requests ............................................................................................. SCM Functional Description ............................................................................................ 7.4.1 Block Diagram ................................................................................................... 7.4.2 SCM Initialization ................................................................................................ 7.4.3 Wake-up Control Module ....................................................................................... 7.4.4 Pad Functional Multiplexing and Configuration ............................................................. 7.4.4.1 Mode Selection ............................................................................................ 7.4.4.2 Pull Selection .............................................................................................. 7.4.4.3 Pad Multiplexing Register Fields ....................................................................... 7.4.4.4 System Off Mode ......................................................................................... 7.4.4.4.1 Save-and-Restore Mechanism ..................................................................... 7.4.4.4.2 Wake-Up Event Detection ........................................................................... 7.4.5 Extended-Drain I/O Pin and PBIAS Cell ..................................................................... 7.4.5.1 PBIAS Cells ............................................................................................... 7.4.5.2 Extended-Drain I/Os ...................................................................................... 7.4.6 Band Gap Voltage and Temperature Sensor ............................................................... 7.4.6.1 Band Gap Voltage Reference ........................................................................... 7.4.6.2 Temperature Sensor ..................................................................................... 7.4.6.2.1 Single Conversion Mode (CONTCONV = 0) ..................................................... 7.4.6.2.2 Continuous Conversion Mode (CONTCONV = 1) ............................................... 7.4.6.2.3 ADC Codes Versus Temperature .................................................................. 7.4.7 Functional Register Description ............................................................................... 7.4.7.1 Static Device Configuration Registers .................................................................Contents

741 742 742 743 743 744 745 745 745 745 745 747 751 751 751 760 761 761 761 762 762 764 764 764 764 765 765 765 766 766 766 768 768 768 770 771 772 782 784 784 785 787 787 789 790 790 790 791 791 792 79213

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System Control Module7.1 7.2

.................................................................................................... 759

7.3

7.4


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7.5

7.6

7.4.7.2 Control CSIRXFE Register .............................................................................. 7.4.7.3 MPU and/or DSP (IVA2.2) MSuspend Configuration Registers .................................... 7.4.7.4 IVA2.2 Boot Registers .................................................................................... 7.4.7.5 PBIAS LITE Control Register ........................................................................... 7.4.7.6 Temperature Sensor Control Register ................................................................. 7.4.7.7 CSI Reciever Control Register .......................................................................... 7.4.8 Protection Status Registers .................................................................................... 7.4.9 SDRC Registers ................................................................................................. 7.4.10 Debug and Observability ...................................................................................... 7.4.10.1 Description ................................................................................................. 7.4.10.2 Observability Tables ...................................................................................... 7.4.11 Electomagnetic Interference Reduction for Clocking Generation (Spreading) ......................... 7.4.11.1 Overview ................................................................................................... 7.4.11.2 Integration ................................................................................................. 7.4.11.2.1 Clocking, Reset, and Power-Management Scheme ............................................. 7.4.11.3 Functional Description ................................................................................... 7.4.11.3.1 Spreading Generation Block ........................................................................ 7.4.11.3.2 Spread Spectrum Clocking ......................................................................... 7.4.11.3.3 Frequency Limitations ............................................................................... 7.4.11.4 Basic Programming Model .............................................................................. 7.4.11.4.1 SSC Configuration ................................................................................... SCM Programming Model .............................................................................................. 7.5.1 Feature Settings ................................................................................................. 7.5.1.1 Force Pad Configuration MuxMode by High-Speed USB ........................................... 7.5.1.2 Video Driver ............................................................................................... 7.5.1.3 McBSP1 Internal Clock .................................................................................. 7.5.1.4 McBSP2 Internal Clock .................................................................................. 7.5.1.5 McBSP3 Internal Clock .................................................................................. 7.5.1.6 McBSP4 Internal Clock .................................................................................. 7.5.1.7 McBSP5 Internal Clock .................................................................................. 7.5.1.8 MMC/SD/SDIO2 Module Input Clock Selection ...................................................... 7.5.1.9 Setting Sensitivity on sys_ndmareq[6:0] Input Pins .................................................. 7.5.1.10 I2C I/O Internal Pull-up Enable .......................................................................... 7.5.1.11 SDRC I/O Drive Strength Selection .................................................................... 7.5.1.12 GPMC I/O Drive Strength Selection .................................................................... 7.5.1.13 MCBSP2 I/O Drive Strength Selection ................................................................. 7.5.1.14 MCSPI1 I/O Drive Strength Selection .................................................................. 7.5.1.15 Force MPU Writes to Be Nonposted ................................................................... 7.5.2 Extended-Drain I/Os and PBIAS Cells Programming Guide .............................................. 7.5.2.1 PBIAS Error Generation ................................................................................. 7.5.2.2 Critical Timing Requirements ........................................................................... 7.5.2.3 Speed Control and Voltage Supply State ............................................................. 7.5.3 Off Mode Preliminary Settings ................................................................................ 7.5.4 Pad Configuration Programming Points ...................................................................... 7.5.5 I/O Power Optimization Guidelines ........................................................................... SCM Register Manual ................................................................................................... 7.6.1 SCM Instance Summary ....................................................................................... 7.6.2 SCM Register Summary ....................................................................................... 7.6.3 SCM Register Description ..................................................................................... 7.6.3.1 INTERFACE Register Description ...................................................................... 7.6.3.2 PADCONFS Register Description ...................................................................... 7.6.3.3 GENERAL Register Description ........................................................................ 7.6.3.4 MEM_WKUP Register Description .....................................................................

792 792 793 794 794 794 794 795 796 796 798 832 832 833 833 834 834 835 839 840 840 841 841 841 841 841 841 842 842 842 842 842 843 843 843 845 845 846 846 848 849 849 849 850 851 852 852 852 859 859 860 873 925

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7.6.3.5 7.6.3.6

PADCONFS_WKUP Register Description ............................................................ 925 GENERAL_WKUP Register Description ............................................................... 927

8

Memory Management Units8.1 8.2

............................................................................................... 933934 935 935 936 936 936 937 937 938 938 939 940 941 941 942 943 943 944 944 944 945 946 946 947 947 948 949 949 951 952 952 953 953 953 954 958 958 959

8.3

8.4

8.5

MMU Overview ........................................................................................................... MMU Integration ......................................................................................................... 8.2.1 Clock Domains .................................................................................................. 8.2.2 Power Management ............................................................................................ 8.2.2.1 System Power Management ............................................................................ 8.2.2.2 Module Power Saving .................................................................................... 8.2.3 Reset ............................................................................................................. 8.2.4 Interrupts ......................................................................................................... MMU Functional Description ........................................................................................... 8.3.1 MMU Benefits ................................................................................................... 8.3.2 MMU Architecture ............................................................................................... 8.3.2.1 MMU Address Translation Process .................................................................... 8.3.3 Translation Tables .............................................................................................. 8.3.3.1 Translation Table Hierarchy ............................................................................. 8.3.3.2 First-Level Translation Table ............................................................................ 8.3.3.2.1 First-Level Descriptor Format ....................................................................... 8.3.3.2.2 First-Level Page Descriptor Format ................................................................ 8.3.3.2.3 First-Level Section Descriptor Format ............................................................. 8.3.3.2.4 Section Translation Summary ...................................................................... 8.3.3.2.5 Supersection Translation Summary ............................................................... 8.3.3.3 Two-Level Translation .................................................................................... 8.3.3.3.1 Second-Level Descriptor Format ................................................................... 8.3.3.3.2 Small Page Translation Summary ................................................................. 8.3.3.3.3 Large Page Translation Summary ................................................................. 8.3.4 Translation Lookaside Buffer .................................................................................. 8.3.4.1 TLB Entry Format ......................................................................................... 8.3.5 MMU Error Handling ............................................................................................ 8.3.6 MMU Instance Design Parameters ........................................................................... MMU Basic Programming Model ...................................................................................... 8.4.1 Writing TLB Entries Statically .................................................................................. 8.4.1.1 Protecting TLB Entries ................................................................................... 8.4.1.2 Deleting TLB Entries ..................................................................................... 8.4.1.3 Reading TLB Entries ..................................................................................... 8.4.2 Programming the MMU Dynamically ......................................................................... 8.4.2.1 Programming the MMU Using First- and Second-Level Translation Tables ...................... MMU Register Manual ................................................................................................... 8.5.1 Register Mapping Summary ................................................................................... 8.5.2 MMU Register Description .....................................................................................

9

DMA9.1 9.2

9.3

............................................................................................................................... 971 SDMA Module Overview ................................................................................................ 972 SDMA Controller Environment ......................................................................................... 974 9.2.1 Environment Overview ......................................................................................... 974 9.2.2 SDMA Request Scheme ....................................................................................... 974 SDMA Module Integration .............................................................................................. 975 9.3.1 External SDMA Request Interface Description ............................................................. 975 9.3.2 Clocking, Reset, and Power-Management Scheme ........................................................ 976 9.3.2.1 Clocking .................................................................................................... 976 9.3.2.2 Resets ...................................................................................................... 977 9.3.2.2.1 Asynchronous Hardware Reset .................................................................... 977 9.3.2.2.2 Software Reset Through the Configuration Port ................................................. 977Contents 15


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9.4

9.5

9.6

9.7

9.3.2.3 Power Domain ............................................................................................ 977 9.3.3 Hardware Requests ............................................................................................. 977 9.3.3.1 Interrupts to the MPU Subsystem ...................................................................... 977 9.3.3.2 DMA Requests to the SDMA Controller ............................................................... 978 SDMA Functional Description .......................................................................................... 981 9.4.1 Logical Channel Transfer Overview .......................................................................... 981 9.4.2 FIFO Queue Memory Pool ..................................................................................... 983 9.4.3 Addressing Modes .............................................................................................. 983 9.4.4 Packed Accesses ............................................................................................... 987 9.4.5 Burst Transactions .............................................................................................. 988 9.4.6 Endianism Conversion ......................................................................................... 988 9.4.7 Transfer Synchronization ...................................................................................... 988 9.4.7.1 Software Synchronization ................................................................................ 988 9.4.7.2 Hardware Synchronization .............................................................................. 988 9.4.8 Thread Budget Allocation ...................................................................................... 991 9.4.9 FIFO Budget Allocation ........................................................................................ 991 9.4.10 Chained Logical Channel Transfers ......................................................................... 992 9.4.11 Reprogramming an Active Channel ......................................................................... 992 9.4.12 Interrupt Generation ........................................................................................... 992 9.4.13 Packet Synchronization ....................................................................................... 993 9.4.14 Graphics Acceleration Support ............................................................................... 994 9.4.15 Supervisor Modes .............................................................................................. 995 9.4.16 Posted and Nonposted Writes ............................................................................... 995 9.4.17 Disabling a Channel During Transfer ........................................................................ 995 9.4.18 FIFO Draining Mechanism .................................................................................... 995 9.4.19 Reset ............................................................................................................ 996 9.4.20 Power Management ........................................................................................... 996 9.4.20.1 Interconnect Clock Auto-Idle ............................................................................ 996 9.4.20.2 Automatic Standby Mode ................................................................................ 996 SDMA Basic Programming Model ..................................................................................... 996 9.5.1 Setup Configuration ............................................................................................. 996 9.5.2 Software-Triggered (Nonsynchronized) Transfer ........................................................... 997 9.5.3 Hardware-Synchronized Transfer ............................................................................. 998 9.5.4 Synchronized Transfer Monitoring Using CDAC .......................................................... 1000 9.5.5 Concurrent Software and Hardware Synchronization .................................................... 1001 9.5.6 Chained Transfer .............................................................................................. 1001 9.5.7 90 Clockwise Image Rotation ............................................................................... 1001 9.5.8 Graphic Operations ............................................................................................ 1002 SDMA Use Cases and Tips ........................................................................................... 1003 9.6.1 Camcorder Use Case: How to Configure SDMA to Handle Transfers With McBSP2 and MMC to External DRAM ................................................................................................ 1003 9.6.1.1 Introduction ............................................................................................... 1003 9.6.1.2 SDMA Configuration to Transfer Data Between the McBSP and External DRAM ............. 1003 9.6.1.2.1 Overview ............................................................................................. 1003 9.6.1.2.2 Environment ......................................................................................... 1004 9.6.1.2.3 Data Path ............................................................................................ 1004 9.6.1.2.4 Programming Flow ................................................................................. 1004 9.6.1.3 SDMA Configuration to Transfer Data Between MMC and External DRAM .................... 1007 9.6.1.3.1 Overview ............................................................................................. 1007 9.6.1.3.2 Programming Flow ................................................................................. 1007 SDMA Registers Manual .............................................................................................. 1010 9.7.1 SDMA Instance Summary .................................................................................... 1010 9.7.2 SDMA Register Summary .................................................................................... 1010 9.7.3 SDMA Register Description .................................................................................. 1011SPRUF98L April 2010 Revised November 2010 Submit Documentation FeedbackCopyright 2010, Texas Instruments Incorporated

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10

Interrupt Controller10.1 10.2 10.3

......................................................................................................... 10371038 1040 1041 1041 1041 1041 1042 1042 1045 1047 1047 1047 1047 1047 1047 1048 1048 1048 1049 1049 1049 1053 1056 1057 1057 1057 1058 1068

10.4

10.5

10.6

Interrupt Controller Overview ......................................................................................... Interrupt Controller Environment ..................................................................................... MPU Subsystem INTCPS Integration ................................................................................ 10.3.1 Clocking, Reset, and Power Management Scheme ..................................................... 10.3.1.1 MPU Subsystem INTC Clocks ......................................................................... 10.3.1.2 Hardware and Software Reset ........................................................................ 10.3.1.3 Power Management .................................................................................... 10.3.2 Interrupt Request Lines ...................................................................................... Interrupt Controller Functional Description ....................................................................

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