ZDS-1/40

Zilog Hardware Reference Manual

May 1979

03-3018-03

MAY 1979

Copyright 1979 by Zilog, Inc. All rights reserved.No part of this publication may be reproduced, storedin any retrieval system, or transmitted, in any formor by any means, electronic, mechanical, photocopying,recording or otherwise, without the prior writtenpermission of Zilog.

Zilog assumes no responsibility for the use of anycircuitry other than circuitry embodied in a Zilogproduct. No other circuit patent licenses areimplied.

ZDS-1/40

Hardware Reference Manual

May 1979

CONTENTS

Section 1 GENERAL INFORMATION

1.1 Introduction 1-11.2 Z-80 Development System Description 1-11.3 Note to the Development Engineer. 1-4

Section 2 INSTALLATION

2.1 Initial Unpacking and Inspection 2-12.2 Power and Signal Connections 2-1

Section 3 PRINCIPLES OF OPERATION

3.1 Processor Module 3-13.2 Real Time Debug Module 3-13.3 System Memory Module 3-23.4 Floppy Disk Controller Module 3-23.5 User POD Controller 3-3

Section 4 OPERATION

4.1 Introduction 4-14.2 Controls and Indicators 4-14.2.1 Front Panel Indicators and Switches 4-14.2.2 Rear Panel Switches 4-24.2.3 External Cables 4-24. 3 Monitor Mode 4-24. 4 Debug 4-24. 5 Memory Mapping 4-34.6 I/O Ports 4-4

Section 5 OPTIONS

5.1 The Peripheral Interface Board 5-15.2 The Auxiliary Serial/Parallel I/O Board 5-1

111

Section 6 TECHNICAL DESCRIPTION

6.1 Introduction 6-16.2 Processor Module Introduction 6-16.2.1 Reset Logic 6-36.3 Hardware Breakpoint Module 6-36.4 Real-Time Storage Module (RTSM) 6-66. 5 Monitor Module 6-66.6 64K Memory Module. .6-76.6.1 Introduction 6-76.6.2 Interpretation of Schematic c.6-76.7 Floppy Disk Controller... ..6-86.7.1 Data Format 6-86.7.2 Sector Recording Format 6-96.7.3 Tracks 6-96.7.4 Controller Functional Description., 6-116.7.5 Recording Format , 6-126.8 Z-80A CPU Emulator Sub-System 6-146.8.1 Introduction 6-146.8.2 Capabilities 6-196.8.3 Architecture 6-206.8.4 Restrictions .6-206.9 Hardware Overview 6-21

Section 7 THE EMULATOR

7.1 Emulator 7-17.2 Z-80A CPU Emulator 7-2

Section 8 THE USER POD

8.1 User POD 8-1

Section 9 THE USER POD CONTROLLER

9.1 User POD 9-19.2 Memory Map Software Interface 9-19.3 User POD Control Port 9-29.4 User POD Controller Sheet 1 9-59.5 User POD Controller Sheet 2 9-59.6 User POD Controller Sheet 3 9-69.7 User POD Controller Sheet 4 9-69.8 User POD Controller Sheet 5 9-7

IV

APPENDICES*

APPENDIX A: PORT ASSIGNMENTS A-l

APPENDIX B: ZDS-1/40 CONFIGURATION B-l

APPENDIX C: BACKPLANE DEFINITION FOR ZDS-1/40 C-l

APPENDIX D: PINOUT CHARTS D-l

APPENDIX E: LOGIC DIAGRAMS E-l

SECTION 1

GENERAL INFORMATION

1.1 Introduction

This manual describes the Z-80 Development System from thehardware point of view. It is intended to be used as a toolfor the engineer/programmer to design systems based on Z-80hardware and software. In particular, the user is guided inthe debug of his prototype hardware and software.

Although reference is frequently made to Development SystemSoftware, the main descriptions and operating instructions arecontained in the following documents:

• RIO OS User Manual

• RIO Relocating Assembler and Linker User Manual

• RIO Text Editor User Manual

• ZDS-1/40, ZDS-1/25 PROM User Manual

• Zilog Analyzer Program (ZAP) Software Manual

This manual describes the basic operation and basic componentsof the ZDS-1/40 Development System.

*

1.2 Z-80 Development System Description

The Z-80 Development System is a computer system designed tosupport all activities associated with the creation ofmicroprocessor hardware and software. The system includes twofloppy disks with a sophisticated file maintenance system.With this capability, the user can quickly retrieve,manipulate, and store large files of data to minimize softwaredevelopment time. The system also includes an advanced realtime debug module that connects directly to the user's system,thus, providing a simultaneous hardware and software debugcapability. A block diagram of the ZDS-1/40 is shown inFigure 1-1.

1-1

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The specific features of the Development System include:

• Z-80 CPU with 4K bytes dedicated RAM/ROM

• RS-232 or current-loop serial interface

• 60K bytes of general-purpose read/write memory

• Programmable hardware breakpoint module

• Programmable real time event storage module

• In-circuit emulation module to connect systemto user's equipment

• 2 floppy disk drives and controller

• Full software including:

ROM-based I/O handler and command interpreterDisk-based debug package

- RIO operating system- Editor- Assembler and Linker

The ZDS-1/40 uses a Z-80 2.5 MHz CPU to accommodate thesystem's operation in the monitor mode and a special Z-80A 4MHz CPU in the emulator to accommodate in-circuit emulation inthe user's system.

In the Program Development mode, the system performs as astand-alone program development tool, allowing softwareprograms to be entered into RAM, edited, assembled, filed ondisk for future use, and loaded for execution. This entireprocess is performed through simple commands from the user'sterminal.

In the Hardware/Software Debug mode(ZAP), the system memoryand peripheral elements are available to the user's ownsystem. The system peripherals use I/O port number EOHthrough FFH. These port numbers are reserved for the systemin monitor mode. In user mode, a RAM resident user's programis executed in real time and all I/O ports may be in the UserSystem. The use of Ram for the program eliminates costly andtime-consuming PROM programming in the early phases ofsoftware development.

A major feature of the ZDS-1/40 Development System is itspowerful debug module. This module allows ZDS-1/40 emulationsystem bus transactions that are designated pertinent by the

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user to be stored in real time into an independent memory. Theuser can also specify that any type of system transaction cansuspend user operation and cause the system to re-enter themonitor mode. The complete record of all transactions -—•'preceding this suspension that was recorded in the independentmemory can then be conveniently displayed on the systemterminal. This ability to freeze real time event sequencesand then to review selected events in detail, permits the userto accomplish product design and hardware/software debuggingin the shortest possible time. Without this feature, it isextremely difficult to find errors in programs or hardwarewhere the user cannot single step through a program due toreal time I/O restrictions.

1.3 Note To The Design Engineer

Although the ZDS-1/40 represents the state-of-the-art indevelopment systems, there are certain characteristics andrestrictions associated with its use that must be consideredby design engineers. These considerations are summarized inthis section of the manual so that they might serve as aconvenient reference when planning design procedures.

First, the Z-80 CPU Emulator possesses the characteristics ofthe Z-80 CPU Chip, with the following exceptions:

1) maximum high-level preload is 10 microamps.

2) maximum low-level preload is 200 microamps.

3} maximum cable preload capacitance is 30picofarads.

4) maximum low output voltage is 0.51 volts.

Second, because of the MOS interface and the emulator hybridconcept used in the ZDS-1/40, certain lines to the emulatormust be controlled:

1) BUSRQ - Bus request2) NMI - Non-maskable Interrupt Request3) INT - Maskable Interrupt Request4) MQR - Memory Request5) WR - Write6) CLK - Clock Input Signal

This approach allows the development system to communicatewith the emulator without disturbing the user's system. Thisapproach is also required to provide memory mapping features.

1-4

The WAIT line from the emulator is not controlled, but is OR'dwith the WAIT line from the development system.

In addition, there is a control switch associated with the +5Vdc supply.

The BUSRQ, NMI, and INT lines are controlled by the system sothat the development system software, the Zilog AnalyzerProgram (ZAP), may communicate with the emulator withoutdisruption. These lines are enabled or disabledsimultaneously when the software communicates with theemulator. They are disabled by ZAP on initialization, andmust be enabled by a command from the system console. Theselines may be disabled by the ZAP command when the prototypedevice is being debugged.

The MQR and WR lines are controlled for memory mapping. Thereason is to allow the development system to always see theMQR and WR signals from the emulator, but only to allow theuser's system to see them when the map defines memory to existin the user system at a specified address. These lines arealso controlled to prevent spurious access to user memoryduring Monitor Mode operation, while still allowing refresh ofuser RAM.

The WAIT line is a special line to the emulator, in that itmay be activated from two different sources. Again, thisapproach is due to the memory mapping features of the system.This line may be activated from the user's system, or by thelogic of the development system, when accessing memory thathas been defined to exist in the development system. Thedevelopment system presently pulls the WAIT line for oneT-state for each access to development system memory atfrequencies above 2.5 MHz. When accessing user memory, theaccess will occur without wait states unless the user'sprototype device generates wait states. The WAIT line is alsopulled by the development system during transitions betweenUser and Monitor Modes.

Because the user and system WAIT lines to the emulator areOR'd through a simple transistor gate rather than a TTL gatein the Z-80 CPU emulator, it is extremely important that theWAIT line is terminated properly by the user's system. Thisline should be pulled up with a resistance value greater than4.7K ohms, and driven by a logic device with an open-collectoroutput.

The clock (PHI) line to the Z-80 CPU, as well as any othermicroprocessor, is one of the most critical signals. Thissignal should be generated using the logic circuitry described

1-5

in the Zilog Application Note for the Z-80 Clock Driver, orwith an equivalent circuit. The clock stablility andfrequency should be examined under load, with the Z-80 CPUinstalled, before connecting the emulator and the prototypedevice.

The Emulator PC board contains a switch that is used to selecteither an internal or external clock source for the emulator.When running on internal clock, the frequency will be 2.5 MHz.If the clock selected is internal, and the prototype device isalso providing clock, the two will be tied directly together,making the emulator inoperative.

In order for the emulator to operate when it is not suppliedwith +5 vdc from the user system, the development system powersupply can be connected to the emulator CPU by means of aswitch located next to the internal/external clock switch onthe emulator PC board. If this switch is left in theinternal, or development system, position when the user'sprototype is also providing VCC, the two power supplies willbe connected directly together, causing difficulties andpossible damage to the equipment.

When the emulator executes a HALT instruction, it behavesexactly like a Z-80 CPU. However, some users may use a HALTinstruction as a wait loop to await an interrupt. If the userexecutes a HALT instruction and presses the MON button on thefront panel, the development system will reset the emulator toexit the HALT state. This will have the following effects:

a) The reset will clear the PC, I, and R registers anddisable interrupts.

b) The development system can recover the PC, but theI and R register contents will be lost.

The most important design consideration in using the emulatoris the fact that only the MRQ and WR lines are controlled bythe development system. The RD line is not controlled becauseit cannot be controlled without controlling Ml. This isbecause a Z-80 PIO chip will reset itself when it sees an Mlwithout a RD or IORQ signal also present.

Because RD is not controlled by the development system, theuser must not use the RD signal alone to controlbi-directional data bus drivers in the prototype device. Thecontrol logic for the drivers must use MRQ as one of theenabling terms. If it is not used, bus conflicts (contention)will occur, rendering the emulator inoperative. A recommendedcircuit for control of the user's data bus is shown in Figure1-2.

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74SOO

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Figure 1-2 Bus Driver Control Circuit

This circuit allows the emulator to control the bus driversusing MRQ. It also allows the bus to function properly forinput instructions and for interrupt acknowledge cycles.Using this scheme, the user's data bus is turned away from theemulator Z-80 CPU unless a MRQ+RD (memory read) , IORQ+RD (portread), or IORQ+M1 (interrupt acknowledge) occurs.

The MRQ line is controlled to facilitate transitions betweenIdle Mode when the emulator is not running a program and RunMode when the emulator is running a program.

When the system is in Idle Mode, user dynamic RAM refresh ismaintained by causing the emulator to continuously execute ajump relative minus 2 instruction. This step keeps theemulator Z-80 CPU in a tight loop with constant fetch cycles(known as idling). During the refresh interval of each fetchcycle, MRQ is enabled and refresh occurs in a normal manner.In Run Mode, the emulator runs in the usual manner.

When a transition is made from Idle to Run, the first fetchfrom user memory occurs in a cycle in which MRQ is delayeduntil after the rising edge of T2 by the state machine in theuser pod, which controls the operating mode. Two wait statesare then forced by the state machine to ensure that the usermemory access has sufficient time to occur. The prototypedevice may create additional wait states in the usual way.

When a transition is made from Run to Idle, a final fetch fromthe prototype device memory will be attempted, but the MRQline will be disconnected from the user bus after the leadingedge of T3, and the cycle will be prolonged by three waitstates. This allows the emulator Z-80 CPU to actually readthe jump relative instruction minus 2 instruction referred toabove. The user WAIT line can cause additional wait states tobe added to this cycle.

1-7

SECTION 2

INSTALLATION

2.1 Initial Unpacking and Inspection

Inspect the product for shipping damage as soon as it isunpacked. Check for any physical damage that may beattributed to abuse and handling during shipment. If theproduct is damaged in any way, notify the carrier and Zilogimmediately.

2.2 Power and Signal Connections

Inspect the power connector area on the rear panel of the twochassis units. Next to the power connector is a small switchimprinted with either "120" or "230" to indicate the AC linevoltage for which the unit is configured. In the unlikelyevent that this figure disagrees with the user site voltage,the power supply can be reconfigured by simply moving theswitch element until the proper voltage figure is visible.Verify that the main AC power-on switch is in the OFFposition. The power switch for the ZDS-1/40 system is locatedon the rear panel. Now connect the AC power cords to thesource and rear panel jacks.

The terminal for user communication with the DevelopmentSystem must now be connected. Such a terminal Ccin bepurchased as an option from Zilog, however, any standardteletype with a 20mA interface or CRT terminal with an RS-232interface may be used. Connect the terminal's interconnectcable, supplied with the terminal, to connector J106 on therear of the microcomputer chassis.

*** NOTE ***

The J106 connector on the rear of the microcomputer chassis,used for terminal interface, is shipped with pins 5, 6, and 8permanently wired high. According to standard RS-232specifications, these pins are designated:

Pin 5 - Clear to SendPin 6 - Data Set ReadyPin 8 - Carrier Detect

It is true, however, that some RS-232 interface terminals are

2-1

not fully compatible with these specifications, i.e., theterminal interface might use pins 5, 6, or 8 for a functionother than listed, and when connected to the system, theterminal may not function properly.

If the user determines that the terminal interface does indeedhave pin requirements other than those listed above for Pins5, 6, and 8, the user must modify the cable to interconnect tothe microcomputer by cutting the wires in the cable associatedwith these three pins. If such a change is necessary, themicrocomputer's J106 pin assignments are listed below to makethe change easier.

Pin No.

237

105,24,6,8

1617

23,2520,21,22

18,1914,15

Signal Name

RS-232 Data InRS-232 Data OutRS-232 ReturnTTY Data InTTY In Return (200 ohms to +12)TTY Data OutTTY Out Return (200 ohms to ground)GND 01GND 02GND 03GND 04

2-2

SECTION 3

PRINCIPLES OF OPERATION

3.1 Processor Module

The processor module is a single card containing allelements necessary to function as a stand-alone computer.The card contains 3K bytes of PROM and IK bytes of RAM inwhich reside the operating system, peripheral drivers andbootstrap loader. The peripheral driver routines can beaccessed by the user.

3.2 Real Time Debug Module

The Z-80 Development System real time debugging capabilityenables the user to easily locate and correct any hardwareor software design errors. With this disk-based module, theuser monitors the operation of his software in real time andsets hardware breakpoints to stop the program on any data,address, or control bit pattern. Once stopped, the systemreturns to the monitor mode where the debug software allowsthe user to display the contents of any internal CPUregister, or memory location, or to change any register ormemory location prior to continuing the program from thatpoint.

The real time debug module consists of a real time storageboard, breakpoint board, pod controller board, pod andemulator. The real time storage board contains a 256 by 32storage array. This array stores up to 256 events. The 32stored bits include:

• 16-bit address bus• 8-bit data bus• 7-bit control bus

The last bit is used as a marker to identify the firsttransaction that is stored when the user's program beginsexecution. The debug software package allows the user tospecify the types of transactions that are to be stored inthe memory. Any combination of the following transactionscan be stored:

3-1

• Memory Reads• Memory Writes• I/O Port Reads• I/O Port Writes

After the system returns to the monitor, the contents of thestorage array can be printed on the user's terminal in aconcise form to readily show how the program arrived at thecurrent point.

The breakpoint card monitors the system bus and haltsemulation if a user-specified transaction occurs. The usermay specify that a break should occur on any combination ofthe following transactions:

• Ml Fetch• Memory Read• Memory Write• I/O Port Read• I/O Port Write

In addition, he may specify that the selected transactionhave a specified 16-bit memory address or an 8-bit I/O portaddress and/or any specific bit pattern on the data bus.Thus, the user can specify complex events such as writing a"1" on bit 6 of I/O port number F6H.

3.3 System Memory Module

The system uses standard 16K elements configured in 16K byteincrements, with 64K bytes on a single system memory board.System memory is shared between the monitor mode and theuser mode.

*In Program Development mode, programs are entered,, edited,assembled and loaded directly into RAM for immediateexecution without the additional cost and time delaysassociated with programming PROMs.

In the Hardware/Software Debug mode, Development SystemMemory contains the RIO Operating System, the ZAP OperatingSystem, and the PROM Operating System. The remaining RAM isavailable for mapping into the User System. Any combinationof external ROM, RAM or PROM can be used in place of, or incombination with, the standard system RAM through thein-circuit emulation bus.

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3.4 Floppy Disk Controller Module

This single circuit board interfaces two floppy disk drivesfor support of the Z-80 disk-based operating software andfor user program storage. The utility for the control ofthe disk drives is embodied in system firmware located inPROM on the processor module.

3.5 User Pod Controller

This card contains all elements necessary to interface thesystem bus to the special Emulator bus. In addition, a UserPod and hybrid emulator are provided to complete the systemsinterface. The User Pod contains all time critical emulatorcontrol logic and buffers. The hybrid emulator is amodified Z-80A. This interface includes:

• 16-bit address bus• 8-bit data bus• All CPU control signals• System clock

All lines provide TTL-compatible MOS signal levels forconnection to any external User System. The switch on theemulator hybrid allows for the use of an external clock.

3-3

SECTION 4

USER OPERATION

4.1 Introduction

The user is directed to the manuals listed in Section 1.1for a detailed description of the operation of the systemsoftware.

4.2 Front Panel Indicators and Switches

There are four lighted button-type switches/indicators onthe front panel of the microcomputer chassis. Each switchhas a specific function related to a specified systemoperating mode.

• WAIT

Pressing the WAIT Button resets the entire system to thedebug level by providing a power-on clear. At this time, acharacter "S" or a carriage return must be entered from theterminal in order to resume operation. Depressing the WAITbutton removes the refresh signals to the internal dyanamicRAM so that any programs stored there may be destroyed. Thelamp under this switch serves as an indicator that thecomputer is in a WAIT state. During normal systemoperation, the CPU enters the WAIT state during diskoperations. The only other time that the CPU should enterthe WAIT state is during hardware/software debug mode whenthe user's hardware forces a WAIT state.

• USER

The indicator light is on any time the systems is in theuser mode; that is, when it is running a real-time user'sprogram and it is not in the operating system, edit,assemble, or debug software environments. The USER buttonhas been disabled so that the only way to start an emulationis through the debug software.

• MON

This indicator is lit any time the system is in Monitormode; that is, whenever it is in the operating system, edit,assemble, or debug software environments. The button switchcan be pressed to take the system from the ZAP emulation to

4-1

the ZAP monitor mode. The MON switch is disabled in allother environments. However, the ESC key on the console willstop operation and return to the operating system from anyoperation.

4.3 Rear Panel Switches

The microcomputer chassis has three toggle switches and oneBNC connector on the back panel.

One switch is the main power-on switch for the microcomputerchassis.

Two sense switches are provided but are not used by anystandard software.

The back panel on the microcomputer chassis has a standard3-pronged AC power cable connector, and a BNC connectorwhich allows the synchronization of an oscilloscope to auser selected system event. Refer to the pulse commanddescribed in the Z-80A CPU Emulator Software Manual for adescription of oscilloscope synchronization.

4.4 External Cables

A flat ribbon cable is provided to interface the dual floppydisk unit to the CPU unit. This cable is connected to J107of the CPU unit.

4.5 Monitor Mode

In Monitor mode, the operator can call for four operatingsystem environments: Edit, Assemble, and Zap. Each ofthese environments has its own special command structurederived from the tasks it performs. Together, they comprisea very powerful and complete software and hardwaredevelopment system that allows programs to be entered intomemory, edited, assembled or compiled, filed on disk forfuture use, and loaded into memory for execution andemulation. The ZAP environment allows user programs to beloaded, executed, and quickly debugged.

4.6 Zilog Analyser Program (ZAP)

A major feature of the Z-80 Development System is itspowerful debug capability. This capability allows selected

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emulator transactions to be stored into a special memory inreal-time as the program is being executed by the emulator.The user can also specify that any type of systemtransaction, such as setting Bit 6 of Port 8BH, or readingfrom address 1C8H, can suspend execution of the user programand cause the system to re-enter the monitor mode. Then, acomplete record of the last 256 bus transactions (which wererecorded in a separate Real-Time Storage Module memory stackjust prior to the suspension) can be conveniently displayedon the system terminal. This ability to store real-timeevent sequences and then to review selected events in detailpermits the user to accomplish product design andhardware/software debugging in the shortest possible time.

4.7 Memory Mapping

A memory mapping function is provided that allows the userto define the specific nature of his memory address space.The 64K bytes of the user memory space is divided into 64IK-byte blocks. Each block may be defined to exist ineither the User System, the Development System, or to benon-existent. If a block is defined to be non-existent,then any access to that block causes a break in emulation.If a block is defined to exist in the Development System,then an address transformation may be specified. Thisaddress transformation allows a block of System memory torespond to an address other than the physical addressassigned to that block.

Environment Dynamic Memory Usage

Debug Store user programEdit Edit software and

file work spaceAssemble -Assembler software

and work spaceZAP User program to be

executed, RIO OperatingSystem, and ZAP OperatingSystem ;

OS Executive Commands

4-3

4.8 I/O Ports

The Z-80 CPU can address up to 256 I/O ports. The followinglist shows how these ports are utilized in the basicZDS-1/40. During an emulation, the mapping of I/O portsdepends on the emulation clock that is selected. When userclock is selected, all ports exist only in the User System.When system clock is selected, all ports are in thedevelopment system.

ADDRESS READ FUNCTION

OFFH BAUD RATE DETECTIONOFEH STATUS PORTOFDH SOFTWARE SYSTEM RESETOFCH RTSM CONTROL PORTOFBH BRKPT CONTROL PORTOFAH DISK CONTROL PORT AOF9H DISK CONTROL PORT BOF8H DISK DATA PORTOF7H SET MONITOR MODEOF6H NOT USEDOF5H USART CONTROL PORTOF4H USART DATA PORTOF3H SYSTEM CTC C3OF2H SYSTEM CTC C2 - BAUD RATEOF1H SYSTEM CTC Cl - SER. CLK.OFOH SYSTEM CTC CO - DISK SECTOROEFH USER MEMORY MAP PORTOEEH USER INTERFACE CONTROL PORTOEDH NOT USEDOECH NOT USEDOEBH USER INTF. BREAK GEN.OEAH USER INTF. WRITE PROT. ERR.OE9H USER INTF. NO MEM. ERR.OE8H USER INTF. BAD CLOCK ERR.OE7H USER INTF. CASCADED CTC C3036H USER INTF. CASCADED CTC C2OE5H USER INTF. CASCADED CTC ClOE4H USER INTF. CASCADED CTC COOE3H NOT USEDOE2H NOT USEDOE1H NOT USEDOEOH NOT USED

WRITE FUNCTION

NOT USEDNOT USEDSET USER MODERTSM CONTROL PORTBRKPT CONTROL PORTDISK CONTROL PORT ADISK CONTROL PORT BDISK DATA PORTSET MONITOR MODENOT USEDUSART CONTROL PORTUSART DATA PORTSYSTEM CTC C3SYSTEM CTC C2 - BAUD RATESYSTEM CTC Cl - SER. CLK.SYSTEM CTC CO - DISKUSER MEMORY MAP PORTUSER INTERFACE CONTROL PORTNOT USEDNOT USEDUSER INTF,USER INTF.USER INTF,USER INTF.USER INTF,USER INTF.USER INT?,USER INTF,NOT USEDNOT USEDNOT USEDNOT USED

BREAK GEN.WRITE PROT. ERR.NO MEM. ERR.BAD CLOCK ERR.CASCADED CTC C3CASCADED CTC C2CASCADED CTC ClCASCADED CTC CO

4-4

SECTION 5

OPTIONS •

5.1 The Peripheral Interface Board :

The Zilog peripheral interface board (PIB) is a generalpurpose I/O board for interface to devices that accept datain a parallel format. The PIB contains two Z-80 PIO's withsupporting logic to provide 32 bi-directional I/O bits. Thecard also contains plated through holes for insertion of aZ-80 CTC to provide four counter/timers channels.

The uncommitted PIO's and/or the user supplied CTC can beinterfaced with the system daisy-chain priority interruptstructure. Unused space is provided with 16-pin diplocations (Vcc on pin 16, GND on pin 8) to allow additionallogic at the user's discretion.

The four-bit dip switch determines the ports' addresslocations while additional control logic directs porttransactions with the CPU system data bus.

The PIB can be configured for specific peripherals. Thedetailed logic description for each of the followingconfigurations is provided separately.

• Printer Interface• Paper tape reader/punch ;

5.2 The Auxiliary Serial/Parallel I/O Board

The Z-80 auxiliary serial/parallel I/O (ZDS/ASPIO) boardprovides the development system with one additionalprogrammable serial communications interface and oneadditional programmable parallel interface. The serialinterface is implemented with an 8251 universalsynchronous/asynchronous receiver/transmitter (USART) toprovide a RS232-compatible output. The parallel interfaceconsists of the Z-80 PIO, which has been configured as aprinter interface.

The USART is programmed by means of a control byte loaded bythe Z-80 CPU. Controllable parameters include stop bits percharacter (1.0, 1.5, 2.0), bits per character (5-8), parityinsertion/checking (odd, even, or none), and clocking oftransmitted and received data at frequencies of 1, 16, or 64

5-1

times the data rates. The USART accepts data charactersfrom the Z-80 in a parallel format and converts them into acontinuous serial data stream for transmission. The USARTcan simultaneously receive serial data streams and convertthem into parallel data characters for the Z-80.

The Z-80 PIO provides a software programmable, two portparallel I/O device for standard hardware interface betweenperipheral devices and the Z-80A CPU. The PIO contains twoindependent 8-bit ports with full handshake control that canbe configured by the CPU to operate in any of four majormodes. In the output mode (Mode 0)/ data is written to theports from the Z-80 and onto the port data bus. In theinput mode (Mode 1), the peripheral device supplies data tothe port. The bidirectional mode (Mode 2) allows one port(Port A) to be bidirectional using the handshake signalsfrom both ports. The control mode (Mode 3) allows fordirect bit set and reset capability. This mode also allowsany bit in either port to be individually programmed to beeither an input bit or an output bit. Vectored interruptcommunication with the CPU is included to facilitate datatransfer. A unique feature of the PIO is that it can beprogrammed to interrupt the Z-80 CPU on the occurrence ofspecified status conditions in the peripheral device. Oneport has the ability to source a minimum of 1.5mA of currentat 1.5 volts allowing Darlington transistors to be directlydriven (for printer and high voltage displays, for example).

The CTC provides a data rate clock for the USART with allthe common communication baud rates between 50 and 9600baud. Unused area on the card is filled with plated-throughholes on .10 inch centers for insertion of wire-wrapsockets.

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SECTION 6

TECHNICAL DESCRIPTION

6.1 Introduction

The following sections describe the standard boards in theZDS-1/40 system.

i

6.2A Processor Module Introduction (Schematics, page E-43)(09-0099-03 only) ,

The processor card contains a Z-80 CPU, Z-80 CTC and USART forconsole interface, plus 3K of PROM and 2K of static RAM forcontrolling the system environment. System PHI derives from a19.6608 MHz quartz oscillator divided by eight. An additional16.589 MHz oscillator is provided to the floppy diskcontroller for synchronous data separation. The CPU bus isfully buffered to support stand-alone system operation withfull memory and I/O compliments. The relationship of theseelements is represented in Figure 6.2-1, below.

*tMO«Y PACESELECTS

AOUKESS IUS

DATA IUS

COVntOLlUS(IN)

STATUS BUS (OUT)rowti-ON

RESET

Figure 6.2-1. Processor Module Block Diagram

6-1

The Z-80 CPU bus buffers are shown on Sheet One of theschematics. System PHI is generated by hybrid oscillator A15.Counter A19 produces the 2.46 MHz system clock as well as halfPHI for baud rate timing. The discrete circuit oscillator iscontrolled by a 16.589 MHz crystal and is used by the floppycontroller's synchronous data separator.

Data bus buffers A35 and A36 interface the CPU to the systembus (backplane) and drive toward the CPU during Ml or Readcycles. Buffers A23 and A24 drive the system address bus.A30 drives outbound control signals such as Ml, IORQ, RD,etc., while A32 receives inputs, e.g., INT, NMI, RESET, etc.

Zilog clock driver A21 provides a MOS-compatible clock sourcefor the LSI devices.

Sheet Two depicts the address decoding assignments for thefollowing:

Prom Firmware FOOOH - FFFFHDynamic Memory OH - EFFFHSystem Ports FOB - FFH

Adder A16 always translates addresses from OOH to FOOOH sothat ROM is always in low memory (OOOOH - OBFFH). Gate A17generates the Page 15 address enable that allows access toPROM when user memory is mapped to system memory OOOOH andwhen a system access is made to OOOOH - OBFFH. System I/Oports are decoded by the logic of A2 and A3.

Sheet Three of the schematics details the PROM/RAMimplementation and the bus control logic for A3 3, A34, A35 andA36 buffers.

Chip selects for A9-A11, Al and A2 occur when prom addressesare decoded by Sheet Two logic. These decoded addresses,along with I/O and interrupt requests from peripherals A20 andA8 (Sheet Four) cause bus drivers A35 and A36 to drive thesystem data bus toward the CPU. Automatic baud rate timing isacquired through tristate A18 and data bit DO.

Sheet Four contains the peripherals found on the CPU-3 card.The console interface is implemented by way of USART A8 andCTC A20. Highest priority in the daisy chain, the CTCprovides interrupt capability for the floppy disk interfaceand the USART status lines. Jumpers El and E2 allow receiverinterrupts from the USART. Flip-flop A4 provides a squarewave baud rate clock source to the USART.

6-2

6.2B Processor Module Introduction (Schematics, pages E-31 through 42)(09-0099-02 and -01 only)

The processor card contains a Z-80 CPU, Z-80 CTC and USART forconsole interface, plus 3K of PROM and 2K of static RAM forcontrolling the system environment. System PHI is derivedfrom a 19.6608 MHz quartz oscillator divided by eight. Anadditional 16.589 MHz oscillator is provided to the floppydisk controller for synchronous data separation. The CPU busis fully buffer to support stand alone system operation withfull memory and I/O compliments. The relationship of theseelements is represented in Figure 6.2-1, above.

The Z-80 CPU bus buffers are shown on Sheet One of theschematics. System PHI is generated by hybrid oscillator A29.Counter A22 produces the 2.46 MHz system clock as well as halfPHI for baud rate timing. The discrete circuit oscillator iscontrolled by a 16.589 MHz crystal and is used by the floppycontroller's synchronous data separator.

Data bus buffer A31 interfaces the CPU to the system bus(backplane) and drives toward the CPU during Ml or readcycles. Buffers A26 and A23 drive the system address bus.A32 drives outbound control signals such as Ml, IORQ, RD,etc., while A27 receives user provided inputs (e.g., INT, NMI,RESET, etc.).

Zilog clock driver A25 provides a MOS compatible clock sourcefor the LSI devices.

Sheet Two of the schematics detail the PROM/RAM implementationand the bus control logic for both A31 and A16 buffers.

Chip selects for A17-A19, A13 and A14 occur when promaddresses are decoded by Sheet Three logic. These decodedaddresses, along with I/O and interrupt requests fromperipherals A20 and A21 (Sheet Four) cause bus driver A16 todrive the system data bus toward the CPU. Automatic baud ratetiming is acquired through tristate A28 and data bit DO.

Sheet Three depicts the address decoding assignments for thefollowing:

Prom Firmware FOOOH - FFFFHDynamic Memory OH - EFFFHSystem Ports FOB - FFH

Adder A34 always translates addresses from OOH to FOOOH sothat ROM is always in low memory (OOOOH - OBFFH). Gates A7and All generate the page 15 address enable which allows

6-3

access to PROM when user memory is mapped to system memoryOOOOH and when a system access is made to OOOOH - OBFFH.System I/O ports are decoded by the logic of A2 and A3.

Sheet Four contains the peripherals found on the CPU-2 card.The console interface is implemented by way of USART A21 andCTC A20. Highest priority in the daisy chain, the CTCprovides interrupt capability for the floppy disk interfaceand the USART status lines. Jumpers El and E2 allow receiverinterrupts from the USART. Flip-flop A8 provides a squarewave baud rate clock source to the USART.

6.2.1 Reset Logic

A power-on clear sequence, or depressing the WAIT button onthe front panel will reset the entire system to the Debuglevel, at which time an "S" character or a carriage returnmust be entered from the terminal to re-establish "handshake"with the system.

6.3 Hardware Breakpoint Module (Schematics, page E-59)

A block diagram of this module is shown in Figure 6.3-1. Thetype of transaction selected for the breakpoint, the specificaddress, and data mask are programmed through the ZAP softwareas the user issues terminal commands. The breakpoint module isaddressed at CPU I/O Port FBH. The logic is designed so thatsuccessive writes to Port FBH will load all these programarguments via the system data bus into an internal data busand then into various registers on this module according tothe following sequence:

1st write: Load type of transaction (mode).2nd write: Load data argument register.3rd write: Load lower 8 bits of address argument.4th write: (If memory transaction) Load upper eight bits

of address argument.5th write: Load data bus mask argument, if specified.

On Sheet 4 of the schematics, devices A7 and A14 make up thecycle counter that controls this loading sequence. A7 is amodule 8 binary counter which increments on each cycle of itsclock input. The clock input is, according to the logic onSheet 3, merely an I/O port write request to Port FBH. As A7increments, the five outputs of A14 go true successively toload the sequence of registers indicated above. All dataloaded into these registers is buffered by A29 and A30 onSheet 1. Then, in sequence:

6-4

1. One of five possible Control Bus Transactionsis clocked into A21 on Sheet 3.

2. An 8-bit data word is clocked into A22 and A23on Sheet 1.

3. The lower 8 address bits are clocked into A19and A20 on Sheet 2. ,

4. The upper 8 address bits are clocked into A17and A18 on Sheet 2.

5. The data mask register contents are clockedinto Al and A2 on Sheet 5.

NIK I I I IW K I I I

BREAKKMNT MODULE

Figure 6.3-1. Hardware Breakpoint Module

Thus, when program execution begins under emulation, thecontents of these registers are compared with the currentstates of the system address, data and status/control busses,and true compares will generate breakpoint and scope syncoutput signals on Sheet 4.

6-5

ADDRESS BUS

CONTROL BUS

STATUS BUS

DATA BUS

PORTFC

CONTROL LINES

LASTIN/FIRSTOLTMEMORY STACK

256 X 32 BITS

MEMORYADDRESSCOUNTER

Figure 6.3-2. Real-Time Storage Module

6.4 Real-Time Storage Module (RTSM2) (Schematics, page E-67)

The general layout of this card is shown in Figure 6.3-2.Sheet 2 of the schematics contains 2101-1 RAMs for thepush-down stack. The 16 address bits are stored after theyare clocked through latches A30, A31 and A32. A19 and A17 onSheet 2 store the 8 data bits via latches A27 and A25, whileA18 and A20 on the same sheet store the control and statusbits, respectively.

Register A9 on Sheet 1 will be loaded with selected bits toindicate which type(s) of transactions will be stored, and theAND gate A3 will pass a WRITE DATA signal to the RAMs any timesuch a transaction is detected on the system control bus.

6-6

Sheet 1 contains the counter that generates the addresses forthe 256-word stack. After the breakpoint is reached and thesystem returns to the debug environment, the contents of thestack can be read out for printing via buffers A28 and A29 onSheet 1.

6.5 Monitor Module (Schematics, page E-19)

This board performs several independent functions which willbe detailed.

Sheet 2 of the monitor schematics contains the circuitry tointerface both TTY or RS232 terminals to the serial TTL I/Odata streams generated and received by the CPU module.(Schematics, page 152)

On Sheet 2 of the monitor schematics, A30, A31, and A32comprise I/O port decoders, which turn an address on the lower8 bits of the address bus into enables for various I/O devicecontrol or data functions.

Sheet 1 contains the lamp drivers for the four front panellamps. Also, a buffer (A25) is enabled whenever an I/O readis performed to Port FEB. This will drive the following"System Status" information onto the system data bus: thestate of the MON and USER front panel switches (via debouncelatches), the state of the two rear panel sense switches, andthe BREAK STATUS signal from the breakpoint module. At thebottom of Sheet 1 is logic to turn breakpoint signals from anysort of change of mode into proper timing signals for the PODCONTROLLER.

6.6 64K Memory Module (Schematics, page E-25)

The Z-80 Development System contains one memory moduleconsisting of 64K bytes.

6.6.1 System Memory Organization

The memory is partitioned into sixteen 4K byte pages. Page 0begins at address OOOOH, page 1 at 1000H, etc. "(See Figure6.6.1-1.) Page 0 consists of the 4K bytes of system firmware.

6-7

60KD Y N A M I C R A M

\IK STATIC RAM <

3K P R O M

N

{

FFFFH

1000H

O C O O H

OOOOH

6.6.2

Figure 6.6.1-1. System Memory Organization

Interpretation of Schematic(64K MEMORY)

Sheet 2 contains bi-directional data buffers, with each bitdivided into a Data In and a Data Out line on the storagearray side of the buffer, to effect the required division ofthese two signals on the memory chip itself. The other sideof the buffers connects to the system data bus.

Sheet 2 also depicts multiplexers used to split the 14 addressbits into two 7-bit segments, in accordance with therequirements of the 16-pin 16K memory chips.

Sheet 1 contains the 60K strapping options. The discussion tofollow will assume that the board is wired for 60K capacity.This sheet contains the logic for generating the RAS (RowAddress Strobe) and CAS (Column Address Strobe) signals. Atthe memory chip, the RAS signal latches in the seven leastsignificant address bits from the multiplexer on Sheet 2;then, after sufficient delay to change the select on thismultiplexer, the seven most significant address bits arelatched into the memory chip by CAS.

6-8

There are four different RAS signals to select a differentgroup of memory chips for each of the four PS (Page Select)signals. These PS signals are generated on the processormodule from card select (CD) signals, and only one of the fourwill be true for any particular memory request. The PS signalis buffered by multiplexer All, and will be passed through Aland A2 when MRQ (Memory Request) timing signal is true. Theresulting signal is one of four possible RAS signals. In aMemory Refresh operation, all four RAS signals will beenabled.

The buffer A5 on the lower right causes a delay that allowsthe RAS to latch the first seven address bits; later, acontrol signal changes the select on the address multiplexer.After further delay, CAS is generated to latch the mostsignificant address bits.

Sheet 3 contains the memory array, organized 4 x 8 , tocorrespond to the four different RAS (page select) signalsand to the eight bits per data word.

6.7 Floppy Disk Controller (Schematics, page E-49)

The Z-80 Development System utilizes a dual Shugart 801 floppydisk drive for bulk storage of data and operating programs.The controller is designed to use 32 sectors (records) pertrack and 77 tracks per disk. It provides all controlfunctions for two disk drives. The controller's operationsare facilitated by the fast interrupt response of the CPU, theprogrammable timing features of the CTC module, and the Z-80I/O block transfer capability.

6.7.1 Data Format

All formatting of the data on the disk is accomplished underthe control of the CPU. Figure 6.7.1-1 represents theformatting structure: 16 bytes of all zeros for the preamble;one byte for sector address with the first bit being a startbit; one byte for the track address; then 128 bytes of data; 4bytes of linkage (forward/backward) for file maintenance; 2bytes of CRC; and then a postamble of all zeros.

6.7.2 Sector Recording Format

In this format, the user may record up to 32 sectors (records)per track. Each track is started by a physical index pulse,and each sector is started by a physical sector pulse. This

6-9

type of recording is called hard sectoring.

6.7.3 Tracks

The Shugart drive is capable of recording up to 77 tracks ofdata. The tracks are numbered 0-76. Each track is madeavailable to the read/write head by accessing the head with astepper motor and carriage assembly.

Basic Track Characteristics

Number bits/trackIndex pulse widthIndex/sector pulse width

Unformatted

41,300 bits1.7+/-.5 ms

.2 ms

Formatted

32,768

FORWARD/BACKWARDLINKAGE FOR FILE

PREAMBLE! ?!*IT.™C°K DATA BLOCK LINKAGEAODR.I AOOR. CF.C POST AMBLE

4 BYTES 2 B^TES16 BYTES I BYTE 1 BYTE 128 BYTES

ISECTOR ADDRESS -

Figure 6.7.1-1 DISK FORMAT

6-10

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OPTIONAL

FROM DISK

READ

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Figure 6.7.4-1. Floppy Disk Controller

6.7.4 Controller Functional Description

Zilog's simple controller, which interfaces the disk drives,is diagrammed in Figure 6.7.4-1. The controller enables theuser to store or retrieve information from any one of the diskdrives under its control. Under Z-80 CPU control, itpositions the head carriage assembly at the desired track;locates the field of interest; and either writes or reads.Read/Write transfer of data takes place through the Z-80 CPUI/O channel. The controller's basic functions are read dataseparation, write data assembly, and parallel/serial dataconversion.

1. ERROR CONTROL: The controller includes a CRC generator andchecker to insure that all data has been properly recordedand retrieved from the disk. During a write data assembly,a 16-bit CRC is appended by the controller as the last twobytes of data. During Read operations a hardware check onthe 16-bit CRC code is performed and the result is

6-11

monitored by the CPU. Every sector of disk data containsits own sector and track address. The CPU checks thisaddress after every Read operation to insure that it wascorrect.

2. CONTROL AND STATUS: The status register permits thecontroller to advise the CPU of the condition of the diskvia Port F9H by monitoring Ready, Index, Track 0, and CRCcheck.

Port F8H is used to control the desired disk through theselect, step, and direction lines.

3. WRITE DATA: Write Data is latched from the CPU into theparallel-to-serial shift register and shifted out to theCRC generator and on to the data encoder where it is gatedwith the 2-phase clock signal, at the rate of one clocktime per bit cell. ,

4. READ DATA: The combined Read Data and Read Clock are gatedinto the data separator with the 8-phase clock. The datais separated from the clock and fed into the start bitdetector to sense the end of all zero preamble. Upondetection of the first bit in the sector address byte, thedata is fed into the serial-to-parallel register and out tothe CPU data bus.

5. WAIT: In order to match the disk transfer rate and the CPUsoftware transfer rate, it is necessary to slow down theinstruction execution time of the processor through the useof the WAIT line. The WAIT control logic performs thisfunction.

6.7.5 Recording Format

The format of the data recorded on the diskette is totally afunction of the system resident firmware. Data is recorded onthe diskette using frequency modulation as the recording mode;i.e., each data bit recorded on the diskette has an associatedclock bit recorded with it. This is referred to as FM. Datawritten on and read back from the diskette takes the formshown in Figure 6.7.5-1. The binary data pattern shownrepresents a 101.

6-12

CLoacsrrs

DATA am

Figure 6.7.5-1. Data Pattern

a. BIT CELL - As shown in Figure 6.7.5-1, the clock bits anddata bits (if present) are interleaved. By definition, abit cell is the period between the leading edge of oneclock bit and the leading edge of the next clock bit.

b. BYTE - A byte, when referring to serial data (being writtenonto or read from the disk drive) is defined as 8consecutive bit cells. The most significant bit cell isdefined as bit cell 0, and the least significant bit cellis defined as bit cell 7. When reference is made to aspecific data bit (i.e., data bit 3), it is with respect tothe corresponding bit cell (bit cell 3).

During a write operation, bit cell 0 of each byte, istransferred to the disk drive first with bit cell 7 beingtransferred last. Correspondingly, the most significant byteof data is transferred to the disk first, and the leastsignificant byte is transferred last.

When data is read back from the drive, bit cell 0 of each bytewill be transferred first with bit cell 7 last. As withwriting, the most significant byte will be transferred firstfrom the drive to the user.

Figure 6.7.5-2 illustrates the relationship of the bits withina byte, and Figure 6.7.5-3 illustrates the relationship of thebytes for read and write data.

6-13

C 0 C 0 C

BITCELL*

MSB

BITCELLI

BITCELL:

BITCELLS

BITCELL 4

BITCELL 5

BITCELL 6

BITCELL:

USB

BITCELL«

BINARY REPRESENTATION OF .

DATA BITS

CLOCK BITS

HEXADECIMALREPRESENTATIONOF-

DATA BITS

CLOCK BITS

Figure 6.7.5-2. Bits Within a Byte

MH I I II o I ' I : I 3 I •» I 10 it i:(BYTE!

IJ I U I 15 I 16 I?

tBIT CELL OOF BYTE »ISFIRST D VIA TO BE SECTTO THE DRIVE HHENHRITINC A.NO FROM THEDRIVE WHEN READING

BIT CELL T OF BYTE IT ISUST DATA TO BE SENT TOTHE DRIVE V»HEN WRITING\ND FROM THE DRIVEKHEN READING

DATA BYTES

Figure 6.7.5-3. Data Byte Relationships

6-14

6.8 Z-80A CPU Emulator Sub-System(Schematics, pages E-l, E-7, E-15, E-17)

The purpose of the Development System Z-80A CPU Emulator is topermit real-time analysis and debugging of hardware andsoftware systems. This tool presents the user with a minimumnumber of restrictions while providing him with a maximumnumber of capabilities.

s6.8.1 Introduction t

The Z-80A CPU emulator module for the Development Systemconsists of three sub-assemblies: the User Pod Controller, theUser Pod, and the Emulator. The User Pod Controller is housedin the Development System and provides an interface betweenthe User Pod/Emulator and the Development System. The UserPod is an integral part of the six-foot user cable andcontains all time critical Emulator control logic and buffersto interface the Emulator to the user cable. The Emulator isa special version of the Z-80A CPU that replaces the Z-80 CPUor Z-80A CPU in the User System. It should be noted that onlyCPU activity, which is performed by the Emulator, is testedfor break conditions and is stored in the real time storagemodule. The entire system is shown in Figure 6.8.1-1 whileblock diagrams of the User Pod and User Pod Controller areshown in Figures 6.8.1-2 and 6.8.1-3. The major features ofthe system are:

1) The system is capable of real-time debug of systemswith a CPU clock rate up to 4MHz.

2) The only deviations from an actual CPU are anadditional 200 microampere, 30 picofarad load and amaximum low level output voltage of 0.51 volts.

3) Disk-based debug software that allows the usercomplete visibility into the operation of thehardware/software system.

4) Uses real time storage module to record the data bus,address bus, and control bus status during the mostrecent 256 bus transactions.

5) Uses breakpoint module to monitor and test for userspecified condition on the data bus, address bus, andcontrol bus.

6) Memory mapping and protection in blocks of 1024 bytes.

6-15

7) Hardware check of user clock integrity.

8) User system dynamic RAM refresh is maintained whileemulation is halted.

6.8.2 Capabilities

The Z-80A Emulator module is designed to allow the user to setand display any memory location in user memory space, set anddisplay any I/O port in the user I/O space, or set and dsplaythe current status of the Emulator. t

A memory mapping function is provided that allows the user todefine the specific nature of his memory address space. The64K- bytes of the user memory space are divided into 64 IK-byteblocks. Each block may be defined to exist in either the UserSystem, the Development System, or to be non-existent. If ablock is defined to be non-existent, any access to that blockcauses a break in emulation. If a block is defined to existin the Development System, then an address transformation maybe specified. This address transformation allows a block ofDevelopment System memory to respond to an address other thanthe physical address assigned to that block. As an example,assume that the memory block in the user space defined by therange FCOOH to FFFFH is mapped into the Development Systemmemory block 1000H to 13FFH. When the User System accessesmemory at address FC20H, the Development System memory at1020H will respond. This memory mapping function also allowsany IK block to be write-protected. When a block iswrite-protected, all writes to that block are inhibited. Inaddition, the user may specify that a break be generated whena write is attempted on a protected block. A map specifiedfor an emulation applies to all memory accesses made duringthat emulation regardless of what generates the memory accessrequest. This means that the map is used by all devices inthe User System that access user memory; DMAs, other CPUs, andthe emulator, provide that the user system design respondsproperly and buffers are bi-directional.

The user may select to run on either the internal (system)clock (2.5MHz) or an external (user) clock. The clock signalis monitored and a break is generated if the clock fails tomeet minimum frequency specifications (250KHz). Theaddressing of the user I/O space is determined by the clockand the system mode that has been selected as described inFigure 6.8.2-1. The purpose of allowing the emulator moduleto operate with the Development System clock is to insure thatsoftware programs can be debugged using the real time storagemodule and breakpoint module.

6-16

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6-19

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All I/O in DSEO-FF used

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Figure 6.8.2-1.

6.8.3 Architecture

The Z-80A CPU Emulator module described in this document isdesigned to replace Zilog's original user interface, in thoseapplications requiring 4MHz emulation. This new Emulatormodule contains an emulator to emulate either a Z-80A CPU or aZ-80 CPU in the User System. The Emulator appears to the UserSystem as a Z-80A CPU with a 200 microampere load, 30picofarads additional input capacitance and an increasedmaximum oputput low voltage. (Maximum Vol = 0.51 volts.Maximum high level load - 20 microampere. Maximum low levelload = 200 microampere.) The only CPU allowed to access theuser memory or I/O space is the emulator. While few changeswere required on the breakpoint module and the real timestorage module, the modules have been removed from theDevelopment System bus and placed on a special bus driven bythe User Pod Controller. Because the pinout of the User PodController is completely different from the user interface,the entire Jl connecter has been re-wired. In addition, themonitor module has been modified so that the MON buttongenerates a manual break for the debug software. The Userbutton has been disabled so that the only way to start anemulation is through the debug software.

6.8.4 Restrictions

The User System must not prevent the Development System memoryfrom being refreshed. As an example, the User System may notperform an extended DMA operation that does not generatememory request and refresh. This restriction can beeliminated by replacing the standard Development Systemdynamic RAM with an optional static RAM memory module.

When a portion of the user memory space is mapped into theDevelopment System, some WAIT states may be inserted to insure

6-20

that data reaches the emulator. This means that emulation maynot be in real-time if memory is mapped into the DevelopmentSystem. Since the duration of the WAIT state is determinedonly by the emulator module delay and the Development Systemmemory access speed, no WAIT state is required by userhardware operating with low frequency CPU clocks while severalWAIT states are required by user hardware operating with highfrequency CPU clocks. The number of wait states will beminimized with the use of the optional high speed static RAMboard.

The emulator module is designed not to restrict the maximumfrequency of the user's CPU clock, but the real time storagemodule (RTSM) and the breakpoint module will only operate upto 4MHz. |

The Emulator module makes one restriction on the User Systemdesign. When memory is to be mapped into the DevelopmentSystem, then the User System memory and data bus buffers mustremain inactive when Memory Request is inactive. The Emulatorwill not issue a MRQ- to the user system when DevelopmentSystem memory is accessed. In addition a special signal,called System Memory Access, is provided to the user todisable his memory and data bus buffers. It should be notedthat system level emulations are performed to display, and setmemory, or, to display and set registers. When theseemulations are run, a portion of Development System memory isautomatically mapped into the User Memory space; therefore,ZAP will not run properly if this design restriction isviolated.

6.9 Hardware Overview

The Z-80A Emulator Module for the Z-80 Development Systemconsists of three sub-assemblies: the User Pod Controller, theUser Pod, and the Emulator. The User Pod Controller containsthe control and interface electronics necessary to interfacethe Z-80 Development System to the User Pod. The User Podcontains the cable buffer-drivers and time criticalelectronics required to interface to the emulator. Theemulator is a special Z-80A CPU which replaces the Z-80 CPU orZ-80A CPU in the system under development. The Z-80A EmulatorModule is shown in Figure 6.9-1. This configuration allowsin-circuit emulation of the microprocessor in all systemsdeveloped around the Z-80 and Z-80A families of microprocessorand support devices.

The following signal naming convention has been used throughout this document. All signal names are written in upper case

6-21

letters and match the names used on the logic diagrams.Negative true (active low) signals are indicated by appendinga minus sign to the end of the name. For example, CPU AB 0 isa positive true (active high) signal derived from address busbit 0 of a CPU. A logic 1 is represented by a voltage greaterthan 2.4 volts. Similarly, CPU RD- is a negative true (activelow) signal derived from the read line of a CPU. A logic 1 isrepresented by a voltage less than 0.8 volts.

Emulator

Figure 6.9-1. User Pod, Pod Controllerand Emulator Relationships

6-22

SECTION 7

THE EMULATOR

7.1 EMULATOR (Schematics, page E-15)

The emulator supplied with the Z-80A CPU Emulation Module maybe configured to operator in three modes: Software System,Hardware System-User Clock, and Hardware System-System Clock.The Software System emulator obtains power and clock from theDevelopment System and is not intended to be inserted into aUser System. The Hardware System-User Clock emulator obtainspower and clock from the User System and is intended toreplace the Z-80 CPU or Z-80A CPU in the User System. TheHardware System-System Clock emulator obtains power from theUser System and clock from the Development System and is alsointended to replace the CPU in the User System. WhileHardware System-System Clock emulator makes the selected clockavailable to the User System on the clock pin of the emulator(Pin 6), it is provided only for the early phases of systemdebug when clock loading is light. It must be remembered thatthe clock that is selected by the emulator determines what I/Oports are available to the system being developed. WhenSystem Clock is selected, all I/O ports exist in theDevelopment System and ports EO hex through FF hex are used bythe Development System. When user clock is selected all portsare located in the User System.

. MONITOR MODE . USER MODE

. All I/O in DSEO-FF used

. All I/O inUser Systemexcept EE & EF

All I/O in DSEO-FF used

All I/O inUser System

•

System. CLOCK

. USER

. CLOCK• «

The emulator consists of a 2-80A CPU emulator and a shieldedinterface cable. The Z-80A CPU emulator is a special versionof a Z-80A CPU with the following characteristics:

1) Program execution can be stopped at any time.

2) Dynamic RAM is always refreshed.

7-1

3) The CPU can execute from either "User Memory" or"System Memory".

4) When stopped, the status of all registers can bedetermined.

5) Timing characteristics identical to a Z-80A CPU.

6) AC/DC characteristics identical to a Z-80A CPU withthe following maximum variations on all pins:

20 microampere high-level preload200 microampere low level preload30 picofarad capacitive preload0.51 volts output low voltage

7.2 Z-80A CPU EMULATOR (Schematic, Page E-17)

This schematic shows the logic contained in the hybrid Z-80ACPU emulator. This hybrid is a Z-80A CPU with externallycontrolled MOS-FET switches to permit the control of BUSRQ-,INT-, NMI-, MRQ-, and WR-. Since it is necessary to shut offMRQ- and WR- when they are active, an active pull-up has beenadded. The three transistors in the WAIT- path form an ORgate that combines the USER WAIT- and the SWITCH WAIT-generated by the system.

*av

Jl@Ti

f=\

CLOCK SELECT4- INTERNAL

EXTERNAL

POWER SELECT4- EXTERNAL-» INTERNAL

7-2

SECTION 8

THE USER POD

8.1 USER POD (Schematics, page E-7)

The primary purpose of the User Pod is to provide buffers thatisolate the six-foot user cable from the Emulator. Inaddition, the User Pod contains the logic that maps memory andthe logic that stops the Emulator. Hysteresis buffers(74LS240-74LS244) have been used for both drivers andreceivers to maximize noise immunity and minimize loading andpower dissipation. All cable drivers use series terminationsto further reduce power dissipation. These drivers andreceivers are shown on Sheets 1 through 5 of the User Podlogic diagram. Three state buffers (74LS125 - shown on Sheet3) permit the Development System or User Pod Controller togenerate WAIT-, BUSRQ-, RESET-, and NMI for the User System.The clock driver (A25) used to supply the Emulator with systemclock is also shown on Sheet 3.

The Emulator is stopped by forcing it to execute a jumprelative instruction with an offset of -2 (18 hex, FE hex).This instruction keeps the program counter of the Emulatorfrom being advanced while keeping the dynamic memory of theUser System refreshed. This instruction sequence is generatedby the read-only memory (7603) at location Al, shown on Sheet1, when the Emulator module is idle. During this time, thecontrol logic at the top of Sheet 5 and on Sheet 6 drives WRENA and MRQ ENA to the inactive state (low). These twocontrol signals cause the Emulator to stop issuing MRQ- andWR- to the User System, thus disabling all read and writeoperations on the User Memory. In the event that the memory ofthe User System would respond without these signals, a SYS MEMACCESS signal is made active (high) and available on theEmulator so that the User Memory may be disabled when theEmulator is idle or accessing memory mapped into theDevelopment System. The Emulator always issues MRQ- duringthe refresh portion of the Ml cycles.

The exact nature of the User Memory space is stored in astatic random access memory located at A7 (shown on Sheet 4).When this memory map is read or written, it is accessedthrough port OEFH. The 64 bytes of storage in the RAM aretreated as 64 registers within the single I/O port. Theaddress lines for this RAM are multiplexed between theEmulator trace address lines and the map address linessupplied by the User Pod Controller. The state of thismultiplexer is controlled by the MAP SEL bit of the controlport (bit 1, port OEEH) located on the User Pod Controller.

8-1

For proper operation of the mapping logic, the MAP SEL bitmust be reset (0) when the Emulator is running an emulation.

During an emulation, the six high order address bits are usedto access the map RAM, thus permitting each 1024-byte block ofuser memory to be given one of the attributes listed below.

1) Nonexistent: no access is permitted; a break isgenerated if access is attempted.

NOTE: The instruction involving the access is completedbefore the break is generated; therefore, aninvalid instruction may be executed.

2) User: read/write access is permitted.

3) User/write protected: read access is permitted; writeaccess is not permitted and will generate a break ifthe WP INT ENA bit of the User POD Controller controlport is set (Bit 3, Port OEEH) .

4) System <n>: Development System memory block <n> isaccessed instead of this User Memory block; read/writeaccess is permitted; some wait states may be insertedto adjust for cable delays.

5) System block <n>/write protected: Development Systemmemory block <n> is accessed instead of this usermemory block; read-only access is permitted whilewrite access is not permitted and will generate abreak if the WP INT ENA bit of the User POD Controllercontrol port is set (Bit 3, Port OEEH).

NOTE: In the case of a write access to a write protectedblock of memory the WR- signal does not go active.As a result, the memory sees a memory access cyclewith only MRQ- active (neither RD- or WR- areactive), and no entry will be entered in thehistory.

NOTE: All operations using the User System Address Busare affected by the memory map RAM, since the UserAddress Bus is used to address the RAM. This meansthat DMA (direct memory access) operations may busrequest the Emulator and use the same memory spaceof their operation, but if the User System designuses uni-directional buffers on the Z-80 CPUaddress bus of the Z-80 CPU, then addressesgenerated by DMA or other processors cannot reachthe map RAM, and no mapping will be performed.

8-2

SECTION 9

THE USER POD CONTROLLER \

9.1 USER POD CONTROLLER (Schematics, page E-l)

The User Pod Controller provides all the control logic for theUser Pod as well as the receiver-drivers used to interface theUser Pod to the Development System. Here again, hysteresisbuffers were used (74LS240-74LS244) to minimize power andmaximize noise immunity. Control functions performed by theUser Pod Controller include detecting invalid memory access(nonexistent memory or write protect violations), starting andstopping an emulation, verifying the integrity of the clock,adding wait states to adjust for cable delays, and generatingbreak request interrupt vectors.

The table below summarizes the port assignments in the UserPod Controller. Each of these ports is discribed in greaterdetail in the sections that follow.

Table 9-1. User Pod Controller Port Assignments

Ports E4-E7 (Hex)

Port E8 (Hex)

Port E9 (Hex)

Port EA (Hex)

Port EB (Hex)

Port EE (Hex)

Port EF (Hex)

Four cascaded CTC channels for emulationtime-out breaks andinstruction-counting breaks (cascaded0-1-2-3).

CTC Channel Zero; bad clockinterrupt generator.

CTC Channel One; non-existentmemory interrupt generator.

CTC Channel Two; write-protectviolation interrupt generator.

CTC Channel Three; breakinterrupt generator.

User Interface control port

User Memory Map.

9-1

9.2 Memory Map Software Interface

All access to the memory map are made by instructions of theclass IN (C),<r> or OUT (C), <r>. These instructions placethe contents of the C register on the low order address lines,the contents of the B register on the high order addresslines, and the contents of the <r> register on the data bus.Therefore, the C register contains the map port address(OEFH), the <r> register contains the memory map definition,and the B register contains the right justified high order sixbits of the block address. For example:

LD A, 081H ;SYSTEM MEMORY 8000H, WRITE ENABLELD B, 005H ;USER ADDRESS 1400H —> BLOCK 5HLD C, OEFH ;MAP PORT ADDRESSOUT (C), A ;SET MAP DEFINITION

This routine programs the memory map RAM to transform theaddress 1400H generated by the emulator into an access toDevelopment System memory location 8000H with write operationsallowed. The data bus bits have the following meaning forboth read and write to port OEFH.

BIT MEANING

0 0=write protectedNo write access is allowed. Abreak is generated if bit 3 ofthe control port (EEH) is alsoset.

1 l=User memoryUser memory will be accessed.

0=System memoryDevelopment System memory willbe accessed, wait states willbe inserted as required.

The following bits will be used to addressDevelopment System memory if bit 1 is 0.

2 System memory address bus bit 10This bit is used to indicatenon-existent memory, when bit1 is 1.

3 System memory address bus bit 114 System memory address bus bit 125 System memory address bus bit 136 System memory address bus bit 147 System memory address bus bit 15

NOTE: Setting bits 1 and 2 to a logical 1 (high)defines that block as nonexistent.

9-2

9.3 User Pod Control Port *i

The User Pod Controller control port OEEH may be accessed withany input or output instructions. The bits of this port havethe following meanings:

BIT ON WRITE ON READ

0 RUN EMULATION RUN EMULATION1 MAP SELECT MAP SELECT2 not used EMULATOR HALT STATUS3 WRITE PROTECT WRITE PROTECT

INTERRUPT ENABLE INTERRUPT ENABLE4 RESET EMULATION RESET EMULATION

MODULE MODULE5 EMULATION INTERRUPT EMULATION INTERRUPT

ENABLE ENABLE6 not used BAD CLOCK STATUS7 not used System CLOCK SELECTED

RUN EMULATION (Bit 0): When set to 1, the Development SystemCPU is bus requested and the Emulator is enabled whenBUSAK- becomes true. This bit is reset to idle byPOWER-ON CLEAR-, RESET USER INTERFACE-, or the generationof a break request interrupt.

MAP SELECT (Bit 1): Must be reset to 0 to allow the maplogic to function properly during an emulation. When setto 1, the map logic takes the address information fromthe Development System address bus through the User PodController instead of from the Emulator. This bit isreset by POWER-ON CLEAR- or RESET USER INTERFACE-.

EMULATOR HALT STATUS (Bit 2): A read-only status bitindicating that the Emulator is halted as a result ofexecuting a HALT instruction. The bit is high as long asthe Emulator remains halted.

WRITE PROTECT INTERRUPT ENABLE (Bit 3): When set to 1, anyattempt to write protected memory will generate a breakinterrupt. This bit is reset by POWER-ON CLEAR- or RESETUSER INTERFACE-.

1

RESET EMULATION module (Bit 4): While this bit is set (to1), all User POD Controller logic is held reset (noemulations may be run). In addition, the RESET- line tothe Emulator/User System is held active (low). This bitis reset by POWER-ON CLEAR- and generates the signalRESET USER INTERFACE-.

9-3

EMULATION INTERRUPT ENABLE (Bit 5): When this bit is set to1, both non-maskable interrupts and maskable interruptswill be accepted by the Emulator while running anemulation. When this bit is reset to 0, all interruptsare ignored by the Emulator while running an emulation.The Emulator ignores all interrupts when it is idle.This bit is reset by POWER-ON CLEAR- or USER INTERFACERESET-.

!BAD CLOCK STATUS (Bit 6): A read-only status bit indicating

that a valid clock is present at the Emulator if the bitis set.

SYSTEM CLOCK SELECTED (Bit 7): A read-only status bitindicating that an Emulator that expects system clock isattched to the USER POD. A high indicates that Systemclock is used. A low indicates that the User clock isused.

The sequences listed below are used to control the Emulator

NORMAL RUN SEQUENCE

A) Run is set (performed by software)B) Request Development System bus (Performed by

hardware)C) Receive bus acknowledge from Development System

(performed by hardware)D) Start running emulation on next Ml cycle

(performed by hardware)

NORMAL IDLE SEQUENCE

A) Run is reset (performed by software underemulation)

B) Complete I/O instruction (resetting run)C) Execute one additional single opcode instructionD) Begin idle on next Ml cycle (two-Mi cycles

after resetting run)E) Drop bus request (performed by hardware)

NOTE: Software that resets the run latch duringemulation must keep track of the value of the

(- PC, because the real time storage module willnot contain the first idle instruction.

9-4

BREAK HALT

A) When interrupt is generated by bad clock, writeprotected, non-existent memory, br.eak, ortime-out of software timer

B) Reset run (performed by hardware)C) Complete current instructionD) Begin idle on next Ml cycle (first Ml cycle

after interrupt)E) Drop bus request (when the Development System

comes back on the bus, the interrupt line is active).

NOTE: The value of the PC may be determined by examiningthe address stored in the last entry in thereal time storage module. This entry should showan instruction fetch of data 18H (the first machinecycle of a jump relative minus two). ,

i

9.4 User Pod Controller (Sheet 1) j

The buffers at All and A15 receive the Emulator address busand allow these address bits onto the Development Systemaddress bus when an emulation is running. The high order sixaddress bits (SAB 10, SAB 11, SAB 12, SAB 13, SAB 14, and SAB15) of this bus are sent only to the breakpoint Module and thereal time storage module so that unmapped address informationis used for break and history activity. Buffer A10 buffers thelow order address bits of the Development System to the portdecoder logic and Z-80 CTCs shown on Sheets 2 and 5. Thelogic below All supplies the real time storage module with thecorrect I/O request signal. When an emulation is running,IORQ- must come from the Emulator, and when the Emulator isidle, the IORQ- must come form the Development System.

This sheet contains most of the memory map interface logic.The buffer at A8 receives the output from the memory map RAMand allows it onto the data bus of the Development System topermit the reading of the map. Buffer A7 receives the outputfrom the memory map RAM to provide an interface to theDevelopment System address bus, the NO-MEMORY detector, andthe write protect violation detector. The mapped addresslines (MAPPED AB 10, MAPPED AB 11, MAPPED AB 12, MAPPED AB 13,MAPPED AB 14, and MAPPED AB 15) are placed on the DevelopmentSystem memory address bus so that mapped address informationis used to access the memory. The buffer Al drives the sixleast significant address bits of the Development System highorder address bus out to the memory map RAM along with the mapcontrol lines.

9-5

9.5 User Pod Controller (Sheet 2)

The buffers at A13 and A14 receive the control bus of theEmulator and pass Ml-, RD-, WR-, IORQ-, RFSH-, HALT-, MRQ-,and SBUSAK- on to the Development System control bus and realtime storage module. The Emulator clock (TRC PHI) is alsobuffered and sent to the monitor module. The logic at themiddle of Sheet 2 provides the write protection for theDevelopment System memory when activated write protectionviolation break requests are also generated in the logic atthe middle of Sheet 2.

Sheet 2 shows the two Z-80 CTC devices used to generate breakinterrupt vectors. The upper CTC uses channel zero for thebad clock vector, channel one for the non-existent memoryvector, channel three for the break vector. The second CTC iswired as a very large programmable timer. This timer can beprogrammed to break emulation after a period of time, if noother breaks have occured. The timer is triggered by thefirst Ml- after the run latch is set and counts the 2.5MHzclock of the Development System until the channel programmedto interrupt reaches zero then an interrupt is generated thatstops the emulation. This CTC can also be programmed as acounter, then it counts MIS- which occurs once per instructionthereby counting instructions and again interrupting when theappropri- ately programmed channel reaches zero,. Theremainder of the logic at the bottom of Sheet 2 generates thecontrol signal that determines the direction of the data busdrivers of the User Pod Controller.

9.6 User Pod Controller (Sheet 3)

The buffer at A2 drives general control signals to the UserPod. The remainder of the logic on Sheet 4 interfaces theDevelopment System data bus to the User Pod/Emulator data busand to the User Pod Controller internal data bus.

9.7 User Pod Controller (Sheet 4)

The logic at the top of Sheet 4 is used for starting andstopping emulations. The Development System CPU sets the runbit (bit 0, port OEEH) which makes RUN REQ active andgenerates a BUSRQ- to the Development System CPU. When theDevelopment System responds with BUSAK-, the run latch (A20)is clocked set by the leading edge (high to low transition) ofthe Ml- from the Emulator. Once the run latch is set, STOPbecomes false (0) and allows the Emulator to run. If theEmulator resets the run bit of the control port, then thesecond Ml- clocks the run latch reset and halts the emulationby idling the Emulator. This action of the run latch permits

9-6

the Emulator to reset the run latch and execute one additionalsingle opcode instruction to position the program counter orload a register. However, if a break request is generated,then the monitor module drives FORCE NOP true (high) whichcauses the run latch to be reset. This procedure also assuresthat the emulation will stop at the end of any instructionthat generates a break. The Real Time Storage Module andBreakpoint Module in the Development System are now enabled byRUN instead of MONITOR. This allows both modules to operatein both monitor mode and user mode. When an emulation isstopped by a break condition, then the last entry in the RealTime Storage Module contains the PC in the address field. Onthe other hand, if the emulation was stopped by resetting therun bit (bit 0, port OEEH), then the Real Time Storage Modulemay not contain a value that accruately reflects the PC.However, since the control program caused the run bit toreset, it also knows the actual value of the PC. For example,if the following program were executed by the Emulator,

iORG 8000HLD A,0 ;DATA TO RESET RUNOUT (OEEH),A ;RESET RUNJP 0000 ;USE EXTRA INSTRUCTION TO

; POSITION PC

the Real Time Storage Module would show a last event of memoryread from address 8006H, data of OOH, while the PC would beOOOOH.

The remainder of the logic on Sheet 4 is used to buffer theDevelopment System clock and the Development System controlbus into the internal clock and control bus used on the UserPOD Controller. The same buffer is also used to drive theenable interrupts control signal out to the POD.

«

9.8 User Pod Controller (Sheet 5)

The logic at the top of Sheet 5 is the I/O port decoder logicfor the User POD Controller. Ports OE4H through OE7H aredecoded for selecting the second Z-80 CTC on Sheet 2, whileports OE8H through OEBH are decoded to select the first Z-80CTC on Sheet 2. Port OEEH is decoded for the control portwhich is the logic at the bottom of Sheet 5, and port OEFH isdecoded to be the memory map port. All ports of theDevelopment System are accessible to both the DevelopmentSystem and the Emulator in accordance with the followingtable.

9-7

MONITOR MODE . USER MODE

All I/O in DS . All I/O in DS . SystemEO-FF used . EO-FF used . CLOCK

All I/O in . All I/O in . USERUser System . User System . CLOCKexcept EE & EF

The one-shot at the bottom of Sheet 5 verifies that theEmulator clock has a period greater than 4 microseconds whichis the minimum clock for a Z-80 CPU. The state of thisone-shot can be read through the control port (bit 6, portOEEH) to verify that the Emulator is being driven by a clock.The second one-shot generates wait states for for the Emulatorwhen it accesses the Development System memory or I/O ports.The third one-shot generates wait states for the DevelopmentSystem when it accesses the memory map RAM,, The eight inputor-gate at A17 collects the various break requests andgenerates the BREAK EMULATION signal for the monitor module(shown as BREAK on the monitor module logic diagram). Themonitor module then guarantees that the current instruction iscompleted before issuing the FORCE NOP signal that stopsemulation. At the bottom of Sheet 5 is the buffer that bringsthe control port data bits onto the Development System databus when the control port is read.

9-8

APPENDIX A

PORT ASSIGNMENTS FOR THE ZDS-1/40

PORT ASSIGNMENTS FORTHE ZDS-1/40

ADDRESS READ FUNCTION WRITE FUNCTION

OFFHOFEHOFDHOFCHOFBHOF AHOF9HOF8HOF7HOF6HOF5HOF4HOF3HOF2HOF1HOFOH

OEFHOEEHOEDHOECHOEBHOEAHOE9HOE8HOE7HOE6HOE5HOE4HOE3HOE2HOE1HOEOH

BAUD RATE DETECTIONSTATUS PORTSOFTWARE SYSTEM RESETRTSM CONTROL PORTBRKPT CONTROL PORTDISK CONTROL PORT ADISK CONTROL PORT BDISK DATA PORTSET MONITOR MODENOT USEDUSART CONTROL PORTUSART DATA PORTSYSTEM CTC C3SYSTEM CTC C2 - BAUD RATESYSTEM CTC Cl - SER. CLK.SYSTEM CTC CO - DISK SECTOR

USER MEMORY MAP PORTUSER INTERFACE CONTROL PORTNOT USEDNOT USEDUSER INTF. BREAK GEN.

WRITE PROT. ERR.NO MEM. ERR.BAD CLOCK ERR.CASCADED CTC C3CASCADED CTC C2CASCADED CTC ClCASCADED CTC CO

USER INTF,USER INTF,USER INTF,USER INTF,USER INTF,USER INTFUSER INTF,NOT USEDNOT USEDNOT USEDNOT USED

NOT USEDNOT USEDSET USER MODERTSM CONTROL PORTBRKPT CONTROL PORTDISK CONTROL PORT ADISK CONTROL PORT BDISK DATA PORTSET MONITOR MODENOT USEDUSART CONTROL PORTUSART DATA PORTSYSTEM CTC C3SYSTEM CTC C2 - BAUD RATESYSTEM CTC Cl - SER. CLK.SYSTEM CTC CO - DISK

USER MEMORY MAP PORTUSER INTERFACE CONTROL PORTNOT USEDNOT USEDUSER INTF. BREAK GEN.

WRITE PROT. ERR.NO MEM. ERR.BAD CLOCK ERR.

USER INTF.CASCADED CTC C3USER INTF.CASCADED CTC C2USER INTF.CASCADED CTC ClUSER INTF.CASCADED CTC CONOT USEDNOT USEDNOT USEDNOT USED

USER INTF,USER INTF,USER INTF,

A-l

APPENDIX B

ZDS-1/40 CONFIGURATION

PCB LOCATION FOR ZDS-1/40

CONNECTOR

J01J02J03J04JOSJ06JOTJOSJ09J10JllJ12

PRINTED CIRCUIT BOARDS

POD CONTROLLER - Z-80A CPU EMULATORMONITORZDS/ASPIO, PROM PROGRAMMERPROM PROGRAMMERPROM PROGRAMMER, GIB, PIBPROM PROGRAMMERPROM PROGRAMMER, USER-DEFINABLE I/O32K, 48K, 60K DYNAMIC RAMCPUFLOPPY CONTROLLERBREAKPOINTREAL TIME STORAGE MODULE

I/O CONNECTORS

J13 LINE PRINTER CABLE (CIB/PIB)J14 USER DEFINABLE (SPARE)J15 USER DEFINABLE (SPARE)J16 FLOPPY DRIVE CABLEJ17 TERMINAL CABLEJ18 AUXILIARY SERIAL CABLEJ19 LINE PRINTER CABLE (ASPIO)J20 PROLOG PROM PROGRAMMER CABLEJ21 SPAREJ22 SPAREJ23 FRONT PANEL CABLEJ24 POWER CABLE

REAR PANEL CONNECTORS

J101 SPAREJ102 SPAREJ103 PROLOG PROM PROGRAMMERJ104 LINE PRINTER (ASPIO)J105 AUXILIARY SERIAL PORTJ106 TERMINALJ107 FLOPPY DISK DRIVESJ108 SPAREJ109 SPAREJ110 SECOND LINE PRINTER (CIB/PIB)

B-l

INTERRUPT DAISY CHAIN

PRIORITY CARD

1 J09 CPU2 J01 POD CONTROLLER3 JO3 ZDS/ASPIO4 JOS CIB/PIB

B-2

APPENDIX C

BACKPLANE DEFINITION FOR ZDS-1/40

BACKPLANE DEFINITION FOR ZDS-1/40

NAME=ZDS-1/40SYSTEM=ZDS-1/40REVISION=13-1079-02/REV.AGEOMETRY=Z DS.1.4 0.GEONETS=

+05V.1J01-059J23-009

+05V.2 :

J01-060J23-008

+05V.3J01-061J23-007

+05V.4J02-061J23-010

+12V.1J08-090J08-091J08-092J24-007

+12V.2J08-093J08-094J08-095J24-008

+12V.3J01-105J02-095J03-090J09-090J24-009

-05V.1J08-063J08-069J16-013J24-001

01

ZDS-1/40 BACKPLANE DEFINITION (cont.)

-05V.2J08-083J08-084J08-085J24-002

-05V.3J09-099J24-003

-12V.1J03-107J24-004

-12V.2J02-098J24-005

8.PHIJ09-023J10-023

AOOJ01-100J02-016J03-016J04-016J05-016J06-016J07-016J08-016J09-016Jll-016J12-016

A01J01-098J02-017J03-017J04-017J05-017J06-017J07-017J08-017J09-017Jll-017J12-017

ZDS-1/40 BACKPLANE DEFINITION (cont.)

A02J01-097J02-018J03-018J04-018J05-018J06-018J07-018J08-018J09-018Jll-018J12-018

A03J01-108J02-019J03-019J04-019J05-019J06-019J07-019J08-019J09-019Jll-019J12-019

A04J01-109J02-020J03-020J04-020J05-020J06-020J07-020J08-020J09-020Jll-020

C-3

ZDS-1/40 BACKPLANE DEFINITION (cent.)

A05J01-096J02-021J03-021J04-021J05-021J06-021J07-021J08-021J09-021Jll-021J12-021

A06J01-104J02-009J03-009J04-009J05-009J06-009J07-009J08-009J09-009Jll-009J12-009

A07J01-101J02-010J03-010J04-010J05-010J06-010J07-010J08-010J09-010Jll-010J12-010

A08J01-086J05-011J06-011J07-011J08-011J09-011Jll-011J12-011

C-4

ZDS-1/40 BACKPLANE DEFINITION (cont.)

A09J01-085J05-014J06-014J07-014J08-014J09-014Jll-014J12-014

A10J01-116J05-013J06-013J07-013J08-013J09-013

AllJ01-119J05-012J06-012J07-012J08-012J09-012

A12J01-115J09-042

A12+J08-042J09-068

A13J01-117J09-040

A13 +J08-040J09-066

A14J01-118J09-041

A15J01-114J09-043

C-5

ZDS-1/40 BACKPLANE DEFINITION (cont.)

ACK-.LPJ03-082J19-011

ACK-.LP2J05-082J13-011

ADDRESS.PROLOGJ05-117J20-015

BKPT.SEL-J02-070Jll-015

BREAK-J01-066Jll-100

BREAK.EMULATION-J01-077J02-102

BREAK.PENDINGJ01-004J02-103

BREAK.STATUSJ02-116Jll-085

BREAK.SYNCJll-101J23-003

BUSAK-J01-112J09-022

BUSRQ-J01-110J09-107

BUSY.LPJ03-076J19-023

C-6

ZDS-1/40 BACKPLANE DEFINITION (cont.)

BUSY.LP2J05-076J13-023

CARRIER.DETECTJ03-038J18-008

CD.O-J08-038J09-038

CD.l-J07-038J08-037J09-037

CD.2-J06-038J08-036J09-036

CD.3-J05-038J08-035J09-035

DOJ01-074J02-054J03-054J04-054J05-054J06-054J07-054J08-054J09-054J10-054Jll-054J12-054

C-7

ZDS-1/40 BACKPLANE DEFINITION (cont.)

DlJ01-068J02-055J03-055J04-055J05-055J06-055J07-055J08-055J09-055J10-055Jll-055J12-055

D2J01-075J02-057J03-057J04-057J05-057J06-057J07-057J08-057J09-057J10-057Jll-057J12-057

D3J01-072J02-056J03-056J04-056J05-056J06-056J07-056J08-056J09-056J10-056Jll-056J12-056

C-8

ZDS-1/40 BACKPLANE DEFINITION (cont.)

D4J01-070J02-047J03-047J04-047J05-047J06-047J07-047J08-047J09-047J10-047Jll-047J12-047

D5J01-071J02-048J03-048J04-048J05-048J06-048J07-048J08-048J09-048J10-048Jll-048J12-048

D6J01-073J02-051J03-051J04-051J05-051J06-051J07-051J08-051J09-051J10-051Jll-051J12-051

C-9

ZDS-1/40 BACKPLANE DEFINITION (cont.)

D7J01-069J02-052J03-052J04-052J05-052J06-052J07-052J08-052J09-052J10-052Jll-052J12-052

DATA. 1J06-065J22-001

DATA.1.LPJ03-065J19-001

DATA.1.LP2J05-065J13-001

DATA.2J06-066J22-002

DATA.2.LPJ03-066J19-002

DATA.2.LP2J05-066J13-002

DATA.3J06-067J22-003

DATA.3.LPJ03-067J19-003

C-10

ZDS-1/40 BACKPLANE DEFINITION (cont.)

DATA.3.LP2J05-067J13-003

DATA.4J06-068J22-004

DATA.4.LPJ03-068J19-004

DATA.4.LP2J05-068J13-004

DATA.5J06-069J22-005

DATA.5.LPJ03-069J19-005

DATA.5.LP2J05-069J13-005

DATA.6J06-070J22-006

DATA.6.LPJ03-070J19-006

DATA.6.LP2J05-070J13-006

DATA. 7J06-071J22-007

DATA.7.LPJ03-071J19-007

C-ll

ZDS-1/40 BACKPLANE DEFINITION (cont.)

DATA.7.LP2J05-071J13-007

DATA.8J06-072J22-008

DATA.8.LPJ03-072J19-008

DATA.8.LP2J05-072J13-008

DATA.RDYJ06-117J21-009

DATA.STBJ02-101Jll-114J12-114

DATA.STB-.LPJ03-073J19-009

DATA.STB-.LP2J05-073J13-009

DI.OJ06-104J21-001

DI.lJ06-105J21-002

DI.2J06-106J21-003

DI.3J06-110J21-004

C-12

ZDS-1/40 BACKPLANE DEFINITION (cont.)

DI.4J06-111J21-005

DI.5J06-113J21-006

DI.6J06-114J21-007

DI.7J06-115J21-008

DID.PROLOGJ05-104J20-019

DII.PROLOGJ05-105J20-020

DI2.PROLOGJ05-106J20-017

DI3.PROLOGJ05-110J2.0-018

DI4.PROLOGJ05-111J20-023

DI5.PROLOGJ05-113J20-024

DI6.PROLOGJ05-114J20-021

DI7.PROLOGJ05-115J20-022

C-13

ZDS-1/40 BACKPLANE DEFINITION (cont.)

DIRECTIONJ10-027J16-008

DIRECTION.REMEXJ06-081J22-010

DISK.CONTROL.A.PORT-J02-069J10-117

DISK.CONTROL.B.PORT-J02-068J10-118

DISK.DATA.PORT-J02-067J10-116

DOO.PROLOGJ05-093J20-011

D01.PROLOGJ05-094J20-012

DO2.PROLOGJ05-095J20-007

DO3.PROLOGJ05-096J20-009

«DO4.PROLOG

J05-097J20-010

DOS.PROLOGJ05-098J20-013

D06.PROLOGJ05-099J20-006

C-14

ZDS-1/40 BACKPLANE DEFINITION (cont.)

D07.PROLOGJ05-101J20-008

DRIVE.LTJ06-058J21-017

DRIVE.RTJ06-103J21-016

ERROR.PROLOGJ05-118J20-014

EXT.INHJ06-102J21-015

EXT.PHIJ09-058J09-115

FAULT-.LPJ03-078J19-012

FAULT-.LP2J05-078J13-012

FORCE.NOPJ01-103J02-106J09-106

FORCE.NOP.DELAYEDJ02-037J12-037

GND.01J03-062J13-018J13-019J13-020

C-15

ZDS-1/40 BACKPLANE DEFINITION (cont.)

GND.02

GND.03

GND.04

GND.0 5

GND.06

GND.07

GND.08

GND.09

J03-063J16-014J16-015J16-016

J03-064J16-017J16-018J16-019

J01-062J16-020J16-021J16-022

J01-063J16-023J16-024J16-025J16-026

J01-064J18-007J19-018J19-019J19-020

J02-120J20-025J21-011J21-012

J02-121J21-013J21-024J21-025

J02-122J22-016J22-017J22-018

C-16

ZDS-1/40 BACKPLANE DEFINITION (cont.)

GND.10J02-062J22-023J22-025

GND.llJ02-063J23-001

GND.12J02-064J23-002

GND.13J01-120J23-006

GND.14J01-121J23-013

GND.15J01-122J23-024

HALT-J01-089J02-027J09-027J12-027

HALT.LAMP-J02-005J23-020

HIS.IORQ-J01-095Jll-030J12-030

INDXJ09-078J10-007

C-17

ZDS-1/40 BACKPLANE DEFINITION (cont.)

INDX.O-J10-015J16-012

INPUT.MODE.SELJ06-074J22-014

INPUT.PRIME-.LPJ03-081J19-010

INPUT.PRIME-.LP2J05-081J13-010

INT-J01-107J03-109J05-109J09-109

INT.DAISY.CHAIN.1J01-102J09-079

INT.DAISY.CHAIN.2J01-087J03-088

INT.DAISY.CHAIN.3J03-112J05-088

INTERLOCK.PROLOGJ05-103J20-005

IORQ-J01-091J02-030J03-030J04-030J05-030J06-030J07-030J09-030J10-030

C-18

ZDS-1/40 BACKPLANE DEFINITION (cont.)

LOCAL.MODEJ03-092J18-010

Ml-J01-083J02-028J03-028J04-028J05-028J06-028J07-028J09-028J12-028

M1RQJ02-090Jll-090

M1S-J01-065J02-089

MODE.PROLOGJ05-102J20-003

MONITORJ01-106J02-110

MONITOR.LAMP-J02-006J23-022

MONTR.NCJ02-082J23-026

MONTR.NOJ02-083J23-025

MRD-J02-076J05-046J06-046J07-046J08-046

C-19

ZDS-1/40 BACKPLANE DEFINITION (cont.)

MRQ-J01-093J02-029J05-029J06-029J07-029J08-029J09-029Jll-029J12-029

ORIGINATE.MODEJ03-091J18-009

OUTPUT.MODE.SELJ06-087J22-015

PAPER.EMPTY.LPJ03-077J19-013

PAPER.EMPTY.LP2J05-077J13-013

PG.15-J05-039J06-039J07-039J08-039J09-039

PHIJ01-067J03-024J04-024J05-024J06-024J07-024J09-024

POWER.ON.CLR-J01-076J02-026J09-026Jll-026

C-20

ZDS-1/40 BACKPLANE DEFINITION (cont.)

PS.O-J05-034J06-034J07-034J08-034J09-034

PS.l-J05-033J06-033J07-033J08-033J09-033

PS.2-J05-032J06-032J07-032J08-032J09-032

PS.3-J05-031J06-031J07-031J08-031J09-031

PUNCH.COMJ06-073J22-011

PUNCH.RDYJ06-076J22-012

R.IJ03-089J18-022

C-21

ZDS-1/40 BACKPLANE DEFINITION (cont.)

RD-J01-092J02-045J03-045J04-045J05-045J06-045J07-045J09-045J10-045Jll-045J12-045

RD.CLK-J10-081J16-001

RDR.OUT.MODEJ06-119J21-010

RDR.RDYJ06-118J21-014

RDY-J10-016J16-011

READ.DATA-J10-009J16-002

REFRESH-J01-090J08-025J09-025

RESET.SW-J09-049J23-019

RESPONSE.PROLOGJ05-116J20-016

RESTART.D-J02-011J12-050

C-22

ZDS-1/40 BACKPLANE DEFINITION (cont.)

RS232.DATA.IN

RS232.DATA.OUT

RS232.RETURN

RUN

SA10

SA11

SA12

SA13

SA14

SA15

J02-093J17-002

J02-086J17-003

J02-091J17-007

J01-113J02-036Jll-111J12-111

J01-079Jll-013J12-013

J01-078Jll-012J12-012

J01-084Jll-042J12-042

J01-080Jll-040J12-040

J01-081Jll-041J12-041

J01-082Jll-043J12-043

C-23

ZDS-1/40 BACKPLANE DEFINITION (cont.)

SBUSAK-J01-088J12-022

SEL.O-J10-018J16-010

SEL.l-J10-084J16-009

SELECT.LPJ03-075J19-024

SELECT.LP2J05-075J13-024

SENSE.SW.l-J02-117J23-015

SENSE.SW.2-J02-118J23-014

SERIAL.INJ02-087J09-008

SERIAL.OUTJ02-085J09-015

STEP-J10-028J16-007

STOR.SEL-J02-066J12-066

SYNCJ03-049J18-024

C-24

ZDS-1/40 BACKPLANE DEFINITION (cont.)

SYS.RESET-J02-046J03-026J05-053J09-053J10-053

SYSMEMJ01-006J09-067

SYSTEM.RDYJ06-075J22-013

TAPE.ERRJ06-078J22-020

TAPE.LOWJ06-077J22-021

TCTSJ03-007J18-005

TDSRJ03-008J18-006

TDTRJ03-050J18-020

TERM.BUSYJ03-025J18-025

TRANSPER.PROLOGJ05-119J20-002

TRC.PHIJ01-099J02-024

TRK.OO-J10-011J16-004

C-25

ZDS-1/40 BACKPLANE DEFINITION (cont.)

TRTSJ03-006J18-004

TRXDJ03-005J18-003

TTXDJ03-004J18-002

TTY.DATA.INJ02-092J17-010

TTY.DATA.OUTJ02-084J17-016

TTY.IN.RETURNJ02-097J17-005J17-006J17-008J17-024

TTY.OUT.RETURNJ02-099J17-017

TY.HIJ02-012J09-046

USER.LAMP-J02-008J23-021

USER.NCJ02-077J23-012

USER.NOJ02-078J23-011

C-26

ZDS-1/40 BACKPLANE DEFINITION (cont.)

WAIT-J01-111J02-108J09-108J10-108

WAIT.LAMP-J02-007J23-023

WR-J01-094J02-044J03-044J05-044J06-044J07-044J08-044J09-044J10-044Jll-044J12-044

WR.DATA-J10-006J16-006

WR.PROT.O-J10-013J16-003

WRITE.GATE-J10-025J16-005

C-27

APPENDIX D

PINOUT CHARTS

CONTENTS

PINOUT FOR "POD CONTROLLER" BOARD. . D-l

PINOUT FOR "MONITOR" BOARD D-4

PINOUT FOR "ZDS/ASPIO" BOARD . D-7

PINOUT FOR "PROM PROGRAMMER" BOARD D-10

PINOUT FOR "CIB" BOARD . D-13

PINOUT FOR "PIB" BOARD D-16

PINOUT FOR "6OK MEMORY" BOARD D-19

PINOUT FOR "CPU" BOARD D-22

PINOUT FOR "FLOPPY CONTROLLER" BOARD D-25

PINOUT FOR "BREAKPOINT" BOARD . , D-28

PINOUT FOR "RTSM2" BOARD . . . . . . . . . . . . D-31

PINOUT FOR I/O CONNECTOR: LINE PRINTER (CIB/PIB) CABLE . . D-34

PINOUT FOR I/O CONNECTOR: FLOPPY DRIVE CABLE . . . . . . D-35

PINOUT FOR I/O CONNECTOR: TERMINAL CABLE D-36

PINOUT FOR I/O CONNECTOR: AUXILIARY SERIAL CABLE. . . . D-37

PINOUT FOR I/O CONNECTOR: LINE PRINTER (ZDS/ASPIO) CABLE . D-38

PINOUT FOR I/O CONNECTOR: PROLOG PROM PROGRAMMER CABLE. . D-39

PINOUT FOR I/O CONNECTOR: FRONT PANEL CABLE D-40

PINOUT FOR I/O CONNECTOR: POWER CABLE . D-41

PINOUT FOR POD CONTROLLER BOARD - 09-0055-01J01

PIN f SIGNAL NAME

001002003004005006007008009010Oil012013014015016017018019020021022023024025026027028029030031032033034035036037038039040041042043044045046

(+0 5V.PRINTED.DISTRIBUTION)(+0 5V.PRINTED.DISTRIBUTION)(+0 5V.PRINTED.DISTRIBUTION)BREAK.PENDING(SYS.DB.DISABLE-)SYSMEM.(SYSTEM.MEMORY)

D-l

PINOUT FOR POD CONTROLLER BOARD - 09-0055-01 (cont.)J01

PIN f SIGNAL NAME

047048049050051052053054055056057058059060061062063064065066067068069070071072073074075076077078079080081082083084085086087088089090091092

+05V.1.(PRINTED.DISTRIBUTION)+05V.2.(PRINTED.DISTRIBUTION)+05V.3.(PRINTED.DISTRIBUTION)GND.04.(PRINTED.DISTRIBUTION)GND.05.(PRINTED.DISTRIBUTION)GND.06.(PRINTED.DISTRIBUTION)MIS-BREAK-PHI.(SYSTEM.CLOCK)DlD7D4D5D3D6DOD2POWER.ON.CLR-BREAK.EMULATION-SA11SA10SA13SA14SA15Ml-SA12A09A08INT.DAISY.CHAIN.[#IEO].(IEO.OUT)SBUSAK-HALT-REFRESH-IORQ-RD-

D-2

PINOUT FOR POD CONTROLLER BOARD - 09-0055-01 (cont.)J01

PIN # SIGNAL NAME

093 MRQ-094 WR-095 HIS.IORQ-096 A05097 A02098 A01099 TRC.PHI.(EMULATOR.CLOCK)100 AOO101 A07102 INT.DAISY.CHAIN.[#IEI].(IEI.IN)103 FORCE.NOP104 A06105 +12V.3106 MONITOR107 INT-108 A03109 A04110 BUSRQ-111 WAIT-112 BUSAK-113 RUN114 A15115 A12116 A10117 A13118 A14119 All120 GND.13.(PRINTED.DISTRIBUTION)121 GND.14.(PRINTED.DISTRIBUTION)122 GND.15.(PRINTED.DISTRIBUTION)

D-3

PINOUT FOR MONITOR BOARD - 09-0093-01J02

PIN # SIGNAL NAME

001002003004005006007008009010Oil012013014015016017018019020021022023024025026027028029030031032033034035036037038039040041042043044045046

(+05V. PRINTED.(+0 5V. PRINTED.(+05V. PRINTED.«

H ALT o LAMP -MON I TOR. LAMP-WAIT. LAMP-USER. LAMP-A06A07RESTART. D-TY.HI•

•

•

AOOA01A02A03A04A05•

•

TRC.PHI. (CLOCK(GND)POWER. ON. CLR-HALT-

• Ml-MRQ-IORQ-•

•

•

9

•

RUN

DISTRIBUTION)DISTRIBUTION)DISTRIBUTION)

.FROM. EMULATOR)

FORCE . NOP . DELAYED•

•

•

•

•

•

WR-RD-SYS. RESET-

D-4

PINOUT FOR MONITOR BOARD - 09-0093-01 (cont.)J02

PIN # SIGNAL NAME

047048049050051052053054055056057058059060061062063064065066067068069070071072073074075076077078079080081082083084085086087088089090091092

D4D5*

(RESTART-)D6D7(USER. MEM. ENABLE-)DODlD3D2•

(+05V. PRINTED. DISTRIBUTION)( +0 5V. PRINTED . DISTRIBUTION)+05V.4. (PRINTEDGND.10. (PRINTEDGND.ll. (PRINTEDGND.12. (PRINTED•

STOR.SEL-DISK. DATA. PORT-DISK. CONTROL. B.DISK. CONTROL. A.BKPT.SEL-•

•

•

•

(UB.CONT-)MRD-USER.NCUSER. NO( SPARE. SEL-)(CTC.CARD.SEL-)•

MONTR. NCMONTR . NOTTY . DATA . OUTSERIAL. OUTRS232.DATA.OUTSERIAL. IN•

M1S-MlRQRS232. RETURNTTY. DAT A. IN

.DISTRIBUTION)

.DISTRIBUTION)

.DISTRIBUTION)

.DISTRIBUTION)

PORT-PORT-

D-5

PINOUT FOR MONITOR BOARD - 09-0093-01 (cont.)J02

PIN f SIGNAL NAME

093 RS232.DATA.IN•094095 +12V.3096 (IE*)097 TTY.IN.RETURN098 -12V.2099 TTY.OUT.RETURN100 (RFI)101 DATA.STB102 BREAK.EMULATION-103 BREAK.PENDING104105106 FORCE.NOP107108 WAIT-109110 MONITOR111 (MONITOR-)112113114115 (PHI.B.[CLOCK.BUFFERED])116 BREAK.STATUS117 SENSE.SW.l-118 SENSE.SW.2-119120 GND.07.(PRINTED.DISTRIBUTION)121 GND.08.(PRINTED.DISTRIBUTION)122 GND.09.(PRINTED.DISTRIBUTION)

D-6

PINOUT FOR ZDS/ASPIO BOARD - 09-0034-01J03

PIN # SIGNAL NAME

001 (+05V.PRINTED.DISTRIBUTION)002 (+05V.PRINTED.DISTRIBUTION)003 (+05V.PRINTED.DISTRIBUTION)004 TTXD005 TRXD006 TRTS007 TCTS008 TDSR009 A06010 A07Oil012013014015016 AGO017 A01018 A02019 A03020 A04021 A05022023024 PHI.(SYSTEM.CLOCK)025 TERM.BUSY026 SYS.RESET-027028 Ml-029030 IORQ-031032033034035036037038 CARRIER.DETECT039040041042043044 WR-045 RD-046

D-7

PINOUT FOR ZDS/ASPIO BOARD - 09-0034-01 (cont.)JOS

PIN f SIGNAL NAME

047048049050051052053054055056057058059060061062063064065066067068069070071072073074075076077078079080081082083084085086087088089090091092

D4D5SYNCTDTRD6D7•

DODlD3D2•

( +0 5V. PRINTED . DISTRIBUTION)(+0 5V. PRINTED. DISTRIBUTION)(+0 5V. PRINTED. DISTRIBUTION)GND.01. (PRINTEDGND.02. (PRINTEDGND.03. (PRINTEDDATA o 1 . LPDATA . 2 . LPDATA . 3 . LPDATA.4.LPDATA . 5 . LPDATA.6.LPDATA . 7 o LPDATA . 8 . LPDATA.STB-.LP•

SELECT. LPBUSY.LPPAPER. EMPTY. LPFAULT-. LP«

•

INPUT. PRIME-. LPACK-.LP•

•

•

•

m

INT. DAISY. CHAINR.I+12V.3ORIGINATE. MODELOCAL. MODE

.DISTRIBUTION)

.DISTRIBUTION)

.DISTRIBUTION)

. [#IEI] . (IEI)

D-8

PINOUT FOR ZDS/ASPIO BOARD - 09-0034-01 (cont.)JOS

PIN # SIGNAL NAME

093094095096097098099100101102103104105106107108109110111112113114115116117118119120121122

-12V.1•

INT-•

•

INT.DAISY.CHAIN.[IIEO].(IEO)

(GND.PRINTED.DISTRIBUTION)(GND.PRINTED.DISTRIBUTION)(GND.PRINTED.DISTRIBUTION)

D-9

PINOUT FOR PROM PROGRAMMER BOARD - 09-0031-02J03, JOS, J06, J07

PIN # SIGNAL NAME

001 (+05V.PRINTED.DISTRIBUTION)002 (+05V.PRINTED.DISTRIBUTION)003 (+05V.PRINTED.DISTRIBUTION)004005006007008009 A06010 A07Oil012013014015016 AGO017 A01018 A02019 A03020 A04021 A05022023024 PHI.(SYSTEM.CLOCK)025026027028 Ml-029030 IORQ-031032033034035036037038039040041042043044045 RD-046

D-10

PINOUT FOR PROM PROGRAMMER BOARD - 09-0031-02 (cont.)J03, JOS, J06, J07

PIN f SIGNAL NAME

047 D4048 D5049050051 D6052 D7053054 DO055 Dl056 D3057 D2058059 (+05V.PRINTED.DISTRIBUTION)060 (+05V.PRINTED.DISTRIBUTION)061 (+05V.PRINTED.DISTRIBUTION)062 (GND.PRINTED.DISTRIBUTION)063 (GND.PRINTED.DISTRIBUTION)064 (GND.PRINTED.DISTRIBUTION)065066067068069070071072073074075076077078079080081082083084085086087088 (IEI)089090091092

D-ll

PINOUT FOR PROM PROGRAMMER BOARD - 09-0031-02 (cont.)JOS, JOS, J06, J07

PIN # SIGNAL NAME

093094095096097098099100101102103104105106107108109 (INT-)110111112 (IEO)113114115116117118119120 (GND.PRINTED.DISTRIBUTION)121 (GND.PRINTED.DISTRIBUTION)122 (GND.PRINTED.DISTRIBUTION)

D-12

PINOUT FOR GIB BOARD - 09-0020-01JOS

PIN # SIGNAL NAME

001 (+05V.PRINTED.DISTRIBUTION)002 (+05V.PRINTED.DISTRIBUTION)003 (+05V.PRINTED.DISTRIBUTION)004005006 .007008009 A06010 A07Oil012013014 .015016 AGO017 A01018 A02019 A03020 A04021 A05022 .023024 PHI.(SYSTEM.CLOCK)025 .026 .027 .028 Ml-029 .030 IORQ-031 .032 .033034035 .036 .037038039040041042 .043 .044045 RD-046

D-13

PINOUT FOR GIB BOARD - 09-0020-01 (cont.)JOS

PIN # SIGNAL NAME

047048049050051052053054055056057058059060061062063064065066067068069070071072073074075076077078079080081082083084085086087088089090091092

D4D5e

.

D6D7SYS. RESET-DODID3D2.(+05V(+05V(+05V(GND.(GND.(GND.DATA.DATA.DATA.DATA.DATA.DATA.DATA.DATA.DATA..

. PRINTED . DISTRIBUTION)

. PRINTED . DI STRIBUTION)

. PRINTED . DISTRI BUTION)PRINTED . DI STRIBUTION)PRINTED. DISTRI BUTION)PRINTED. DISTRIBUTION)1.LP22.LP23.LP24.LP25.LP26.LP27.LP28.LP2STB-.LP2

SELECT.LP2BUSY.LP2PAPER. EMPTY. LP2FAULT-. LP2..INPUTACK-..,..*

.PRIME-.LP2LP2

INT. DAISY. CHAIN. [f IEI] . (IEI)...«

D-14

PINOUT FOR CIB BOARD - 09-0020-01 (cont.)JOS

PIN # SIGNAL NAME

09 3 DOO.PROLOG094 D01.PROLOG095 D02.PROLOG096 DO3.PROLOG097 D04.PROLOG098 DOS.PROLOG099 D06.PROLOG100101 D07.PROLOG102 MODE.PROLOG103 INTERLOCK.PROLOG104 DIO.PROLOG105 DI1.PROLOG106 DI2.PROLOG107108109 INT- '110 DI3.PROLOG '111 DI4.PROLOG '112 (IEO) '113 DI5.PROLOG '114 DI6.PROLOG115 DI7.PROLOG116 RESPONSE.PROLOG117 ADDRESS.PROLOG118 ERROR.PROLOG119 TRANSFER.PROLOG120 (GND.PRINTED.DISTRIBUTION)121 (GND.PRINTED.DISTRIBUTION)122 (GND.PRINTED.DISTRIBUTION)

D-15

PINOUT FOR PIB BOARD - 09-0020-02JOS

PIN f SIGNAL NAME

001002003004005006007008009010Oil012013014015016017018019020021022023024025026027028029030031032033034035036037038039040041042043044045046

(+05V. PRINTED(+05V. PRINTED(+05V. PRINTED«

e

o

«

•

A06A07•

•

•

•

•

AOOA01A02A03A04A05a

•

.DISTRIBUTION)

.DISTRIBUTION)

.DISTRIBUTION)

-

PHI. (SYSTEM. CLOCK)•

•

•

Ml-•

IORQ-*

•

•

•

•

•

*

•

•

•

•

•

•

•

RD-•

D-16

PINOUT FOR PIB BOARD - 09-0020-02 (cont.)JOS

PIN # SIGNAL NAME I

II

047048049050051052053054055056057058059060061062063064065066067068069070071072073074075076077078079080081082083084085086087088089090091092

D4D5•

*

D6D7SYS. RESET-DODlD3D2•

( +0 5V. PRINTED . DISTRI BUTION)(+05V. PRINTED. DISTRIBUTION)(+05V. PRINTED. DISTRIBUTION)(GND . PRINTED . DI STRI BUTION)(GND. PRINTED. DISTRI BUTION)(GND . PRINTED . DI STRIBUTION)DATA.1.LP2DATA . 2 . LP2DATA.3.LP2DATA . 4 . LP2DATA.5.LP2DATA . 6 . LP2DATA.7.LP2DATA . 8 . LP2DATA.STB-.LP2•

S ELECT. LP2BUSY.LP2PAPER. EMPTY. LP2FAULT- . LP2•

•

INPUT.PRIME-.LP2ACK-.LP2•

*

•

•

•

INT. DAISY. CHAIN. [#IEI] . (IEI)•

•

*

•

D-17

PINOUT FOR PIB BOARD - 09-0020-02 (cont.)JOS

PIN # SIGNAL NAME

093 DOO.PROLOG094 D01.PROLOG095 DO2.PROLOG096 D03.PROLOG09 7 DO4 «PROLOG098 DOS.PROLOG099 D06.PROLOG100 .101 D07.PROLOG102 MODE.PROLOG103 INTERLOCK.PROLOG104 DIO.PROLOG105 DI1.PROLOG106 DI2.PROLOG107108109 INT-110 DI3.PROLOG111 DI4.PROLOG112 (IEO)113 DI5.PROLOG114 DI6.PROLOG115 DI7.PROLOG116 RESPONSE.PROLOG117 ADORESS.PROLOG118 ERROR.PROLOG119 TRANSFER.PROLOG120 (GND.PRINTED.DISTRIBUTION)121 (GND.PRINTED.DISTRIBUTION)122 (GND.PRINTED.DISTRIBUTION)

D-18

PINOUT FOR 60K MEMORY BOARD - 09-0101-04JOS

PIN * SIGNAL NAME

001002003004005006007008009010Oil012013014015016017018019020021022023024025026027028029030031032033034035036037038039040041042043044045046

(+05V. PRINTED(+05V. PRINTED(+05V. PRINTED•

•

9

•

•

A06A07A08AllA10A09•

AOOA01A02A03A04A05•

•

•

REFRESH-•

•

•

MRQ-•

PS.3-PS.2-PS.l-PS.O-CD.3-CD.2-CD.l-CD.O-PG.15-A13+•

A12+•

WR-•

MRD-

. DISTRIBUTION)

.DISTRIBUTION)

.DISTRIBUTION)

D-19

PINOUT FOR 60K MEMORY BOARD - 09-0101-04 (cont.)JOS

PIN ft SIGNAL NAME

047048049050051052053054055056057058059060061062063064065066067068069070071072073074075076077078079080081082083084085086087088089090091092

D4D5•

o

D6D79

DODlD3D2«

(+05V. PRINT(4-05V. PRINT(+05V. PRINT(GND.PRINTE(GND.PRINTE(GND.PRINTE•

a

o

-05V. 1-05V. 1*

»

•

o

0

•

9

•

•

e

*

•

•

-05V. 2-05V. 2-05V. 2•

•

•

•

+12V.1+12V.1+12V.1

D-20

PINOUT FOR 60K MEMORY BOARD - 09-0101-04 (cont.)JOS

PIN | SIGNAL NAME

093094095096097098099100101102103104105106107108109110111112113114115116117118119120121122

+12V.2+12V.2+12V.2

(GND.PRINTED.DISTRIBUTION)(GND.PRINTED.DISTRIBUTION)(GND.PRINTED.DISTRIBUTION)

D-21

PINOUT FOR CPU BOARD - 09-0099-03J09

PIN # SIGNAL NAME

001002003004005006007008009010Oil012013014015016017018019020021022023024025026027028029030031032033034035036037038039040041042043044045046

(+05V. PRINTED. DISTRIBUTION)(+05V. PRINTED. DISTRIBUTION)(+05V. PRINTED. DISTRIBUTION)RCVR.OUT-( SERIAL. OUT)RCV.CLKRCV.CLK. (XMIT.CLK)SERIAL. INA06A07A08AllA10A09SERIAL. OUTAGOA01A02A03A04A05BUSAK-8 . PHI . ( 8X . SYSTEM .CLOCK)PHI. (SYSTEM. CLOCK)RE FRESH-POWER. ON. CLR-HALT-Ml-MRQ-IORQ-PS.3-PS.2-PS.l-PS.O-CD.3-CD.2-CD.l-CD.O-PG.15-. (MDIS-)A13A14A12A15WR-RD-TY.HI. (MONITOR)

D-22

PINOUT FOR CPU BOARD - 09-0099-03 (cont.)J09

PIN | SIGNAL NAME '

047 D4048 D5049 RESET.SW-050 (RESTART-)051 D6052 D7053 SYS.RESET-054 DO055 Dl056 D3057 D2058 EXT.PHI.(EXTERNAL.SYSTEM.CLOCK)059 (+05V.PRINTED.DISTRIBUTION)060 (+05V.PRINTED.DISTRIBUTION)061 (+05V.PRINTED.DISTRIBUTION)062 (GND.PRINTED.DISTRIBUTION)063 (GND.PRINTED.DISTRIBUTION)064 (GND.PRINTED.DISTRIBUTION)065066 A13 +067 SYSMEM.(SYSTEM.MEMORY)068 A12+069070071072073074075076077 RCVR.OUT-078 INDX.(EN-CLKO)079 INT.DAISY.CHAIN. [# IEO] . ( IE*)079080081082083 (GND)084 (GND)085 (GND)086 (GND)087 (GND)088089090 +12V.3091

D-23

PINOUT FOR CPU BOARD - 09-0099-03 (cont.)J09

PIN | SIGNAL NAME

092093094095096097098099 -5V.3100101 . t

102 |103 . |104105 . i106 FORCE.NOP107 BUSRQ- ,108 WAIT- i109 INT- i110 (NMI-)111112113114115 EXT.PHI.(S2.46MHZ)116117118119120 (GND.PRINTED.DISTRIBUTION)121 (GND.PRINTED.DISTRIBUTION)122 (GND.PRINTED.DISTRIBUTION)

D-24

PINOUT FOR FLOPPY CONTROLLER BOARD - 09-0004-01J10

PIN * SIGNAL NAME

001 (+05V.PRINTED.DISTRIBUTION) '002 (+05V.PRINTED.DISTRIBUTION) I003 (+05V.PRINTED.DISTRIBUTION)004005 . <006 WR.DATA-007 INDX008 (WR.PROT.1-)009 READ.DATA-010 (TRK.01-)011 TRK.OO-012 (DOOR.OPEN-)013 WR.PROT.O- '014 (INDX.1-) I015 INDX.O- '016 RDY- )017 (CURRENT-) i018 SEL.O- !019 (LOAD.HEAD.1-)020 (STEP.OUT.1-) •021 (WRITE.1-)022 (STEP.IN.1-)023 8.PHI. (8X.SYSTEM.CLOCK)024025 WRITE.GATE-026027 DIRECTION028 STEP-029030 IORQ-031032033034035036 . i037 . t038039 . I040041042043044 WR-045 RD-046

D-25

PINOUT FOR FLOPPY CONTROLLER BOARDJ10

PIN | SIGNAL NAME

09-0004-01(continued)

047048049050051052053054055056057058059060061062063064065066067068069070071072073074075076077078079080081082083084085086087088089090091092

D4D5v.D6D7SYS. RESET-DODlD3D2e

(+05V. PRINTED(+05V. PRINTED(+0 5V. PRINTED(GND. PRINTED.:(GND. PRINTED.(GND. PRINTED.«*e

e

e

,

,

e

»

.

.

»

.

.

.

.

RD.CLK-(GND)(GND)SEL.l-(GND).(LOAD. HEAD. 0-.....

D-26

PINOUT FOR FLOPPY CONTROLLER BOARDJ10

PIN f SIGNAL NAME

09-0004-01(continued)

093094095096097098099100101102103104105106107108109110111112113114115116117118119120121122

WAIT-

DISK. DATA. PORT-DISK. CONTROL . A.PORT-DISK . CONTROL.B.PORT-•

(GND.PRINTED.DISTRIBUTION)(GND.PRINTED.DISTRIBUTION)(GND.PRINTED.DISTRIBUTION)

D-27

PINOUT FOR BREAKPOINT BOARD - 09-0003-02Jll

PIN f SIGNAL NAME

001002003004005006007008009010Oil012013014015016017018019020021022023024025026027028029030031032033034035036037038039040041042043044045046

(+0 5V. PRINTED.(+05V. PRINTED.(+0 5V. PRINTED.•

•

•

•

•

A06A07A08SA11SA10A09BKPT.SEL-AOOA01A02A03A04A05•

•

«

•

POWER. ON. CLR-•

.

MRQ-HIS.IORQ-•

*

*

•

•

•

•

•

•

SA13SA14SA12SA15WR-RD-•

DISTRIBUTION)DISTRIBUTION)DISTRIBUTION)

D-28

PINOUT FOR BREAKPOINT BOARD - 09-0003-02 (cont.)Jll

PIN # SIGNAL NAME :

047048049050051052053054055056057058059060061062063064065066067068069070071072073074075076077078079080081082083084085086087088089090091092

D4D5*

•

D6D7•

DODlD3D2*

(+05V.PRINTE!(+05V. PRINTS:(+05V.PRINTE!(GND. PRINTED(GND. PRINTED(GND. PRINTED•

•

•

•

•

•

•

•

•

•

•

•

9

•

•

•

•

•

9

•

BREAK. STATUS•

•

•

•

M1RQ•

•

D-29

PINOUT FOR BREAKPOINT BOARD - 09-0003-02 (cont.)Jll

PIN # SIGNAL NAME

093094095096097098099100101102103104105106107108109110111112113114115116117118119120121122

BREAK-BREAK.SYNC

RUN•

»

DATA.STB

(GND.PRINTED.DISTRIBUTION)(GND.PRINTED.DISTRIBUTION)(GND.PRINTED.DISTRIBUTION)

D-30

PINOUT FOR RTSM2 BOARD - 09-0109-01J12

PIN f SIGNAL NAME

001 (+05V.PRINTED.DISTRIBUTION)002 (+05V.PRINTED.DISTRIBUTION)003 (+05V.PRINTED.DISTRIBUTION)004005006007008009 A06 i010 A07 i011 A08 I012 SA11013 SA10014 A09015016 AGO017 A01018 A02019 A03020 A04021 A05022 SBUSAK-023024025026027 HALT-028 Ml-029 MRQ-030 HIS.IORQ-031032033034035036037 FORCE.NOP.DELAYED038039040 SA13041 SA14042 SA12043 SA15044 WR-045 RD-046

D-31

PINOUT FOR RTSM2 BOARD - 09-0109-01 (cont.)J12

PIN f SIGNAL NAME '

047048049050051052053054055056057058059060061062063064065066067068069070071072073074075076077078079080081082083084085086087088089090091092

D4D5

RESTART.D-D6D7

DODlD3D2•

(+05V.PRINTED(+05V.PRINTED(+05V.PRINTED(GND.PRINTED.(GND.PRINTED.(GND.PRINTED.

STOR.SEL-

.DISTRIBUTION)

.DISTRIBUTION)

.DISTRIBUTION)DISTRIBUTION)DISTRIBUTION)DISTRIBUTION)

D-32

PINOUT FOR RTSM2 BOARD - 09-0109-01 (cont.)J12

PIN f SIGNAL NAME

093094095096097098099100101102103104105106107108109110111 RUN112113114 DATA.STB115116117118119120 (GND.PRINTED.DISTRIBUTION)121 (GND.PRINTED.DISTRIBUTION)122 (GND.PRINTED.DISTRIBUTION)

D-33

PINOOT FOR I/O CONNECTOR: LINE PRINTER (CIB/PIB) CABLEJ13

PIN f SIGNAL NAME

001002003004005006007008009010Oil012013014015016017018019020021022023024025

DATADATA

1.LP22.LP2

DATA.3.LP2DATA.4.LP2DATA.5.LP2DATA.6.LP2DATA.7.LP2DATA.8.LP2DATA.STB-.LP2INPUT.PRIME-.LP2ACK-.LP2FAULT-.LP2PAPER.EMPTY.LP2

GND.01GND.01GND.01

BUSY.LP2SELECT.LP2

D-34

PINOUT FOR I/O CONNECTOR: FLOPPY DRIVE CABLEJ16

PIN | SIGNAL NAME

001 RD.CLK-002 READ.DATA-003 WR.PROT.O-004 TRK.OO-005 WRITE.GATE-006 WR.DATA-007 STEP-008 DIRECTION009 SEL.l-010 SEL.O-011 RDY-012 INDX.O-013 -05V.1014 GND.02015 GND.02016 GND.02017 GND.03018 GND.03019 GND.03020 GND.04021 GND.04022 GND.04023 GND.05024 GND.05025 GND.05026 GND.05

D-35

PINOUT FOR I/O CONNECTOR: TERMINAL CABLEJ17

PIN # SIGNAL NAME

001002003004005006007008009010Oil012013014015016017018019020021022023024025

RS232.DATA.INRS232.DATA.OUTa>

TTY.IN.RETURNTTY.IN.RETURNRS232.RETURNTTY.IN.RETURN«

TTY.DATA.IN

TTY.DATA.OUTTTY.OUT.RETURN

TTY.IN.RETURN

D-36

PINOUT FOR I/O CONNECTOR: AUXILIARY SERIAL CABLEJ18

PIN f SIGNAL NAME

001002 TTXD003 TRXD004 TRTS005 TCTS00£ TDSR007 GND.06008 CARRIER.DETECT009 ORIGINATE.MODE010 LOCAL.MODEOil012013014015016017018019020 TDTR021022 R.I0230 24 SYNC025 TERM.BUSY

D-37

PINOUT FOR I/O CONNECTOR: LINE PRINTER (ZDS/ASPIO) CABLEJ19

PIN | SIGNAL NAME

001002003004005006007008009010Oil012013014015016017018019020021022023024025

DATADATA

,1.LP, 2.LP

DATA.3.LPDATA. 4. LPDATA.5.LPDATA.6.LPDATA.7.LPDATA. 8. LPDATA.STB-.LPINPUT.PRIME-.LPACK-.LPFAULT-.LPPAPER.EMPTY.LP

GND.06GND.06GND.06

BUSY.LPSELECT.LP

D-38

PINOUT FOR I/O CONNECTOR: PROLOG PROM PROGRAMMER CABLEJ20

PIN # SIGNAL NAME

001002 TRANSPER.PROLOG003 MODE.PROLOG004005 INTERLOCK.PROLOG006 DO6.PROLOG007 D02.PROLOG008 DO7.PROLOG009 DOS.PROLOG010 D04.PROLOG011 DOO.PROLOG012 DO1.PROLOG013 DOS.PROLOG014 ERROR.PROLOG015 ADORESS.PROLOG016 RESPONSE.PROLOG017 DI2.PROLOG018 DI3.PROLOG019 DIG.PROLOG020 DII.PROLOG021 DI6.PROLOG022 DI7.PROLOG023 DI4.PROLOG024 DI5.PROLOG025 GND.07

D-39

PINOUT FOR I/O CONNECTOR: FRONT PANEL CABLEJ23

PIN # SIGNAL NAME I

001002003004005006007008009010Oil012013014015016017018019020021022023024025026

GND.llGND.12BREAK. SYNC•

•

GND.13+05V.3+05V.2+05V.1+05V.4USER. NOUSER.NCGND.14SENSE. SW. 2-SENSE.SW.l-e

9

O

RESET. SW-HALT. LAMP-USER. LAMP-MONITOR. LAM!WAIT.LAMP-GND.15MONTR. NOMONTR. NC

D-40

PINOUT FOR I/O CONNECTOR: POWER CABLEJ24

PIN # SIGNAL NAME

001 -05V.1002 -05V.2003 (-05V.3)004 -12V.1005 -12V.2006 (-12V.3)007 +12V.1008 +12V.2009 +12V.3010 (+05V.PRINTED.DISTRIBUTION)011 (GND.PRINTED.DISTRIBUTION)

D-41

APPENDIX E

LOGIC DIAGRAMS

CONTENTS

LOGIC DIAGRAMS, USER POD CONTROLLER E-l

LOGIC DIAGRAMS, USER POD E-7

LOGIC DIAGRAMS, EMULATOR . E-14

LOGIC DIAGRAMS, Z-80A CPU EMULATOR (HYBRID) E-16

LOGIC DIAGRAMS, MONITOR.40 E-18

LOGIC DIAGRAMS, MEMORY 25 E-22

LOGIC DIAGRAMS, CPU.2 (09-0099-01) E-26

LOGIC DIAGRAMS, CPU-3 (09-0099-03) E-36

LOGIC DIAGRAMS, FLOPPY CONTROLLER E-41

LOGIC DIAGRAMS, BREAKPOINT . . . . . E-59

LOGIC DIAGRAMS, RTSM.2 . . . . . . . . . . . . E-56

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DOCUMENT CHANGE NOTICE

DATE: 04-03-80

DCN NUMBER: E3-3018-03, Rev. C

PUBLICATION NUMBER: 03-3018-03

TITLE: ZDS-1/40 Hardware Reference Manual

PREVIOUS DCNs BY NUMBER: E3-3018-03, Rev.AE3-3018-03, Rev.B

EFFECTIVE DATE: 04-03-80

This Document Change Notice provides replacementpages for the publication specified above. Thesereplacement pages contain changes to the technicalcontents of the manual specified above, and willremain in effect unless specifically amended orsuperseded by another DCN, or merged into themanual by a publication revision. The followingpages are to be treated as described.

Replace Logic Diagram Set DZ-0056-02, Rev. Dwith DZ-0056-03, Rev. A.

Changes to text are indicated by a vertical linein the right margin, opposite the changed textportion.

NOTE: Please file this DCN at the back of manualto provide a record of changes.

CF-1017-01A

1

DOCUMENT CHANGE NOTICE

Zilog

DATE: 2/1/80

DCN NUMBER: E3-3018-03, Rev. B

PUBLICATION NUMBER: 03-3018-03

TITLE: ZDS-1/40 Hardware Reference Manual

PREVIOUS DCNs BY NUMBER: E3-3018-03, Rev. A

EFFECTIVE DATE: 2/1/80

This Document Change Notice provides change pagesfor the publication specified above. These changepages contain changes to the technical contents ofthe manual specified above, and will remain ineffect unless specifically amended or supersededby another DCN, or merged into the manual by apublication revision. The following pages are tobe treated as described.

Replace Logic Diagram Set DZ-0099-04, Rev. Awith DZ-0099-04, Rev. B

Changes to text are indicated by a vertical linein the right margin, opposite the changed textportion.

NOTE: Please file this DCN at the back of themanual to provide a record of changes.

CF-1017-01 A

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DOCUMENT CHANGE NOTICE

ZilogDATE: 12-07-79

DCN NUMBER: E3-3018-03, Rev. A

PUBLICATION NUMBER: 03-3018-03

TITLE: ZDS-1/40 HARDWARE REFERENCE MANUAL

PREVIOUS DCN's BY NUMBER: None

EFFECTIVE DATE: 12-07-79

This Document Change Notice provides chcinge pagesfor the publication specified above. These changepages contain changes to the technical contents ofthe manual specified above, and will remain ineffect unless specifically amended or supersededby another DCN, or merged into the manuail by apublication revision. The following pages are tobe treated as described.

Replace page D-22 in manual with change pageattached.

Replace CONTENTS page of APPENDIX E with changepage attached.

Replace page E-33 in manual with change pageattached.

Replace Logic Diagram Set DZ-0099-03, Rev. Awith DZ-0099-04, Rev. A

Changes to text are indicated by a vertical linein the right margin, opposite the changed textportion.

NOTE: Please file this DCN at the back of themanual to provide a record of changes.

CF-1017-01A

PINOUT FOR 60K MEMORY BOARD - 09-0101-04 (cont.)JOS

PIN # SIGNAL NAME

093 +12V.2094 +12V.2095 +12V.2096097098099100101102103104105106107108109110111112113114115116117118119120 (GND.PRINTED.DISTRIBUTION)121 (GND.PRINTED.DISTRIBUTION)122 (GND.PRINTED.DISTRIBUTION)

D-21

PINOUT FOR CPU BOARD - 09-0099-01 or 09-0099-04 IJ09

PIN t SIGNAL NAME —'

001002003004005006007008009010Oil012013014015016017018019020021022023024025026027028029030031032033034035036037038039040041042043044045046

(+0 5V. PRINTED.(+05V. PRINTED.(+0 5V. PRINTED.RCVR.OUT-( SERIAL. OUT)RCV.CLKRCV.CLK. (XMIT.SERIAL. INA06A07A08AllA10A09SERIAL. OUTAOOA01A02A03A04A05BUSAK-

DISTRIBUTION)DISTRIBUTION)DISTRIBUTION)

CLK)

8 . PHI . ( 8X . SYSTEM . CLOCK)PHI. (SYSTEM. CLOCK)REFRESH-POWER. ON. CLR-HALT-Ml-MRQ-IORQ-PS.3-PS.2-PS.l-PS.O-CD.3-CD.2-CD.l-CD.O-PG.15-. (MDIS-)A13A14A12A15WR-RD-TY.HI. (MONITOR)

E3-3018-03, Rev. A D-22 12/03/79

APPENDIX E

LOGIC DIAGRAMS

CONTENTS

LOGIC-

LOG 1C

LOGIC

LOGIC

LOGIC

LOGIC

LOGIC

LOGIC

LOGIC

LOGIC

LOGIC

DIAGRAMS,

DIAGRAMS ,

DIAGRAMS ,

DIAGRAMS ,

DIAGRAMS ,

DIAGRAMS ,

DIAGRAMS ,

DIAGRAMS ,

DIAGRAMS ,

DIAGRAMS ,

DIAGRAMS ,

USER POD CONTROLLER .

USER POD

EMULATOR

Z-80A CPU EMULATOR (HYBRID) .

MONITOR. 40

MEMORY

CPU. 2

CPU-3

FLOPPY

25

(09-0099-01)

(09-0099-04)

CONTROLLER

BREAKPOINT

RTSM . 2

. . . . E-l

. . . . E-7

. . . . E-15

. E-17

. . . . E-19

. . . . E-25

. . . . E-31

. . . . E-33

. . . . E-39

. . . . E-49

. . . . E-57

E3-3018-03, Rev. A 12/03/79

LOGIC DIAGRAMS, CPU-3

(09-0099-04) "j

E3-3018-03, Rev. A E-33 12/03/79

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