October 2010 FDD86102LZ - docs-apac.rs- · PDF fileVery low Qg and Qgd compared to competing...
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FDD
86102LZ N-C
hannel PowerTrench ® M
OSFET
©2010 Fairchild Semiconductor CorporationFDD86102LZ Rev.C
www.fairchildsemi.com1
October 2010FDD86102LZ N-Channel PowerTrench® MOSFET
100 V, 35 A, 22.5 mΩFeatures
Max rDS(on) = 22.5 mΩ at VGS = 10 V, ID = 8 A
Max rDS(on) = 31 mΩ at VGS = 4.5 V, ID = 7 A
HBM ESD protection level > 6 kV typical (Note 4)
Very low Qg and Qgd compared to competing trench technologies
Fast switching speed
100% UIL tested
RoHS Compliant
General DescriptionThis N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that has been especially tailored to minimize the on-state resistance and switching loss. G-S zener has been added to enhance ESD voltage level.
ApplicationsDC - DC Conversion
Inverter
Synchronous Rectifier
G
S
D
TO-252D-PAK(TO-252)
D
S
G
MOSFET Maximum Ratings TC = 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings UnitsVDS Drain to Source Voltage 100 VVGS Gate to Source Voltage ±20 V
ID
Drain Current -Continuous (Package limited) TC = 25 °C 42
A -Continuous (Silicon limited) TC = 25 °C 35 -Continuous TA = 25 °C (Note 1a) 8 -Pulsed 40
EAS Single Pulse Avalanche Energy (Note 3) 84 mJ
PDPower Dissipation TC = 25 °C 54
WPower Dissipation TA = 25 °C (Note 1a) 3.1
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJC Thermal Resistance, Junction to Case 2.3°C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 40
Device Marking Device Package Reel Size Tape Width QuantityFDD86102LZ FDD86102LZ D-PAK(TO-252) 13 ’’ 12 mm 2500 units
FDD
86102LZ N-C
hannel PowerTrench ® M
OSFET
©2010 Fairchild Semiconductor CorporationFDD86102LZ Rev.C
www.fairchildsemi.com2
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characteristics
On Characteristics (Note 2)
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 VΔBVDSS ΔTJ
Breakdown Voltage TemperatureCoefficient ID = 250 μA, referenced to 25 °C 69 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μAIGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±10 μA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 1.0 1.5 3.0 V ΔVGS(th) ΔTJ
Gate to Source Threshold VoltageTemperature Coefficient ID = 250 μA, referenced to 25 °C -6 mV/°C
rDS(on) Static Drain to Source On ResistanceVGS = 10 V, ID = 8 A 17.8 22.5
mΩVGS = 4.5 V, ID = 7 A 23.2 31VGS = 10 V, ID = 8 A, TJ = 125 °C 31.1 40
gFS Forward Transconductance VDS = 5 V, ID = 8 A 31 S
Ciss Input CapacitanceVDS = 50 V, VGS = 0 V,f = 1 MHz
1157 1540 pFCoss Output Capacitance 181 245 pFCrss Reverse Transfer Capacitance 7.7 15 pFRg Gate Resistance 0.6 Ω
td(on) Turn-On Delay TimeVDD = 50 V, ID = 8 A,VGS = 10 V, RGEN = 6 Ω
6.6 14 nstr Rise Time 2.3 10 nstd(off) Turn-Off Delay Time 20 32 nstf Fall Time 2.3 10 nsQg Total Gate Charge VGS = 0 V to 10 V
VDD = 50 V, ID = 8 A
18 26 nCQg Total Gate Charge VGS = 0 V to 4.5 V 8.7 13 nCQgs Gate to Source Gate Charge 2.7 nCQgd Gate to Drain “Miller” Charge 2.4 nC
VSD Source to Drain Diode Forward VoltageVGS = 0 V, IS = 8 A (Note 2) 0.82 1.3
VVGS = 0 V, IS = 2.6 A (Note 2) 0.75 1.2
trr Reverse Recovery TimeIF = 8 A, di/dt = 100 A/μs
43 70 nsQrr Reverse Recovery Charge 43 70 nC
Notes:1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting TJ = 25°C, L = 1 mH, IAS = 13 A, VDD = 90 V, VGS = 10 V.
4. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
a. 40 °C/W when mounted on a 1 in2 pad of 2 oz copper.
b. 96 °C/W when mounted on a minimum pad of 2 oz copper.
FDD
86102LZ N-C
hannel PowerTrench ® M
OSFET
©20FDD
Typical Characteristics TJ = 25 °C unless otherwise noted
Figure 1.
0 1 2 3 4 50
10
20
30
40
VGS = 3.5 V VGS = 3 V
VGS = 10 V
PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX
VGS = 2.5 V
VGS = 4.5 V
I D, D
RA
IN C
UR
REN
T (A
)
VDS, DRAIN TO SOURCE VOLTAGE (V)
On-Region Characteristics Figure 2.
0 10 20 30 400
1
2
3
4
5VGS = 2.5 V
PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX
NO
RM
ALI
ZED
DR
AIN
TO
SO
UR
CE
ON
-RES
ISTA
NC
E
ID, DRAIN CURRENT (A)
VGS = 4.5 V
VGS = 3.5 V
VGS = 3 V
VGS = 10 V
Normalized On-Resistance vs Drain Current and Gate Voltage
Figure 3. Normalized On- Resistance
-75 -50 -25 0 25 50 75 100 125 1500.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ID = 8 AVGS = 10 V
NO
RM
ALI
ZED
DR
AIN
TO
SO
UR
CE
ON
-RES
ISTA
NC
E
TJ, JUNCTION TEMPERATURE (oC)
vs Junction TemperatureFigure 4.
2 4 6 8 100
30
60
90
120
TJ = 125 oC
ID = 8 A
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
r DS(
on),
DR
AIN
TO
SO
UR
CE
ON
-RES
ISTA
NC
E (m
Ω) PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
On-Resistance vs Gate to Source Voltage
Figure 5. Transfer Characteristics
0 1 2 3 4 50
10
20
30
40
TJ = 25 oCTJ = 150 oC
VDS = 5 V
PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX
TJ = -55 oC
I D, D
RA
IN C
UR
REN
T (A
)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.0 0.2 0.4 0.6 0.8 1.0 1.20.001
0.01
0.1
1
10
50
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
I S, R
EVER
SE D
RA
IN C
UR
REN
T (A
)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode Forward Voltage vs Source Current
10 Fairchild Semiconductor Corporation86102LZ Rev.C
www.fairchildsemi.com3
FDD
86102LZ N-C
hannel PowerTrench ® M
OSFET
©20FDD
Figure 7.
0 5 10 15 200
2
4
6
8
10ID = 8 A
VDD = 50 V
VDD = 25 V
V GS,
GA
TE T
O S
OU
RC
E VO
LTA
GE
(V)
Qg, GATE CHARGE (nC)
VDD = 75 V
Gate Charge Characteristics Figure 8.
0.1 1 10 1001
10
100
10002000
f = 1 MHzVGS = 0 V
CA
PAC
ITA
NC
E (p
F)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Capacitance vs Drain to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 301
10
40
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
I AS,
AVA
LAN
CH
E C
UR
REN
T (A
)
Unclamped Inductive Switching Capability
Figure 10.
0 5 10 15 20 25 30 3510-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
VGS = 0 V
TJ = 125 oC
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
I g, G
ATE
LEA
KA
GE
CU
RR
ENT
(A)
Gate Leakage Current vs Gate to Source Voltage
Figure 11.
25 50 75 100 125 1500
10
20
30
40
VGS = 4.5 V
RθJC = 2.3 oC/W
VGS = 10 V
I D, D
RA
IN C
UR
REN
T (A
)
TC, CASE TEMPERATURE (oC)
Maximum Continuous Drain Current vs Case Temperature
Figure 12.
0.1 1 10 100 3000.050.1
1
10
100
100us
10 ms
DC
1 ms
I D, D
RA
IN C
UR
REN
T (A
)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS LIMITED BY rDS(on)
SINGLE PULSETJ = MAX RATEDRθJC = 2.3 oC/WTC = 25 oC
Forward BiasSafe Operating Area
Typical Characteristics TJ = 25 °C unless otherwise noted
10 Fairchild Semiconductor Corporation86102LZ Rev.C
www.fairchildsemi.com4
FDD
86102LZ N-C
hannel PowerTrench ® M
OSFET
©20FDD
Figure 13.
10-5 10-4 10-3 10-2 10-1 110
100
1000
10000P (P
K), P
EAK
TR
AN
SIEN
T PO
WER
(W)
SINGLE PULSERθJC = 2.3 oC/W
TC = 25 oC
t, PULSE WIDTH (sec)
Single Pulse Maximum Power Dissipation
Figure 14. Junction-to-Case Transient Thermal Response Curve
10-5 10-4 10-3 10-2 10-1 10.005
0.01
0.1
1
SINGLE PULSERθJC = 2.3 oC/W
DUTY CYCLE-DESCENDING ORDER
NO
RM
ALI
ZED
TH
ERM
AL
IMPE
DA
NC
E, Z
θJC
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5 0.2 0.1 0.05 0.02 0.01
2
PDM
t1t2
NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x ZθJC x RθJc + TC
Typical Characteristics TJ = 25 °C unless otherwise noted
10 Fairchild Semiconductor Corporation86102LZ Rev.C
www.fairchildsemi.com5
©2010 Fairchild Semiconductor CorporationFDD86102LZ Rev.C
www.fairchildsemi.com6
FDD
86102LZ N-C
hannel PowerTrench ® M
OSFET
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*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONSDefinition of Terms
AccuPower™Auto-SPM™Build it Now™CorePLUS™CorePOWER™CROSSVOLT™CTL™Current Transfer Logic™DEUXPEED®
Dual Cool™EcoSPARK®
EfficentMax™ESBC™
Fairchild®
Fairchild Semiconductor®FACT Quiet Series™FACT®
FAST®
FastvCore™FETBench™FlashWriter® *FPS™
F-PFS™FRFET®
Global Power ResourceSM
Green FPS™Green FPS™ e-Series™Gmax™GTO™IntelliMAX™ISOPLANAR™MegaBuck™MICROCOUPLER™MicroFET™MicroPak™MicroPak2™MillerDrive™MotionMax™Motion-SPM™OptiHiT™OPTOLOGIC®
OPTOPLANAR®®
PDP SPM™
Power-SPM™PowerTrench®
PowerXS™Programmable Active Droop™QFET®
QS™Quiet Series™RapidConfigure™
Saving our world, 1mW/W/kW at a time™SignalWise™SmartMax™SMART START™SPM®
STEALTH™SuperFET™SuperSOT™-3SuperSOT™-6SuperSOT™-8SupreMOS™SyncFET™Sync-Lock™
®*
The Power Franchise®
®
TinyBoost™TinyBuck™TinyCalc™TinyLogic®
TINYOPTO™TinyPower™TinyPWM™TinyWire™TriFault Detect™TRUECURRENT™*μSerDes™
UHC®
Ultra FRFET™UniFET™VCX™VisualMax™XS™
®
tm
tm
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Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
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No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
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Rev. I48
™