October 10, 2000 1

October 10, 2000 2

USB 2.0 Peripheral Design Options

USB 2.0 Peripheral Design Options

Dave PodsiadloDave Podsiadlo

Product Marketing ManagerProduct Marketing ManagerCypress SemiconductorCypress Semiconductor

dpz@cypress.comdpz@cypress.com

Single-Chip, Internal MicrocontrollerSingle-Chip, Internal Microcontroller

October 10, 2000 3

Peripheral Design OptionsPeripheral Design Options

PHY-PLD/ASICPHY-PLD/ASIC

Multi-chip: function + external CPUMulti-chip: function + external CPU

Single-chip, internal microcontrollerSingle-chip, internal microcontroller

ASICASIC

Inte

grat

ion

Inte

grat

ion

October 10, 2000 4

External External PHYPHY

Multi-Chip:Multi-Chip:

Function +Function +

External CPUExternal CPU

Single-chip, Single-chip, Internal Internal

uControlleruController

ASICASIC

Design effortDesign effort MEDIUMMEDIUM MEDIUMMEDIUM LOWLOW HIGHHIGH

Time to marketTime to market LONGLONG MEDIUMMEDIUM SHORTSHORT LONGLONGNRE costsNRE costs LOW/HILOW/HI MEDIUMMEDIUM LOWLOW HIGHHIGHParts costParts cost MEDIUMMEDIUM MEDIUMMEDIUM MEDIUMMEDIUM LOWLOW

Pin countPin count HIGHHIGH MEDIUMMEDIUM LOWLOW LOWLOW

Design Tradeoffs Design Tradeoffs

Quick to marketQuick to marketLowest development costLowest development cost

Modest priceModest price

Quick to marketQuick to marketLowest development costLowest development cost

Modest priceModest price

October 10, 2000 5

Single-Chip IssuesSingle-Chip Issues

1.1. How fast is it? How fast is it?Can it keep up with the new 480 Mbit/sec rate?Can it keep up with the new 480 Mbit/sec rate?Can it get data on and off chip quickly enough?Can it get data on and off chip quickly enough?

2.2. How easy is development? How easy is development?How much of my USB 1.1 experience is usable?How much of my USB 1.1 experience is usable?

3.3. How easily does it connect to my system? How easily does it connect to my system?How much glue logic do I need?How much glue logic do I need?Does it introduce any performance bottlenecks?Does it introduce any performance bottlenecks?

4.4. How cost effective is it? How cost effective is it?What can I replace that’s already in my system?What can I replace that’s already in my system?

October 10, 2000 6

1. How Fast Is It?1. How Fast Is It?

An internal microprocessor should not touchAn internal microprocessor should not touch480 Mbit/sec data480 Mbit/sec data– Instead, optimize the channel that moves data onInstead, optimize the channel that moves data on

and off chip using specialized logicand off chip using specialized logic DMADMA OtherOther

– Use the CPU for USB housekeeping, I/O, etc.Use the CPU for USB housekeeping, I/O, etc. Fast data transfers require fast control logicFast data transfers require fast control logic

– Adaptable to many interfacesAdaptable to many interfaces ATA, EPP, etc.ATA, EPP, etc.

October 10, 2000 7

Speed Example:ATA Hard DriveSpeed Example:ATA Hard Drive

Internal data transfer rate is 40 Mbytes/sec.Internal data transfer rate is 40 Mbytes/sec. Avg. sustained transfer rate is 15 Mbytes/sec.Avg. sustained transfer rate is 15 Mbytes/sec. Channel rate is 66.6 Mbytes/sec.Channel rate is 66.6 Mbytes/sec.

– The closer the interface gets to this number, the better The closer the interface gets to this number, the better it services the drive’s internal bufferit services the drive’s internal buffer Higher overall performanceHigher overall performance

USB 2.0USB 2.0– 13 Bulk packets per microframe max13 Bulk packets per microframe max– 13 * 512 * 8 * 1000 = 53,248,000 bytes/sec.13 * 512 * 8 * 1000 = 53,248,000 bytes/sec.

7200 RPM, 512 Kbyte Internal Buffer7200 RPM, 512 Kbyte Internal Buffer

October 10, 2000 8

ATA Hard Drive Data RatesATA Hard Drive Data Rates

USBHost

BufferBuffer

HeadHead

4040

Disk DriveDisk Drive

USB 2.0Controller

USBUSB 606020-5020-50 IFIF

15 Sustained

15 Sustained

October 10, 2000 9

2. How Easy Is Development?2. How Easy Is Development?

Continuity with USB 1.1 is the keyContinuity with USB 1.1 is the key– Everything you know about 1.1 plus a little extraEverything you know about 1.1 plus a little extra– (Thank you, USB 2.0 architects)(Thank you, USB 2.0 architects)– Differences are real improvementsDifferences are real improvements

PING-NYET PING-NYET Minimize changesMinimize changes

– Use the same microprocessorUse the same microprocessor– Hide the protocol enhancements in hardwareHide the protocol enhancements in hardware

Chirp, PING-NYET, DATA2/1/0, etc.Chirp, PING-NYET, DATA2/1/0, etc.– Use the same interface logic Use the same interface logic – Use the same development toolsUse the same development tools

October 10, 2000 10

Packet Size ComparisonPacket Size Comparison

ControlControl

BulkBulk

InterruptInterrupt

IsochronousIsochronous

8, 16, 32, 648, 16, 32, 64

8, 16, 32, 648, 16, 32, 64

1-641-64

10231023

6464

512512

10241024

10241024

USB 1.1USB 1.1 USB 2.0USB 2.0

Transfer typeTransfer type Packet sizePacket size

October 10, 2000 11

An Efficient Design PlanAn Efficient Design Plan

Write ‘1.1’ code using the new endpoint structureWrite ‘1.1’ code using the new endpoint structure Debug & test using existing tools & OSDebug & test using existing tools & OS Later, run at 2.0 speeds with onlyLater, run at 2.0 speeds with only

slight modificationslight modification– Configure larger endpoint buffers to take Configure larger endpoint buffers to take

advantage of USB 2.0 high bandwidthadvantage of USB 2.0 high bandwidth

October 10, 2000 12

3. How Well Does ItConnect to My System?3. How Well Does ItConnect to My System?

How much ‘glue’ logic is required?How much ‘glue’ logic is required? How does it handle two clock domains?How does it handle two clock domains?

– USB & interface logicUSB & interface logic– May require a FIFOMay require a FIFO

Data pathsData paths– 8 bit8 bit– 16 bit16 bit

No speed bottlenecks allowedNo speed bottlenecks allowed

October 10, 2000 13

4. How Cost Effective Is It?4. How Cost Effective Is It?

Look for a family of partsLook for a family of parts– ‘‘Economy’ through ‘Full function’Economy’ through ‘Full function’– Code compatibility up and down the familyCode compatibility up and down the family

Consider the full system costConsider the full system cost– The internal microprocessor may replace oneThe internal microprocessor may replace one

already in your systemalready in your system– Interface as peripheral, use internal processorInterface as peripheral, use internal processor

only as a USB housekeeperonly as a USB housekeeper– USB 2.0 changes the cost equationUSB 2.0 changes the cost equation

Internal processor can be a tiny percentage of the chip areaInternal processor can be a tiny percentage of the chip area

October 10, 2000 14

16

Single-Chip ExampleSingle-Chip Example

Low level protocolLow level protocolCRC, PID encode-CRC, PID encode-

decode, chirp decode, chirp Deliver WORDS Deliver WORDS

TokenTokenProcessorProcessorEP0, Ping,EP0, Ping, ACK/NAK/ ACK/NAK/

STALL/STALL/NYETNYET

"Chapter 9""Chapter 9"

Outside InterfaceOutside Interface

High speed logicHigh speed logicclock extractionclock extraction

serialize/serialize/ deserialize deserialize

bit stuffbit stuffNRZINRZI

SYNC,SYNC,EOPEOP

16

16 EndpointsEndpointsEndpoint FIFOSEndpoint FIFOS& control logic& control logic

16

CPUCPU48 MHz48 MHz 8051 8051

Program & Program & Data RAMData RAM

Dow

nloa

d C

ode

Dow

nloa

d C

ode

Dat

a C

han

nel

GPIF

October 10, 2000 15

USB Speed: LargeEndpoint BuffersUSB Speed: LargeEndpoint Buffers

And “Zero Time” DMAAnd “Zero Time” DMA

512512

512512

512512

512512

EP2

EP4

512512

512512

512512

512512

EP2

512512

512512

512512

512512EP6

EP8

512512

512512

512512

512512

EP6

512512

512512

512512

512512

EP2

512512

512512EP6

10241024

10241024

EP2

10241024

10241024

EP6

10241024

10241024

EP2

10241024

10241024

10241024

EP2

10241024

10241024

512512

512512EP8

EP0 IN&OUTEP0 IN&OUTEP1 INEP1 IN

EP1 OUTEP1 OUT 646464646464

646464646464

646464646464

646464646464

646464646464

646464646464

512512

512512EP8

October 10, 2000 16

Interface Speed: GPIF Interface Speed: GPIF

N1N1 N2N2 N3N3 N4N4 N5N5

Cycles /Cycles / branchbranch

Data BusData Bus

CTL1 OECTL1 OE

CTL1 ValCTL1 Val

11 2/32/3 22 11

drivedrive

11 11

11 1111

Decision Point?Decision Point? 00 11 00 00

1111zz1100

0000drivedrivezzzz

00

WR StrobeWR Strobe

data outdata out

readyready

address outaddress out

RDYRDY

WRWR

20.8 nsec Edge Resolution20.8 nsec Edge Resolution

October 10, 2000 17

Design Ease: Same ToolsDesign Ease: Same Tools

October 10, 2000 18

Value: Three PackagesValue: Three Packages

100100TQFPTQFP

14x20x1.414x20x1.4mmmm

100100TQFPTQFP

14x20x1.414x20x1.4mmmm

5656SSOPSSOP

8x18x2.38x18x2.3mmmm

5656SSOPSSOP

8x18x2.38x18x2.3mmmm

Price ChampPrice ChampPrice ChampPrice Champ

128128TQFPTQFP

14x20x1.414x20x1.4mmmm

128128TQFPTQFP

14x20x1.414x20x1.4mmmm

October 10, 2000 19

Summary: Challengesand SolutionsSummary: Challengesand Solutions

1.1. Speed Speed– USB: Large, multiple-buffered endpointsUSB: Large, multiple-buffered endpoints– Interface: fat, dedicated data pipe & fast control logicInterface: fat, dedicated data pipe & fast control logic

2.2. Development ease Development ease– Leverage USB 1.1 experience using same toolsLeverage USB 1.1 experience using same tools

3.3. System integration System integration– CPU, system glue logic insideCPU, system glue logic inside

4.4. Cost effective Cost effective– Internal microcontrollerInternal microcontroller– Planned familyPlanned family