NVIDIA Tesla P100 Graphics Processing Unit (GPU) with HBM2 - … · 2017. 10. 19. · NVIDIA Tesla...

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COMPLETE TEARDOWN WITH: Detailed photos and cross-sections Precise measurements Material analysis Manufacturing process flow Supply chain evaluation Manufacturing cost analysis Estimated sales price NVIDIA Tesla P100 Graphics Processing Unit (GPU) with HBM2 Title: NVIDIA Tesla P100 GPU with HBM2 Pages: 130 Date: October 2017 Format: PDF & Excel file Price: Full report: EUR 3,490 TSMC CoWoS – Samsung HBM2 – 2.5D and 3D Packaging HBM2 greatly increases memory capacity and bandwidth over first generation HBM1 technology. HBM1 was limited to 1GB of memory per stack of four dynamic random access memory (DRAM) die with maximum capacity of 256MB and 125GB/sec of bandwidth. That compares to 8GB of memory per stack of eight stacked DRAM die with maximum capacity of 1GB and 180GB/sec bandwidth for HBM2. The single 55mm x 55mm 12-layer ball grid array (BGA) package of the NVIDIA Tesla P100 includes more than 3,500 mm² of silicon area. Two industry leaders, TSMC and Samsung, had to come together to deliver this much silicon area in a package. TSMC is the main provider for the Tesla P100. Using its 2.5D CoWoS platform, it manufactures the GP100 GPU die, featuring a 16nm FinFET process and 15.3 billion transistors. It also produces a large silicon interposer on top of which the GPU is assembled at the wafer-level with its four HBM2 stacks. Samsung provides the HBM2 stacks. A 3D assembly process yields HBM2 stacks composed of four 1GB DRAM memory dies and one buffer die, connected with via-middle through-silicon vias and micro-bumps. The report includes a complete physical analysis of the packaging process, with details on all technical choices regarding process, equipment and materials. Also, the complete manufacturing supply chain is described and manufacturing costs are calculated. The report also compares the Tesla P100 with AMD’s Fury X, which uses HBM1 and 2.5D assembly, to explain the interest in evolution through the HBM2 and CoWoS 2.5D platforms. Finally, it describes NVIDIA’s key module design and related process choices. Targeted for High Performance Computing (HPC) and deep learning, the NVIDIA Tesla P100 is the world's first artificial intelligence supercomputing data center GPU. It uses various leading edge technologies, including 3D stacked memory with 2.5D integration on a silicon interposer in a Chip-on- Wafer-on-Substrate (CoWoS) process. Improving memory performance threefold over the NVIDIA Maxwell architecture, the Tesla P100 accelerators are equipped with 12GB or 16GB of second generation high bandwidth memory (HBM2).

Transcript of NVIDIA Tesla P100 Graphics Processing Unit (GPU) with HBM2 - … · 2017. 10. 19. · NVIDIA Tesla...

Page 1: NVIDIA Tesla P100 Graphics Processing Unit (GPU) with HBM2 - … · 2017. 10. 19. · NVIDIA Tesla P100 Graphics Processing Unit (GPU) with HBM2 Title: NVIDIA Tesla P100 GPU with

COMPLETE TEARDOWN

WITH:

• Detailed photos and cross-sections

• Precise measurements

• Material analysis

• Manufacturing process flow

• Supply chain evaluation

• Manufacturing cost analysis

• Estimated sales price

NVIDIA Tesla P100 Graphics ProcessingUnit (GPU) with HBM2

Title: NVIDIA Tesla P100 GPU with HBM2

Pages: 130

Date: October 2017

Format: PDF & Excel file

Price: Full report: EUR 3,490

TSMC CoWoS – Samsung HBM2 – 2.5D and 3D Packaging

HBM2 greatly increases memory capacity and bandwidth over first generation HBM1technology. HBM1 was limited to 1GB of memory per stack of four dynamic random accessmemory (DRAM) die with maximum capacity of 256MB and 125GB/sec of bandwidth. Thatcompares to 8GB of memory per stack of eight stacked DRAM die with maximum capacity of1GB and 180GB/sec bandwidth for HBM2.

The single 55mm x 55mm 12-layer ball grid array (BGA) package of the NVIDIA Tesla P100includes more than 3,500 mm² of silicon area. Two industry leaders, TSMC and Samsung, hadto come together to deliver this much silicon area in a package.

TSMC is the main provider for the Tesla P100. Using its 2.5D CoWoS platform, itmanufactures the GP100 GPU die, featuring a 16nm FinFET process and 15.3 billiontransistors. It also produces a large silicon interposer on top of which the GPU is assembled atthe wafer-level with its four HBM2 stacks.

Samsung provides the HBM2 stacks. A 3D assembly process yields HBM2 stacks composed offour 1GB DRAM memory dies and one buffer die, connected with via-middle through-siliconvias and micro-bumps.

The report includes a complete physical analysis of the packaging process, with details on alltechnical choices regarding process, equipment and materials. Also, the completemanufacturing supply chain is described and manufacturing costs are calculated.

The report also compares the Tesla P100 with AMD’s Fury X, which uses HBM1 and 2.5Dassembly, to explain the interest in evolution through the HBM2 and CoWoS 2.5D platforms.Finally, it describes NVIDIA’s key module design and related process choices.

Targeted for High Performance Computing (HPC) anddeep learning, the NVIDIA Tesla P100 is the world'sfirst artificial intelligence supercomputing datacenter GPU. It uses various leading edgetechnologies, including 3D stacked memory with2.5D integration on a silicon interposer in a Chip-on-Wafer-on-Substrate (CoWoS) process.

Improving memory performance threefold over theNVIDIA Maxwell architecture, the Tesla P100accelerators are equipped with 12GB or 16GB ofsecond generation high bandwidth memory (HBM2).

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TABLE OF CONTENTS

Overview / Introduction

Company Profile and Supply Chain

Physical Analysis

• NVIDIA Tesla P100 Teardown

• Package

View, Dimensions &

Marking

Dies Size

• DRAM Die

View, Dimensions &

Marking

µBumps & TSVs

• Package Cross-Section

Laminate & Frame Cross-

Section

Interposer Cross-Section

GPU Cross-Section

HBM2 Stack Cross-Section

• Comparison with AMD Fury X

including SK-Hynix HBM1

Manufacturing Process Flow

• Global Overview

• GPU Process Description

Interposer Process Flow

• HBM2 Stack Process Flow

• CoWoS Process Flow

Cost Analysis

• Overview of the Cost Analysis

• Yields Hypotheses

• GPU Front-End & Die Cost

• Interposer Wafer & Die Cost

• DRAM Front-End Cost

TSV Manufacturing Cost

Micro-Bumping

Manufacturing Cost

• DRAM Die Cost

• Logic Die Cost

• HBM Stack Cost

• CoWoS Assembly

Manufacturing Cost

• Final Component Cost

Estimated Price Analysis

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AUTHORS:

ting in 2011 to setup itslaboratory. He previously workedfor 25 years at Atmel NantesTechnological Analysis Laboratoryas fab support in physical analysis,and for three years at HirexEngineering in Toulouse, in adestructive physical analysis lab.

YvonLe Goff (Lab)

Y vo n ha s jo i n edSystem Plus Consul-

for Advanced Packaging, MEMSand Integrated Circuits. He haspublished more than 50 ReverseCosting reports on various MEMSdevices including inertial,pressure, microphones or RFsensors.

Romain Fraux

Romain is in chargeof costing analyses

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