Number One
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Transcript of Number One
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Number One
Tom BozicIan NuberGreg RamseyHenry RomeroMatt Unangst
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GITHU Processor
General Purpose 32-bit, pipelined computer processor
MIPS-like architecture– Reduced instruction set
24-bit address space– 22 bits, concatenate with ending 00– 32 bit boundaries
16 Registers
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Registers
16 Registers (ease in immediate operations) 3 Special Purpose
– R0 – zero– R14 – stack pointer– R15 – return address
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Instruction Set Architecture
First two bits indicate instruction category– Load, store, bra/jump, R-type
16 bit immediate built into R-type reduces complexity of design
Addressing Modes– Direct– Indirect with Offset
ISA accounts for full address space– NO PC-relative addressing
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Instruction Format
31 30 29 24 23 20 19 16 15 0Op(2) Addr(6) Rt (4) Rs (4) Address Displacement (16)
31 24 23 20 19 16 15 12 11 0Opcode(8) Rd(4) Rs1 (4) Rs2 (4) Immediate (12)
31 30 29 26 25 24 23 20 19 0Op(2) Type(4) Addr (2) Rs (4) Address Continued (20)
Load / Store
R-Type
Bra / Jmp
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Instructions
Arithmetic– Add– Addi – add immediate– Sub– Subi – subtract immediate
Data Transfer– Ld - load word– St – store word
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Instructions
Logic– And– Andi – And immediate– Or– Ori – Or immediate– Nor– Nand– Sll – logic shift left– Slr – logic shift right
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Instructions
Branches– Beq – branch equal to zero– Bne – branch not equal to zero
Jumps– Jmp – jump to specified address– Jsr – jump to subroutine
Interrupt handler Save current PC in register
Nop – No Operation
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Datapath Diagram
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Functional Units
Register File ALU Control Logic Memory System Assembler
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Hardware
Xilinx XCV300/400/600/800 FPGA Keep FPGA on board Make PCB for all off-chip peripherals Connect two boards together via ribbon cable
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Processor I/O
Serial RS232 port LCD, Monitor outputs Keypad, Keyboard Inputs
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Vital Goals
Implement processor on FPGA in Verilog– Pipelined– Thorough simulation
Complete Assembler Keypad, LCD I/O Make PCB with off-chip peripherals Successfully run assembly program
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Extended Goals
On-chip caches (Instruction and data) C Compiler Monitor, Keyboard I/O Multiplier, Divider units Floating Point Units
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Individuals Roles
Tom Bozic– Assembler, control logic, documentation
Ian Nuber– Assembler, control logic, test-program design
Greg Ramsey– ALU, PCB design
Henry Romero– PCB design, Memory system
Matt Unangst– Pipeline implementation (forwarding, rollback)– Register File
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Schedule
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Risks
PCB issues (signal noise, speed, etc)– Wire wrapping
Pipeline complexity– Design allows for insertion of no-ops to essentially
turn machine into multi-cycle machine
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Questions?