Novel MOSFET-Like Transistor Structures - NNIN · 2019. 12. 19. · MOSFET F ll S liMOSFETs Follow...

Novel MOSFET-Like Transistor Structures

Jason C.S. Woo

University of California Los AngelesUniversity of California, Los AngelesElectrical Engineering

Jason Woo IWSG2009

Outline

• Needs for novel Device concepts• Asymmetric Channel DevicesAsymmetric Channel Devices• Schottky Transistors• Tunnel Source (PNPN)MOSFET• Heterojunctions CMOSHeterojunctions CMOS• Graphene MOSFETs

Jason Woo IWSG2009

Scaling Challengesg g

Challenges arising due to scaling in the sub-nm regime

Source/Drain-to Channel

Electrostatic

Channel Transport Limitation

(Mobility Reduction

Parasitic Effects (Source/Drain

Resistance/CapacitanceElectrostatic Coupling

(Mobility Reduction, Velocity saturation)

Resistance/Capacitance, Gate Leakage)

Jason Woo IWSG2009

End of Scaling in CMOS?End-of-Scaling in CMOS?Power vs. Node Frequency Vs. Node

300

350

400

450

(W/c

m2)

Freq. = 20GHz 65

75

85

95

ncy

(G

Hz) P=50W/cm2

P=100W/cm2P=200W/cm2

50

100

150

200

250

Pow

er C

onsu

mpt

ion Freq. = 50GHz

Freq. = 80GHz

25

35

45

55

switc

hing

freq

uen

Further scaled CMOS beyond 40nm will

030 40 50 60 70 80 90 100

Node (nm)

1530 40 50 60 70 80 90 100

node (nm)

Further scaled CMOS beyond 40nm will soon hit performance limit due to less-

scalable parameters like Vth, Vdd , signal-to-noise-[distortion] ratio current leakage and

Jason Woo IWSG2009

noise-[distortion] ratio, current leakage and substrate conductivity

Impact of CMOS ScalingPros:• Higher ft and fmax

• Higher gm

Scaling (Interconnect)

0.25μm(1P5M)

0.18μm(1P6M)

0.13μm(1P8M)

0.09μm(1P9M)

g gm

• More interconnect levels• Lower switching power

consumptionCons:

Vdd(V) 2.5 1.8 1.2 1.0-1.2Vth(V) 0.46 0.42 0.34 0.29ft(GHz) 30 60 80 120

Cons:• Lower signal headroom• Lower breakdown voltage• Lower effective gain (gmro)

fmax(GHz) 40 80 120 150Ion(μA/μm) 600 600 550 510Ioff(μA/μm) 10 20 320 10,000 g (gm o)

• Higher Vth & β mismatch • Higher device leakage• Higher gate resistance

gm(mS/μm) 0.3 0.4 0.6 1.0ro(KΩ⋅μm) 129 67 24 6gmro 39 27 14 6

• Less-scalable properties:

• Vdd, Vth

• Signal noise S/NLWVA Δ LWA Δβ

Ath(mV⋅μm) 7 5.5 4.5 3.6Aβ(%⋅μm) 2.0 1.9 1.8 1.7

Jason Woo IWSG2009

Signal, noise, S/N, I/O impedance

• Substrate conductivity

LWVA thth ⋅⋅Δ= LWA ⋅⋅Δ

=ββ

β

Impact of Scaling on Analog Performance

100 Lg=60nmL 100

Vth=0.25 - 0.35 V

80

ing

Lg=100nmLg=150nmLg=250nm

Black: Bulk

Vth=0.25 – 0.35 VFor Mid gap gateFDSOI MOSFET

40

60

rinsi

cG

ai Green: PDSOIBlue: FDSOI

Xj=10nmVds=0.8V

Ids=100μA/μm

20

40

Intr Xj 10nm

Tox=1.5nmTSi=15nm

foper=1GHz

0 50 100 150 2000

f (GH )

Jason Woo IWSG2009

fT (GHz)

SDE & Series Resistance Scaling TrendsSDE & Series Resistance Scaling Trends 60

70

Physical Gate Length2001 ITRS

h [n

m]

50

60

40

50

ch,id

eal [%

]

Max. Ratio of Rsd

to Ideal Rch

SDE

Dep

th

30

40

10

20

30

Rsd

/ R

c

engt

h or

S

10

20

2000 2002 2004 2006 2008 2010 2012 2014 2016 20180

10SDE Junction Depth

Gat

e L

Year

0

Year

)( thgs

oxchch VV

tLR−

∝

1

⇒ Scaled with Lg (Lch ↓, tox↓)

R /R ↑

Jason Woo IWSG2009

jsdshsd XN

RR 1∝∝ ⇒ Difficult to scale Rsh ⇒ Rsd/Rch ↑

(Nsd ↑, Xj ↓ )

Relative Contributions of Resistance ComponentsComponents

500m]

70]

NMOSFETs

300

400

500NMOS scaled by ITRS

tanc

e [Ω

μm

Rext

Rov

40

50

60

70

RcsdNMOS

ibut

ion

[%

100

200

erie

s Re

sist

Rcsd

Rdp

10

20

30

40 Rext

Rov

tive

Con

tri

32 nm 53 nm 70 nm 100 nm0

S/D

Se

Physical Gate Length32 nm 53 nm 70 nm 100 nm

0

10 Rdp

Physical Gate Length Re

lat

• Assumptions : Scaled according to ITRS projection Gradual doping & midgap silicide material

• R d will be a dominant component for highly scaled nanometer transistor

Jason Woo IWSG2009

Rcsd will be a dominant component for highly scaled nanometer transistor( Rcsd/Rseries is rising up to >> ~ 60 % for LG < 53 nm)

Relative Contributions of Resistance C tComponents

PMOSFETs700m

] 70

%]

400

500

600

stan

ce [Ω

μm PMOS scaled by ITRS

Rt

Rov

40

50

60 Rcsd PMOS

ribu

tion

[%

100

200

300

erie

s Re

sis

Rcsd

Rdp

ext

10

20

30

Rdp

Rov

Rext

ativ

e C

ontr

32 nm 53 nm 70 nm 100 nm0

S/D

Se csd

Physical Gate Length32 nm 53 nm 70 nm 100 nm

0

Physical Gate Length

p

Rela

• Relatively large Rov contribution, but still largest in Rcsd

( Rcsd/Rseries : ~ 60 % , Rov/Rseries : 20 ~ 30 % for LG < 53 nm)

Jason Woo IWSG2009

csd series ov series G

Ad d S/D E i iAdvanced S/D Engineering300

210

240

270

300

Rovce

[Ωμm

]

B P fil

Graded JunctionMidgap SilicideL

G = 53 nm • Potential solutions for

advanced S/D Engineering:

120

150

180

210

Rdp

Rext

Resi

stan

c

Box Profile

Box ProfileMidgap Silicide

⇒ Box-shaped highly-doped ultrashallow SDE

30

60

90

120 Rcsd

D S

erie

s R Low-Barrier Silicide(Φ

B = 0.2 eV)

junction (i.e., laser annealing)

⇒ Schottky Barrier0

30

Source/Drain Engineering

S/D ⇒ Schottky Barrier

lowering(i.e., ErSi for NMOS, PtSi2 for PMOS and

Jason Woo IWSG2009

PtSi2 for PMOS, and lower bandgap Si1-xGexlayer)

P d S l ti f Hi h P fProposed Solutions for High Performance Low Power Transistors

• New Materials with Higher Mobilities• New Gate Stack to Reduce Tunneling• New Gate Stack to Reduce Tunneling• New Contact Materials (Metal and

Semiconductor) to reduce RSemiconductor) to reduce Rco

• New S/D Structures (e.g. Raised S/D) for Small RS/DRS/D

• SOI, DG, … to improve SCE

Jason Woo IWSG2009

2-D MOSFETs-- Double Gate FETs

Jason Woo IWSG2009P. Wong

3D FETs -- Nanowire Transistors(1D Transport)

Samsung 2005

Jason Woo IWSG2009

I-V (Ballistic, DOS Capacitance)( , p )

Taur, TED 2008

Jason Woo IWSG2009

Essentially, Try to Make Scaled MOSFET F ll S liMOSFETs Follow Scaling

Behavior of “Long ChannelBehavior of Long Channel Device Miniaturization” by improving Electrostatic and T t ( bilit d )Transport (mobility and v)

Jason Woo IWSG2009

Alternatives?

New Device ArchitecturesNew Device Architectures• Novel Transports Mechanisms• Incorporate QM Effects• Incorporate QM Effects

New Materials• High Mobilities• Bnadgap Engineering

Others

Jason Woo IWSG2009

Lateral Asymmetric Channel (LAC) MOSFETConventional

S DLgate=0.12 μm

θTilt angle θLAC

1018

1019

1020

rity

Conv.

S Dgate μ

ratio

n -3

)

LAC: Tilt=10o

polypoly BF2 (NMOS) S D

1015

1016

1017

Impu

r Conv.

LACCon

cent

r(c

m-

-0.1 -0.05 0 0.05 0.1Lateral Position (μm)

10

Formation of Channels in the Simulated channel profiles for devices LAC and conventional structures. Usual tilt angle: 10o-15o

with same Vth from source to drain 1.5 nm away from the SiO2/Si interface.

Jason Woo IWSG2009

LAC Transistor

2LACDPConventional

2

m/s

)

LACDPConventional

11

1.5

eloc

ity (1

07 cm

05 V/c

m)

1

0.5

e C

arri

er V

e

Ey (1

0

-0.05 0 0.05Lateral Position y (μm)

0 -0.05 0 0.05Lateral Position y (μm)

0

Ave

LAC Devices: Higher doping near the source end ⇒

Ids = W Cox(Vgs-Vth(y)-V(y))v(y)

LAC Devices: Higher doping near the source end • High lateral electric field near the source end in channel region• High average carrier drift velocity near the source end in channel region• High current drive,

Jason Woo IWSG2009

LAC DEVICES: ANALOG PERFORMANCELAC DEVICES: ANALOG PERFORMANCE0.4

LAC Tox =25ÅLAC Tox =36Å

Å

15Vgt=0.3V, V ds=0.8V for Conv.Vds=0.8V, I ds same as Conv. for SP(V ~0 15-0 3V)

0.2

0.3 Conv. T ox =25ÅConv. T ox =36Å

(mS/

μm

)

10

/Id(

V-1

)

for SP(Vgt~0.15-0.3V).

0.1 NMOSV =0 8V

g m(

5LAC Tox=25 ÅLAC Tox=36 Å

g m/

0 0.2 0.4 0.6 0.8 1.00

Ids same at same Lg & Tox

Vds=0.8V

0 0.2 0.4 0.6 0.8 1.00

ToxConventional, T ox=25 ÅConventional, T ox=36ÅNMOS

Lg(μm)Lg(μm)

•g m is higher in SP devices•g m/Id ratio is very high compared to conventional devices when biased at same

current density :d t hi h t d i ll V t i d d Al hi h

Jason Woo IWSG2009

- due to high current drive, small Vgt is needed. Also high gm

Issues with LAC TransistorsIssues with LAC Transistors

• High doping near the source – Lower Mobilityg p g y• Sharp doping profile in sub45 nm transistors –

DifficultDifficult

Jason Woo IWSG2009

Split Gate Design

1.3

Potential profile for the HL devic e

H L Lg=45nmH gate

H -- L gate

0.3

0.5

/cm

) H-L gate H gate

0 7

0.9

1.1

pote

ntia

l (V

) Vds=0.2 VVds=0.4 VVds=0.6 VVds=0.8 VVds=1.0 V

Lg 45nmWH-WL=0.3eVVgt=0.2V, Vds=0V

H gate

Source Drain

-0.1

0.1

0.3

Fiel

d (M

V/

60

10.0 20.0 30.0 40.0 50.0 60.0Channel position (nm)

0.5

0.7

Vd 0 8 V

p- sub-0.5

-0.3

0.1

Lat

eral

E-F

0 5 10 150

20

40

60

EX

(kV

/cm

) H gateH - L gate

Vds=0.8 V• The work-function of the H gate is higher than that of the L gate 0.0 20.0 40.0 60.0

Channel position (nm)

-0.7L 0 5 10 15

Channel-X (nm)

•An electric field peak is generated in the channel close to the sourceside which enhances source carrier injection into the channel ( gm ).

R b i d d t th d d h l l th d l ti↑

Jason Woo IWSG2009

• Rout can be increased due to the reduced channel-length-modulation.

Simulation: Gm and Rout in scaled MOSFETs

2250Empty Symbol: H deviceSolid Symbol: HL device

50 400Empty symbol: H gate

1750

S/m

m)

30

40

t(K

Ω)

100

200

300Solid symbol: HL gate

Lg = 130 nm

Rou

t(K

Ω)

1250

Gm

(mS

Lg = 45 nm 10

20Rou

t

0 50 100 150 200 2500

Bias current (μΑ/ μm)

250

750Lg = 45 nmLg = 90 nmLg = 130 nmLg = 180 nm 0 100 200 300 4000

10Lg = 45 nm

Bias current (μΑ/ μm)

• Both gm and rout can be improved by using this split gate design

0 100 200 300 400 500Bias current (μΑ/ μm)

250 Bias current (μΑ/ μm)

Jason Woo IWSG2009

gm out p y g p g gfor different channel length considered.

Sb-induced Work Function Shift in the NiSi Gate

Tox = 2.6nm

NiSi/Oxide Capacitor, 100μm x μm

2.6nm

Tox 2.6nm100

ce (p

F) undoped NiSi

Sb doped NiSi50

Cap

atan

c Sb doped NiSi (1.5x1015cm-2)

-2.0 -1.5 -1.0 -0.5 0.0 0.5Gate Bias (V)

0

• NiSi Gate: Gate full silicidation and no oxide degradation.• Antimony implantation in the polysilicon gate reduces theNiSi gate work function (~0 25eV) due to the dopant

Jason Woo IWSG2009

NiSi gate work function (~0.25eV) due to the dopantsegregation effect at the NiSi/oxide interface.

Process Flow

PR

LTO

Sb

• Oxide/Poly/LTO:LTO

Si

Poly

Si

SiN SiNPoly oxide

Oxide/Poly/LTO:4.5nm/50nm/200nm

• Sb implant energy, Si Si

(a) (c)

p gy,dose and angle: 25KeV, 1.5x1015 cm-2, 30o

Nit id idthL TO

SiN SiNN iSi

NiSi NiSiSiN SiN

• Nitride spacer width : ~ 80nm

• Silicide conditions:Si Si

(b) (d)

• Silicide conditions: 10mins @ 450 oC

Jason Woo IWSG2009

Id-Vg and Id-Vds curves

(Substrates are undoped)5.0m tilt-angle doped(Sb) NiSi gate

U d d NiSi

3 0m

4.0m Lg=0.6μm Vg=2 V

Vg=1 5 V

Undoped NiSi gate

10 μ

m)

1E-4Lg=0 6μm10

μm)

2.0m

3.0m Vg=1.5 V

Vg =1.0 V

urre

nt (A

/ Lg=0.6μm VDS=0.1 V

urre

nt (A

/

Undoped NiSi

1E-5

0 0 0 5 1 0 1 5 2 0 2 50.0

1.0m Vg=0.5 V

Vg=0 VDra

in c

u

-0 5 0 0 0 5 1 0 1 5 2 01E-7

1E-6

Dra

in c

u

Tilt-angle Sb-doped NiSi

• Improved current drive capability is observed for the NiSi gate d i ith tilt l S i l t ti f th d i id i th

0.0 0.5 1.0 1.5 2.0 2.5Vds (V)

0.5 0.0 0.5 1.0 1.5 2.0Vg (V)

Jason Woo IWSG2009

device with tilt angle Sb implantation from the drain side, i.e, the split-gate device.

Scalable?

2250Empty Symbol: H device

1750

mm

)

Empty Symbol: H deviceSolid Symbol: HL device

1250

m(m

S/m

40

50

Ω)

750

g m

10

20

30R

out(

KΩ

0 100 200 300 400 5002500 100 200 300 400

Bias Current (μA/μm)

0Lg = 45 nm

Jason Woo IWSG2009

Bias Current (μA/μm)

Improved speed-gain performance

350 Vth=0.15--0.25Vth=0.25--0.35

L 45300

GH

z)Lg=45nmIDS =100 μ A/μm

Lg=45 nm250F T

(G

200Lsp=27.5 nmLsp=30 nmLsp=35 nmLsp=40 nmLsp=45 nmEmpty symbol: H device

Solid symbol: H-L device

SplitSplit--gate HL MOSFETs have improved gaingate HL MOSFETs have improved gain-- frequencyfrequency

10 20 30 40Intrinsic Gain

150Solid symbol: H L device

Jason Woo IWSG2009

SplitSplit--gate HL MOSFETs have improved gaingate HL MOSFETs have improved gain-- frequency frequency performance compared with conventional MOSFETsperformance compared with conventional MOSFETs

Laterally Asymmetric SiGe MOSFET

Conventional MOSFET Design: Constant Vth across theConventional MOSFET Design: Constant Vth across the channel

Channel Engineering using Band gap Engineering Concept: Modification of threshold voltage across the channel

Vth (Source Side)>Vth (Drain Side)Vth (Source Side)>Vth (Drain Side)

Conduction Band offset (ΔEc) between materials changes VthConduction Band offset (ΔEc) between materials changes Vth across the channel

Jason Woo IWSG2009

Band Gap Engineering for MOSFET ChannelBand Gap Engineering for MOSFET Channel

Tension Compression Tensionzzz

Si1-xGexSi1-yCySi

SiSi Si1-xGex

’

Ec EcEc

Strained ΔEc~5y [eV] ΔEc~0.6x [eV]

z’z’z’

Ev Ev Ev

Si1-xGexStrained -SiSi1-xGexSiStrained

Si1-yCySi

ΔEv~0.5x [eV]

Jason Woo IWSG2009

Ev EvSuitable for

PFETSuitable for

NFETSuitable for

NFET

Novel Asymmetric SiGe/Strained Si MOSFETNovel Asymmetric SiGe/Strained-Si MOSFET

Gate

Poly-Si

Source Drain

P Si0.30Ge0.70n+ Si0.30Ge0.70 n+ Strned-SiP Strned-Si

BOX

Si

Jason Woo IWSG2009

Digital Performance: Ion/Ioff ComparisonLg=50 nm, tsi=20 nm, tox=1.5 nm, Na=2x18 cm-3

Ioff same, VDS=1.0V1.6x10-3

Asymmetric

(A/μ

m)

1x10-4

10-3

1.0x10-3

1.2x10-3

1.4x10-3

A/μ

m)

Asymmetric Ch l MOSFET

Asymmetric Channel MOSFET

Conventional

Dra

in c

urre

nt (

1x10-5

4 0x10-4

6.0x10-4

8.0x10-4

rain

cur

rent

(AChannel MOSFET

Conventional

Conventional Si MOSFET

D

0.0 0.2 0.4 0.6 0.8 1.010-7

10-6

0.0 0.2 0.4 0.6 0.8 1.0

2.0x10-4

4.0x10 DSi MOSFET

Gate Voltage(V) Gate Voltage(V)

Improved Ion/Ioff ratio (15% improvement)

Jason Woo IWSG2009

Comparable Subthreshold Swing (S)

Analog Performance Trends: Gm & Rout ComparisonsLg=50 nm, tsi=20 nm, tox=1.5 nm, Na=2x18 cm-3

Ioff same, VDS=1.0V

2 0 10-3

2.2x10-3

4

3.0x104

/μm

) 1.6x10-3

1.8x10-3

2.0x10 3

2.0x104

2.2x104

2.4x104

2.6x104

2.8x104

μm)

Asymmetric Channel MOSFET Asymmetric

Channel MOSFET

Gm

sat (

S/

1.0x10-3

1.2x10-3

1.4x10-3

1 0x104

1.2x104

1.4x104

1.6x104

1.8x104

Rou

t(Ω

/μ



0 100 200 300 400 500

6.0x10-4

8.0x10-4

0 100 200 300 400 500

4.0x103

6.0x103

8.0x103

1.0x10

Ibias (A/m ) Ibias (A/m )

Higher gm & gm/Ids ratio (low power) due to enhanced source injection

Higher output resistance due to reduced CLM

Jason Woo IWSG2009

Higher output resistance due to reduced CLM

Higher Intrinsic gain (gm x rout)

Best Semiconductor Junctions –Bandgap Engineering?Bandgap Engineering?

Jason Woo IWSG2009S.M. Sze “Semiconductor devices” Wiley, 1985

III-V/Si Co-Integration IssuesgIssues:• Incompatibility with Si CMOS process/infrastructure in large area co pat b ty t S C OS p ocess/ ast uctu e a ge a ea

material growth and wafer bonding• Poor device yield • Poor device reliability

S i th l i t h• Serious thermal mismatch

Potential Solutions:E b dd d h t th t th l d i l l i• Embedded heterogeneous growth at the nanoscale device level in selective drain/channel/source areas

• Choose the best heterojunctions for the best circuit functions• Exploit bandgap engineering for higher injection efficiency fasterExploit bandgap engineering for higher injection efficiency, faster

carrier transport, higher breakdown and lower leakage currents• Continue to use silicon as a substrate for mass production

compatibility

Jason Woo IWSG2009

Selective Heterojunctions for Functions

P l Si Metal?

Si Si

Poly SiOxide

INSb/InAs/Ge InPGaN ?

Metal? High-K Insulator

InSb/InAs/Ge?Si/SiGe

Si/SiGe CMOS COSMOS CMOS

Si Substrate/SOI Si Substrate/SOI

Nano-scale heterogeneous integration in selective

Si/SiGe CMOS COSMOS CMOS

Nano scale heterogeneous integration in selective device areas may lead to ultra-high performance

and excellent reliability

Jason Woo IWSG2009

Low Power High Performance Digital

175195

Hz)

Low Power High Performance Digital

P=50W/cm2

P=100W/cm2

PotentialP=10W/cm2

135155175

ncy

(G

H

P=200W/cm2

Scaled CMOS95115135

Freq

uen

5575

itchi

ng F

304050607080901001535Sw

i

Jason Woo IWSG2009

30405060708090100node (nm)

Potential for High Performance Mixed Signal

260Analog Behavior

Potential for High Performance Mixed-Signal

22000

27000

Hz)210

260

)

COSMOS Goals

12000

17000

22000

Gai

n (G

H

110

160

ft (G

Hz)

> 4X> 10X

7000

12000

ft *

G

60

110f

Silicon CMOS

200030507090110130150170

Node (nm)

10

Jason Woo IWSG2009

( )

Novel Source Injection MOSFETNovel Source Injection MOSFET

I. Asymmetric I. Asymmetric SchottkySchottky Tunneling Tunneling yy yy ggSource Injection MOSFETSource Injection MOSFET

“A novel device structure incorporating gate controlled “A novel device structure incorporating gate controlled source injection by schottky barrier tunneling” source injection by schottky barrier tunneling”

Jason Woo IWSG2009

MotivationMotivationScaled MOSFET performance is increasingly limited by:

1. Parasitic Resistances : 2. Electrostatics and transport :Source / Drain junction resistance Non Scalability of subthreshold swing

(diffusion limited) as well as built in voltage of p-n junctions

Metal Source/ Drain junctions Source injection of carriers through different gate controlled mechanismdifferent gate controlled mechanism

Schottky Source Tunneling MOSFET:Schottky Source Tunneling MOSFET:y gy g•Fully Silicided Source/Drain junctions

•Gate controlled source injection through schottky barrier

Jason Woo IWSG2009

tunneling

Schottky Barrier FETsSchottky Barrier FETsIssues and ProblemsIssues and ProblemsGateMetal

•Large φb causes reduction in drive currentSource Drain

g φb•Drain Side SB causes reverse drain leakage as well as degradation in current in the linear region•High resistance region under the spacer causes potential drop

Resistance like Resistance like behavior observed behavior observed in the linear region in the linear region of the Iof the IDD--VVDD curvescurves

Jason Woo IWSG2009

QQ.. TT.. ZhaoZhao etet al,al, MicroelectronicMicroelectronic EngineeringEngineering,,VolVol.. 7070,, pppp.. 186186,, 20032003..

Schottky Barrier FETsSchottky Barrier FETsPotential solutionsPotential solutions

U ll ( i i 0 28 V (E Si2) fGate

Use small φb (minimum: 0.28eV (ErSi2) for electrons and 0.25eV (PtSi) for holes)

but φb always positive also increases back injection leakage

Source Drain

also increases back injection leakage

Use doped extension under the spacer Reduces drop at the junction byReduces drop at the junction by reducing eff. φb

Eliminates high Resistance region under the gate

Doped extension

The sourceThe source--channel and channel and drain channel contacts drain channel contacts are now ohmic and not are now ohmic and not

under the gatebut transistor becomes conventional like

eliminates advantages of

Jason Woo IWSG2009

schottky in natureschottky in natureSchottky Barrier

How about Analog ApplicationsSource injection of carriers by tunneling at

the source schottky junction

N+ Region on the drain side to form ohmiccontact between drain and channel

0 .3 0

0 .4 5

J

J T h e r m io n ic I n c r e a s in g G a te V o lta g e

ge (e

V)

0 .0 0

0 .1 5J T u n n e lin g

uctio

n B

and

Edg

SourceThe gate controls tunneling through the schottky barrier by changing the tunneling

-4 -2 0 2 4 6 8 1 0 1 2 1 4

-0 .3 0

-0 .1 5

Con

duwidth as well as the available density of states on the semiconductor side

Jason Woo IWSG2009

4 2 0 2 4 6 8 1 0 1 2 1 4D is ta n c e a lo n g c h a n n e l (n m )

Effect of Barrier Height (φb)1x102

φb = 0.25eV

At same tOX, subthreshold char dominated by tunneling

1x100

1x101

0.45eV

b char. dominated by tunneling at high φb

For small φb, the current

1x10-2

1x10-1

0.65eV

μA/μ

m)

For small φb, the current is limited by the virtual cathode point in the channel (diff i li it d)

1x10-4

1x10-3 tOX = 20 Å

V = 0.1V

I D ( (diffusion limited)

However, Short Channel Eff t (DIBL)

0 0 0 2 0 4 0 6 0 8 1 01x10-6

1x10-5 VD 0.1V VD = 1.0V

Effects (DIBL) are considerably improved with tunneling at high φb

Jason Woo IWSG2009

0.0 0.2 0.4 0.6 0.8 1.0VG (V)

b

Effect of Drain pocket (NDrn)

1200

1500

φb = 0.45eVÅ

Vg=1.0 V

no drain pocket with drain pocket

Degradation in ID mainly caused

300

600

900 tOX = 5Å

Vg=0.6 V

Vg=0.8 V

D (μ

A/μ

m) due to a drop across the forward

biased schottky junction at the drain side.

0.0 0.2 0.4 0.6 0.8 1.00

300 Vg=0.4 VI D

V (V)

side.

1µ10µ

Sim.

VD (V)

1001n

10n100n

µ

no pocket

F (A/μ

m)

Increase in IOFF due to back injection of holes from drain to source

0 0 0 4 0 8 1 2 1 61p

10p100p

n+ drain pocket

I OFFA n+ type pocket makes the drain side

junction ohmic and hence prevents back-injection

Jason Woo IWSG2009

0.0 0.4 0.8 1.2 1.6VD (V)

Scalability of the STS-FETDramatic Improvement in VTH roll-off and Drain0.25

0.30

120

150

SOI FET V) VTH roll off and Drain Induced Barrier Lowering (DIBL) with increasing φb0.15

0.200.25

Vth

(V)

60

90

120SOI-FET (φb=0.25eV) (φb=0.45eV)(φb=0.65eV) B

L (m

V/V

0.45 Immune to

ge60 90 120 150 180

0.050.10

0

30(φb )

DIB

The junction at the 0.000.150.30

Immune toincrease in VD

Ban

d E

dg

60 90 120 150 180LG (nm)

The junction at the source side is not affected by drain voltage (immune -0 45

-0.30-0.15 Increasing Drain

Voltage

ondu

ctio

n

Jason Woo IWSG2009

y g (to drain field) 0 20 40 60 80 100

-0.45

Co

Distance along channel (nm)

Analog Performance: gm

1 0 0 0

1 2 0 0

6 0 0

8 0 0

(μS/

μm)

2 0 0

4 0 0 F D - S O I B H = 0 . 3 0 e V

Gm

0 5 0 1 0 0 1 5 0 2 0 00

2 0 0 B H = 0 . 4 5 e V B H = 0 . 5 5 e V

B i a s C u r r e n t ( μ A / μ m )

At low bias currents, gm of the STSFET is higher than that of the conv. SOI-FET due to the difference in injection mechanisms The gain in gm

Jason Woo IWSG2009

SOI FET due to the difference in injection mechanisms. The gain in gm is higher as the barrier height decreases.

Analog Performance: ROUT1 0 4

1 0 3

(KΩ

-μm

)

1 0 2 F D - S O I B H = 0 . 3 0 e V B H = 0 . 4 5 e V

Rou

t

0 5 0 1 0 0 1 5 0 2 0 01 0 1

B H = 0 . 5 5 e V

B i a s C u r r e n t ( μ A / μ m )B i a s C u r r e n t ( μ A / μ m )

At low bias currents, ROUT of STSFET is superior to conv. SOIFET due to improved DIBL The ROUT ~ constant w r t φb

Jason Woo IWSG2009

to improved DIBL. The ROUT constant w.r.t φb. Tunneling mechanism high ROUT

3

Analog Performance: Gain (AV)1 0 3

1 0 2 F D - S O I B H = 0 . 3 0 e V B H = 0 . 4 5 e V ai

n (A

v)

1 0 1B H = 0 . 5 5 e VG

a

0 5 0 1 0 0 1 5 0 2 0 01 0 0

B i a s C u r r e n t ( μ A / μ m )( μ μ )•The gain is ~10X more than that of conventional SOI-FET •Increase in gm and ROUT for low bias currents (<200μA/μm) makes it an ideal candidate for low power high performance circuit design

Jason Woo IWSG2009

an ideal candidate for low power high performance circuit design

Frequency-Gain Performance

3

STS-FET SOI-FET

2.0x103 STS-FET SOI-FET

103

Ibias = 100 (μA/μm)Gai

n

3

1.5x103

Gai

n

102

Intr

insi

c

5 0x102

1.0x103 Ibias = 100 (μA/μm)Vth = 0.2 - 0.35V

Intr

insi

c 30 60 90 120

101Vth = 0.2 - 0.35V

I

30 60 90 1200.0

5.0x10I30 60 90 120

ft (GHz)30 60 90 120

ft (GHz)Improvement in Frequency-Gain performance for different

technology nodes

Jason Woo IWSG2009

technology nodesSuitable for High performance, low power transistors

N-FET device

1x1021x103

S h k1.1VVD=1.6V

ID-VG char. for the NiSi STS nFET LG = 0.15μm

250

300

350 S im . D ata E xp. D ata

old

Swin

gde

c)

1x10-11x1001x101 Schottky

Tunneling Current0.1V

0.6V

m) 100

150

200

SS = 60 + 4 .7 x tO X

Subt

hres

ho(m

V/d

1x10-41x10-31x10-2

0

Lg=0.15μm

I D (μ

A/μ

0 10 20 30 40 5050

O X

O xide th ickness (Å )

10µ

0 1 2 3 41x10-61x10-51x10 Lg 0.15μm

tOX=30Å

V (V) 1n10n

100n1µ

10µ

no pocket

Sim. Exp.

A/μ

m)VG (V)

1p10p

100p1n

n+ drain pocket

I OFF

(AObserved drain leakage due to back-injection of h+ (ambipolar transport)

Jason Woo IWSG2009

0.0 0.4 0.8 1.2 1.6VD (V)

SummaryNeed to explore alternate structures to achieve high

performance low power transistorsp p

Asymmetric Schottky Tunneling Source MOSFETt i t d dconcepts introduced

φb ~ 0.3 – 0.65eV, EOT < 10Å,

Drain-side pocket to improve linear characteristics

Optimized device structure highly immune to ShortChannel Effects Very Scalable Transistor Structures

Jason Woo IWSG2009

gm is higher than conv. SOI-FET at low bias currentsmaking it ideal for low power high performancemaking it ideal for low power, high performanceapplications

Big Improvement in ROUT and intrinsic gain(gmxROUT) even at LG < 90nm at low currents

Exceptional frequency-gain performance for lowpower high performance applicationspower, high performance applications

Promising Alternative for mixed mode, RF and SOC

Jason Woo IWSG2009

applications

Novel Source Injection MOSFETNovel Source Injection MOSFET

II. QM-Injection TransistorsVs/db

unscaled Vth Vsupply Exploit novel device physicsunscaled

S Ioff Ion

Exploit novel device physicsconcepts made possible bynano-dimensions to achievet bth h ld i dS Ioff Ion

Hi h I d d d I /I i

steep subthreshold swing andballistic carrier transport togive high Ion.

Higher Ioff and reduced Ion/Ioff ratio

V Source/Drain-Substrate Junction Potential

Jason Woo IWSG2009

Vs/db – Source/Drain-Substrate Junction PotentialVth – Threshold VoltageS – Subthreshold Swing

BackgroundChallenges arising due to scaling in the sub-30nm regime

Channel Transport Parasitic Effects VDD scaling:

g

Source/Drain-to Channel

Electrostatic Coupling

Channel Transport Limitation (Mobility

Reduction, Velocity t ti )

Parasitic Effects (Source/Drain

Resistance/Capacitance, Gate

L k )

VDD scaling: Subthreshold Swing >

60mV/Decade⇒ min VTH for given

ICoupling saturation) Leakage)

Proposed Solutions

Ioff⇒ low Ion/Ioff

Proposed Solutions• Improved Device Architecture (Double or Tri-gate MOSFETS)• New materials to enhance transport (SiGe or Ge channel)• New Gate Dielectrics to reduce gate leakage (High-K dielectrics)g g ( g )

Rationale of these approaches:Make the device “Long-channel” like

Jason Woo IWSG2009

(instead of exploiting new device physics opportunitiesafforded by nano-dimensions)

54

VDD ScalingDD g• Low power devices with continued VDD scaling need

- Reduced Vth to have reasonable ION at low VDDth ON DD

- Small IOFF even with low Vth

• Conv. MOSFET Subthreshold Swing limited to60mV/dec (@300K) due to diffusion mechanism

• Alternate mechanisms of carrier injection not limitedby diffusion limited swing:

–TunnelingPotential reduction in subthreshold swingPotential reduction in subthreshold swing

–Impact IonizationNeed of high VDD (> EG/q) to have working FETs

Jason Woo IWSG200955

MotivationIn order to continue scaling of transistors for low power

digital and analog circuits alternate structures must be exploreddigital and analog circuits, alternate structures must be explored

These alternate structures must be optimized for both analogand digital performance conducive to SOC applicationsg p pp

The Tunnel Source MOSFET: (PNPN FET)

Hi h R i SCE E t l l blSignificant low-powerf i

( )

Jason Woo IWSG2009

High Resistance to SCEs Extremely scalablePerformance improvementOver conventional devices

56

Tunnel TransistorsPrevious efforts on p-i-n structure using gate modulatedtunneling injectiong j

TFET (P-I-N)Nirschl. T et al, EDL, vol. 28, 4, pp. 315, 2007

Vertical TFETBhuwalka et al, TED, vol. 51, 2, pp. 279, 2004

• Hitoshi Kisaki Proc IEEE vol 61 No 7 pp 1053 1054 1973• Hitoshi Kisaki, Proc. IEEE, vol. 61, No. 7, pp. 1053-1054, 1973• W. M. Reddick and G. A. J. Amaratunga, APL., vol. 67, no. 4, pp. 494–497, 1995• Qin Zhang, Wei Zhao, Alan Seabaugh, EDL, Vol. 27, No. 4, 2006, pp. 297-300

• Simple Structure to fabricate but large drop at the tunneling

Jason Woo IWSG2009

• Simple Structure to fabricate, but large drop at the tunnelingjunction causes 100X reduction in current

57

Tunnel Transistors

Experimental TFETW. Y. Choi et al, EDL, vol.28, 8, pp. 743

p-i-n FETK. Boucart et al, ESSDERC 2006, pp. 383

• Experimental verification of the p-i-n concept, however a 100Xreduction in current compared to conv. FET

Jason Woo IWSG2009

• ambipolar nature of the device

58

Alternative Tunnel TransistorPossible solutions

• Make the tunneling junction more abruptMake the tunneling junction more abrupt

• Increase the lateral electric field at the source sidejunction and reduce tunneling widthjunction and reduce tunneling width

• Asymmteric structure to eliminate ambipolar conduction

Alternative Solution:Tunnel source PNPN-FET has advantages over p-i-n

• Reduced potential drop at the tunnel junction• Improved drive current• Reduced ambipolar conduction

Jason Woo IWSG2009

Reduced ambipolar conduction

59

Device Concept•Novel device concept based on Band-to-Band Tunneling•Gate controlled tunneling junction is a source of electrons•Gate controlled tunneling junction is a source of electrons(Tunneling width is reduced by the fully depleted N+ layer)

SilicideSilicideSilicide

Poly

n+ source fully depleted

Gate

Poly

n+ source fully depleted

Gate

Pol

n+ source fully depleted pocket

Gate

Polypocket

P+ Source N+ Drain

Polypocket

P+ Source N+ Drain

Poly

P+ Source N+ Drain

Bulk (p)Bulk (p)BOX


Tunnel Source (PNPN) n-MOSFET ( )Gate Electrode controls the source-to-channel tunneling

t bcurrent by

• modulating the band-alignment between the valencemodulating the band alignment between the valenceband of the tunneling-source junction and the conductionband of the channel, thus modulating the availability ofdensity of states for tunneling

d l i h li id h ( hi h i l d d• modulating the tunneling width (which is already madesmall because of the narrow and fully depleted n-pocket)


Device ConceptConduction Band

( )Conduction Band

(b)(a) (b)

Valence Band Valence Band

• When VG < VTurnon, I is small since the electrons from the P+

valence band can tunnel only to the trap states+• When VG > VTurnon, electrons from the P+ source valence

band tunnel to empty states in the conduction band of thechannel

Jason Woo IWSG2009

(VTurnon – Gate voltage required for conduction and valencebands to overlap)

62

FD Pocket Essential 1.0

1.5

(eV

) W= 4 nm

1.0

1.5 W= 15 nm

(eV

)

1 0-0.5

0.0

0.5

n E

nerg

y

ECEV

-0.5

0.0

0.5

ECEV

n En

ergy

(

2 5

-2.0-1.5

-1.0

Elec

tron

Just Full Depletion -2.0-1.5

-1.0

Partial DepletionElec

tron

0.00 0.05 0.10 0.15 0.20-2.5

Distance along channel (μm) 0.00 0.05 0.10 0.15 0.20-2.5 Partial Depletion

Distance along channel (μm)W – width of the n+ pocket

Band diagrams illustrate the importance of full depletion of the pocket. For pocket which is only partially depleted, injection

Jason Woo IWSG2009

mechanism is no longer tunneling

63

Device SimulationQuantum Mechanical Tunneling

(Band-to-Band)governed by

( a d to a d)

d b

Tunneling Probability (Tt)dependent on the

Fermi Selection RuleFFVV (E)* (E)* [1[1--FFCC (E)(E)]*]*u(E)u(E)

Where u(E) =1 if there is availability of states

governed by

dependent on the Tunneling width

(incorporating phonon energy term)

to tunnel to; 0 otherwise. FV(E) and FC(E) are Fermi-Dirac distribution functions for the initial and final energy states.

Tunneling current: Esaki Diode integral IV-C=A ∫ FV (E)*nV (E)*Tt *[1-FC (E)]*nC (E)* u(E)dE

energy term)


Methodology for ATLAS simulationsInitial Guess for ATLASBand-to-Band tunneling

ATLAS Device Simulator with Band-to-Band tunnelingM d l d t l tparameter (BB.A) Model on used to evaluate

channel current (Ichan)

Esaki tunnel diode formalism usedto calculate tunneling current (Itun)

at the tunneling source junction using

Solution convergedUsed as starting guess

for next bias point simulated structure from ATLASfor next bias point

0.999 < Itun/Ichan < 1.001? Tweak parameterBB.A

NoYes


Device Calibrationm

2 ) Parameters:

sity

(A/c

m

Effective mass m,tuned to obtain a fit

i h h

rren

t Den with the

experimental data f ili t l

Cur from silicon tunnel

diodes Reverse Voltage (V)

Theoretical Reverse bias tunneling diode current matched with experimental p+/n+

Jason Woo IWSG2009

p pdiodes. Ref: M.W. Dashiell et al, TED, Vol. 47, no.9, 1707 (2000)

66

Pocket Design

300

360

W=4nmPocket Doping = 5x1019cm-3

1.6x1020

7080 ID = 1 nA/μm

ID = 100 nA/μm

180

240 W=15nm Conv SOI

(mV

/dec

)

8.0x1019

1.2x1020

MA

X (c

m-3)

405060

mV

/dec

)

0

60

120

SS (

0.0

4.0x1019N D

M

203040

SS

(m

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1V

G - V

T (V)

• Pocket should be fully depleted for subthreshold swing to go below60mV/dec

2 4 6 8 10Pocket Width W (nm)

60mV/dec• Pocket width should be small (<6nm) for SS to be appreciably below the diffusion limit

•(Doping x Width1.4 ≈ Constant)

Jason Woo IWSG2009

(Doping x Width Constant)• For all subsequent slides: Pocket width = 4nm and Pocket doping = 5x1019cm-3

67

Device Scalability

0.300.32

260

0.260.280.30

(V) 220

240

PNPN mV

/V)

0.220.24

V

THLI

N

180200 PNPN

SOI

DIB

L (m

40 50 60 70 80 90 1000.180.20

Ch l L h L ( )140160 D

Channel Length LG (nm)

• Optimized structure is very scalable• Suppression of short channel effects as compared to conv SOI FET with

Jason Woo IWSG2009

• Suppression of short channel effects as compared to conv. SOI-FET with respect to Vth roll off and DIBL

68

Low Standby Power Performance

1x105

1x106PNPN

1x104

1x10

I OFF

1x102

1x103

TSI=60nm

TOX = 1.1nm TOX = 2.5nm

I ON/I

40 50 60 70 80 90 1001x101

SI

Conv SOI

LG (nm)• Degradation in subthreshold swing and IOFF with scaling is

negligible for the tunneling device

Jason Woo IWSG2009

• As a result, ION/IOFF is improved by 3 orders over conventionalSOI with scaling – highly beneficial for low standby powerapplications 69

Low Operating Power Performance

3540

(a) TOX = 1.1nm TOX = 2.5nm

m) 30

35 (b) L 45

TOX = 1.1nm T

OX = 2.5nm

15202530 LG = 45nm

VTH

= 0.3-0.35 V

T (K

Ω−μ

m

152025 PNPN

LG= 45nmVTH = 0.3-0.35V

x R

OU

T

05

1015

Conv. SOI

PNPN

RO

UT

51015

Conv. SOIGM

0 200 400 600 800 10001200

0 Conv. SOI

ID (μΑ/μm) 0 200 400 600 800 100012000

ID (μΑ/μm)

Tunnel n-FET also exhibits an improvement in ROUT over theconventional SOI for the given channel length as in (a). This can beattributed again to reduced drain coupling and resistance to SCEs.

Jason Woo IWSG2009

Intrinsic gain (GM x ROUT) is higher than the conventional device, asshown in (b), especially at low IBIAS.

70

Vertical PNPN MOSFETTunneling junction doping profile needs to be sharp, which is easier to achieve with growth techniques rather k twhich is easier to achieve with growth techniques rather than ion implantation

Vertical PNPN Transistorp+ Source

pn+ pocket

In addition, vertical transistors have the advantages:• Immunity to short-channel effects (multi-gate structure)

p channel

Gate

Gate

)• Lithography independent critical dimensions (less process variation) • Higher on-current (multiple channels in one device)

n+ Drain

l

• Potential in 3-dimensional integration


SummaryNeed to explore alternate structures to continue scaling for low

power applications

The Tunnel Source MOSFET (PNPN tunnel nFET) has very lowstandby power due to smaller than 60mV/dec subthreshold swingy p g

Optimized device structure highly immune to Short ChannelEffects Very Scalable Transistor Structures

Achievement of Sub-threshold swing well below the diffusionlimit of 60mv/dec (at 300K) with Very Low IOFF and consequently ahi h I /I ihigher ION/IOFF ratio

Improvement in intrinsic gain (gmxROUT) even for sub-90nmchannel lengths at low bias current levels

Jason Woo IWSG2009

channel lengths at low bias current levels

72

Ultimate High-Mobility Channel Monolayer UTB FETs – Graphene?Monolayer UTB FETs – Graphene?

Jason Woo IWSG2009

0Dfullerenes

1Dcarbon nanotube

3Dgraphite

0D fullerenes, 1D carbon nanotube and 3D graphite can be

2D

regarded as the wrap and stacks of several layers of graphene.

Graphene: 2DGraphene

Graphene: single sheet of graphiteunwrapped SWNT

Jason Woo IWSG2009

Graphene Deposition MethodsMechanical exfoliation

hili i l ( )

Jason Woo IWSG2009

Philip Kim, et al. (2005) K.S.Novoselov, et al. (2004)

Graphene Deposition MethodsEpitaxial growth ---- thermal desorption of Si on (0001) face of single crystal 6H-SiC;

Jason Woo IWSG2009

Walt A.de Heer, et al. (2006)

Chemically Converted Grapheney pReview: Graphite is oxidized via modified Hummer’s method and simultaneously reduced and dispersed in anhydrous hydrazine.

N2H5+

N2H5+

Thermally annealThermally anneal

N2H5+

N H +

Solution processable chemically converted graphene has been developed by the Kaner Group for electrical testing and nucleation

N2H5+

Jason Woo IWSG2009

developed by the Kaner Group for electrical testing and nucleation growth tests with the CERA team.

77

Chemically Converted Grapheney p1. Reduction of these new graphite oxides have been achieved 2. Single sheet dispersions using purification techniques g p g p q

previously described is being investigated 3. These films are useful for the development of Graphene

channel FETs and for the study of graphene electricalchannel FETs and for the study of graphene electrical propoerties.

10 um


Graphene Deposition Methods4. Chemical vapor deposition using Ni as catalyst.

Alfonso Reina, et al. Nano Lett. (2009)

Jason Woo IWSG2009

Graphene Deposition MethodsChemical synthesize from reduced graphite oxide.

N2H4

Spin coat on substrate

Vincent Tung, et al. Nature Nanotech., (2009)

Jason Woo IWSG2009

Graphene Deposition Methods

Radio frequency plasma-enhanced chemical vapor deposition.

Jason Woo IWSG2009

J.J.Wang, et al. (2004)

Graphene Film Formation over Large Areas:Graphene Film Formation over Large Areas: Current Technology

1. Mechanical ExfoliationScotch tape is used to peel and stamp single and/or few layers from HOPG (the yield is exceedingly low).

2. Reduction of Silicon Carbide2. Reduction of Silicon Carbide1,100°C can be used to make very small regions of graphitic carbon

3 Intercalation and Exfoliation3. Intercalation and ExfoliationDifficulty is the strong van der Waals forces between sheets

Graphene properties demonstrated to date are marginal for RF Electronics – not clear that this process can be easily enhanced to improve materials or applicable to large silicon wafers.

Jason Woo IWSG2009

improve materials or applicable to large silicon wafers.

Fundamental Challenges of CVD Graphene on Ni

Common characteristics of the reported results:Common characteristics of the reported results:• Non-homogeneity of graphene thickness;• The presence of wrinkles;• The presence of wrinkles; • The expected grain boundaries in graphene.

Basic challenges:Basic challenges:• The multiple grained structure of blank Ni films on

various substrates:v ous subs es:• The unavoidable multiple nucleation of graphene;• The inability to control the location of graphene grain

Jason Woo IWSG2009

boundaries.

83

Large size monolayer graphene and the Raman spectra

One LTwo L

Two layer graphene

30um

O i f h h Two layer graphene

Large size high quality 1-2 layer

OM image of the graphene

Large size high quality 1 2 layer graphene film without grain boundary

Jason Woo IWSG2009

One layer graphene 84

Graphene transfer using PDMS

Pick‐up Transfer

Continuous film

t‐Graphene

PDMS

(Grap’n/Ni/)SiO2/Si

Sample 06292009‐3

(1) Pick-up process : Attaching the PDMS with the CVD-grown Grap’n/Ni/SiO2/Si and etching Ni/SiO (FeCl solution or HCl)

-We achieved the transfer yield as high as 95% with the size of a quarter

etching Ni/SiO2 (FeCl3 solution or HCl)(2) Transfer process : Putting the FLG/PDMS onto the 300 nm SiO2/Si substrate to transfer

Jason Woo IWSG2009

-We achieved the transfer yield as high as 95% with the size of a quarter of 2 inch diameter wafer.

85

Graphene as grown and after transferred

Graphene was synthesized by CVD using camphor as carbon sourceg p

SEM image of the graphene grown on Ni poly-crystaline surface at 850oC.

Transfer 26992699

SEM image of the graphene

Jason Woo IWSG2009

SEM image of the graphene after transferred onto SiO2 surface.

Raman spectrum of the transferred graphene which indicates the graphene.

86

Single Grain Patterned NiSingle Grain Patterned Ni

1. Pattern and etch of annealed Ni film;2. Thick Ni film deposited on patterned surfaces +

anneal + CMP3. Annealing of patterned Ni with a capping layerg p pp g y

Jason Woo IWSG2009

Process flow

SiO2Ni

SiO2TiN

Si substrate

Pattern TiN/SiO2

Ni

substrateDeposit Ni/SiO2on SiO2

Anneal at1000C 5minTiN

R SiO2CMP t t

Ni

SiO2

Si

Jason Woo IWSG2009

Remove SiO2CMP to getflat surface

Si

88

SEM picture of annealed Part 1

psample

Jason Woo IWSG2009

Over 90% Ni patterns have become single crystal

89

Structure of Graphene

• 2-dimensional Dirac-Fermions– In plane: honey comb structure

ith diff t t A d Bwith different atoms A and B– Out of plane: Van de Waals force

• Zero band-gap

Jason Woo IWSG2009

• Linear E-k relationship

Physical Properties of Grapheney• Semi-metal with zero band-gap and large

number of carriers even in ‘intrinsic’number of carriers even in intrinsic .

• High mobility in the plane ( ~15,000cm2/Vs at room temperature )p )

• Nearly ballistic transport in μm scale ( velocity ~108cm/s )

• 2D structure more compatible with current MOSFET process technology.

---- Graphene has great potential to be used as a channel material in MOSFET devices.

Jason Woo IWSG2009

Carrier Densities in Monolayer Graphene• Linear E-k relationship

– E = ћνF·|k|, ћ is reduced Planck constant, F | |, ,νF is Fermi velocity ~ 1x106m/s

• Carrier Densities per unit area in monolayer graphene

5

6

7

cm-2

)

electron densityhole density

,1)(2 0

/)(2 += ∫

+∞

−+ kTEEF

vse e

dggnFcξ

ξξνπ h

2

3

4

5

,nh

(x10

12 y

,1)(2 0

/)(2 += ∫

∞+

+− kTEEF

vsh e

dggnFvξ

ξξνπ h

ni =1011cm-2

• Intrinsic Carrier Density -0.2 -0.1 0 0.1 0.2 0.30

1

2

E E (V)

n e ,

-0.3

2,2 == vs gg

Jason Woo IWSG2009

– ni ~ 1011/cm2-1012/cm2 EF-Ec,v (V)

Metal-Oxide-Graphene Capacitor Structure

VG

0 7

0.8

VG

Metal Oxide

0.6

0.7

/Cox

Graphene

SiO

0.4

0.5Cto

t/SiO2

-1 -0.5 0 0.5 1

0.

V (V)

0.3• monolayer graphene ~ 3.37Å• gate oxide: tox=2nm• Φ 0

Jason Woo IWSG2009

VG (V)• Φmetal-graphene =0

Graphene Field-effect Transistors with Metal Source and Drain - SimulationDrain Simulation

S DG Hole dominates Electron dominates

n+Metal

S D

n+Metal

GrapheneMetal Metal

G

10-1

101

Total Current

m)

Hole dominates Electron dominates

p-SiSiO2p-SiSiO2

p

10-3

10

Electron Current Hole Current(mA

/μm

2

10-7

10-5I DS• tgraphene ~ 3.37Å

• gate oxide: tox=2nm• Φmetal-graphene =0

• Ambipolar conduction: IDS = Ie+IhI /I 45 f V 1V d V 0V

-1.0 -0.5 0.0 0.5 1.010 7

VGS (V)

Jason Woo IWSG2009

• Ion/Ioff ~ 45 for VGS=1V and VGS=0V

Issues of Graphene Field-effect Transistors

Choose different gate workfunction for V tuning

Top-gate dielectric deposition:-- Function layer needed

Cause transport degradation

GateDielectricSource Drain

workfunction for VTH tuning -- Cause transport degradation in graphene

DielectricBottom dielectric

Si substrate

Source DrainGraphene

Interaction between graphene and bottom dielectric

t t d d tiSeries resistance

Contact resistance-- cause transport degradation

Add to parasitic resistances and degrade the conduction

Trap states in graphene consume

Jason Woo IWSG2009

degrade the conduction charges but not conductive

Effect of Parasitic Resistance and Capacitance on Current

scc

GcsGc

DD RQ

WQLVR

RVRVI

⋅=

+= .resistance parasitic is charge, conductive is ,)(,

)( μ

d f

oxgra

G

c

G

c

D

DsD

G

D

CCCCC

VQ

VQ

VIRV

LW

VI

++=

∂∂

∂∂

⋅−

⋅=∂∂ 2

,)(μ

defgraox

gra

D

DsDDox

defgraoxGGDG

CCCC

VIRVVC

LW

CCCVVVLV

++⋅

−⋅=

++∂∂∂

2)(μ

Ideal expression

Effect of parasitic resistance

Effect of quantum capacitance of graphene and defect capacitance.

Jason Woo IWSG2009

Effect of Parasitic Resistance on Current

0.25 Ideal case, on/off ~ 68R 50Ω / ff 30 Assume:

0.15

0.20

A/μ

m)

Rs=50Ω, on/off ~ 30Rs=100Ω, on/off ~ 20Rs=200Ω, on/off ~ 12

V 0 01V

Assume:W/L=1;μ=15,000cm2/Vstox=2nm

0 05

0.10

0.15

I DS

(mA VDS=0.01V tox 2nm

VDS=10mV

0 0.2 0.4 0.6 0.8 10

0.05

VGS (V)

• Reduce IDS: Rs=50Ω, IDS @VGS=1V decrease ~57%

GS ( )

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• Reduce gm: change the shape of IDS-VGS

• Reduce Ion/Ioff: Rs=50Ω, on/off ratio decrease >50%

Back-gated Graphene Field-effect Transistors

• Highly resistive silicon substrate• Thermally grown SiO2 or ALD high-k materials asThermally grown SiO2 or ALD high k materials as

back-gate dielectric• Spin coat chemical synthesized graphene• E-beam evaporated 2nm Cr and 50nm Au as p

source/drain contactsa.

Dielectric

Cr/Au Cr/AuGraphene Cr/Au Cr/Au

Graphene

Si

Al2O3

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Evaporated SiO2 on Exfoliated Graphene

• 20nm SiO2 deposited together with gate metals using e-beam

ti d lift ffevaporation and lift-off process• Current degraded (~30%) after

top-gate stack deposition

Jason Woo IWSG2009

M. C. Lemme, etc. Solid-State Elec. 2008

ALD Al2O3 on Graphene2 3

• Defect-free pristine grapheneDefect free pristine graphene – no dangling bonds or functional groups to

assist oxide depositionassist oxide deposition• Al2O3 using functional group

Non interacting layer between graphene and– Non-interacting layer between graphene and Al2O3

A layer catalytically suitable for ALD Al O– A layer catalytically suitable for ALD Al2O3formation

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ALD Al2O3 using O3 as Function Layer

(a) HOPG surface treated by ozone pretreatment. (b) ALD Al2O3 surface on(a) HOPG surface treated by ozone pretreatment. (b) ALD Al2O3 surface on ozone-treated HOPG. (c) TEM image of cross-section after Al2O3 deposition.

• Fresh HOPG sample• Pre-treated by ozone, oxygen atoms absorbed on the surface• ALD Al2O3 using TMA+O3

Bongki Lee et al Appl Phys Lett (2008)

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Bongki Lee, et al. Appl. Phys. Lett. (2008)

ALD Al2O3 using NO2 as Function Layer

• First applied on single wall carbon nanotubes• NO2 attracted on carbon surface through physical

adsorptionadsorption• Aluminum centers of TMA attracted to oxygen end of

NO2• Further deposition with TMA+H2O

Jason Woo IWSG2009

Further deposition with TMA+H2ODemon B. Farmer, et al, Nano. Lett. (2006)J. R. Williams, et al. Science (2007)

ALD Al2O3 processALD Al2O3 process • Al[CH3]3 (trimethylaluminum) and H2O precursors• Physisorption of NO2• 50 cycles of the ALD process

aphe

ne

aphe

ne

SiO 2gr

a

SiO 2gr

a

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ALD Al2O3 using Evaporated Al as Function Layer

Graphene, covered by Al2O3

• E-beam evaporate 1~2nm Al on graphene• Al being oxidized in ambient before ALDg• ALD Al2O3 deposited on oxidized Al

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Seyoung Kim, etc. Appl. Phys. Lett. 2009

Graphene FETs with Al2O3 Dielectrics2 3

Jason Woo IWSG2009

IBM, IEDM 2008

Ambipolar Conduction of Graphene

Electron current1.2

1.6

m)Simulation of Graphene FET with

t l t t

1.2

1.6

m)

Hole dominates

Electron dominates0.4

0.8

I D(m

A/μmetal contacts

0 4

0.8

D(m

A/μ

m Electron dominates

-1.0 -0.5 0.0 0.5 1.00.0

VG (V)

-1.0 -0.5 0.0 0.5 1.00.0

0.4I D

V (V) A/μ

m) Hole current

1.2

1.6

VG (V)I D

(mA

0.4

0.8

The sum of electron and hole current is ambipolar.

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VG (V)-1.0 -0.5 0.0 0.5 1.0

0.0Electron (or hole) current only is unipolar.

Schottky Tunneling Structure Applied in Graphene FETs

• Employ Schottky junctions at S DG

p y y jsource/drain– to suppress ambipolar

conduction

n+Metal n+Metal

Graphenen+-Sin+-Si

– increase Ion/Ioff

• Schottky junction at source:– Graphene is semi-metal ⇒

p-SiSiO2p-SiSiO2

Φ =0 6eVE Graphene is semi metal ⇒band-bending near the junction ⇒ always electrons tunneling through the barrier

EC EC=EV

ΦB =0.6eVEFn

through the barrier• Schottky junction at drain:

– n+ drain supplies only few holes ⇒ small I

EVVDS =0.01V

Sili S G h Ch l

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⇒ small IhSilicon Source Graphene Channel

Graphene FETs with Schottky Tunneling Source/Drain -ExperimentalExperimental

• LPCVD Polysilicon on insulated surface• Etch Polysilicon to form source/draintc o ys co to o sou ce/d a• Spin coat chemical synthesized graphene• Top-gate dielectric deposition• Etch dielectric in source/drain area and e-beamEtch dielectric in source/drain area and e beam

evaporate 500nm Al contacts on Polysilicon• E-beam evaporate 500nm Al as gate

Al

SiOPoly-Si Poly-SiGraphene

AlAlDielectric Poly Poly

G hSiO2

Si

Graphene

Al O

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Al2O3

ALD Al2O3 with Evaporated Al on CVD Graphene

• CVD graphene transferred to SiO2 substrateE t 2 Al i b ti• Evaporate 2nm Al using e-beam evaporation

• Immediately transfer to ALD machine• ALD Al O using TMA + H O• ALD Al2O3 using TMA + H2O

SiO2Graphene

SiO2Graphene Oxidized Al

ALD Al2O3

Si Si

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AFM Images of Al2O3 on CVD Graphene

~3.05nma) CVD Graphene on SiO2

SiO2

Before Al2O3 deposition

2.05μm

Graphene

~3.05nmb) 2nm evaporated Al on surface

2.05μm

SiO2

After Al2O3 deposition

μ

Graphene~3.05nm

c) 8nm ALD Al2O3 on top of Al

Jason Woo IWSG2009

Summaryy• Potential CVD Graphene Synthesis• Graphene Proporties – Inteface Issues• Graphene MOSFET Processes

− Graphene Channel FET Structures − Graphene FETs Processing

Jason Woo IWSG2009

Conclusion• New Device Structures Exploiting Physical• New Device Structures Exploiting Physical

Mechanisms Made Feasible by Nanometer di i A hi ULPEdimensions to Achieve ULPE

• Exploiting ΔEG not just High mobilities ---p g G j gBandgap Engineering

• Tunnel Source Transistors Promising• Tunnel-Source Transistors Promising• What about other junctions?

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Novel MOSFET-Like Transistor Structures - NNIN · 2019. 12. 19. · MOSFET F ll S liMOSFETs Follow...

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