Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is...
5
Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share source/drains. Transistors in parallel do not share source/drains. If layout was available, actual capacitances would be extracted from layout. Three-input Nand Gate
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Transcript of Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is...
![Page 1: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.](https://reader036.fdocuments.net/reader036/viewer/2022082517/56649f225503460f94c3a3a5/html5/thumbnails/1.jpg)
Notes on Elmore Delay Calculations for Gate
Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share source/drains.Transistors in parallel do not share source/drains.
If layout was available, actual capacitances would be extracted from layout.
Three-input Nand Gate
![Page 2: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.](https://reader036.fdocuments.net/reader036/viewer/2022082517/56649f225503460f94c3a3a5/html5/thumbnails/2.jpg)
Gate Delay: 3-input NAND Driving 4X Inverter
![Page 3: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.](https://reader036.fdocuments.net/reader036/viewer/2022082517/56649f225503460f94c3a3a5/html5/thumbnails/3.jpg)
Gate Delay: Worst case TPHL (fall time), TPLH (rise time)
TPHL
TPLH
![Page 4: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.](https://reader036.fdocuments.net/reader036/viewer/2022082517/56649f225503460f94c3a3a5/html5/thumbnails/4.jpg)
Gate Delay: Best case TPHL (fall time), TPLH (rise time)
Best Case TPLH = R/3*(9C+12C) = R/3 * 21C = 7RC
Best Case TPHL = Worst Case TPHL because all transistors in series.
![Page 5: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.](https://reader036.fdocuments.net/reader036/viewer/2022082517/56649f225503460f94c3a3a5/html5/thumbnails/5.jpg)
Compute Elmore Delay for the following gate, best/worst TPLH/TPHL