Nortel Networks Institute University of Waterloo

CMOS Design and Reliability GroupDepartment of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

1

Nortel Networks InstituteUniversity of Waterloo

Embedded SRAM Design Challenges for Nano-metric

Technologies

Manoj Sachdev

Electrical and Computer Engineering

[email protected]


3

Talk Outline Group Introduction Motivation SRAM Basics Low Power Techniques Data Stability Soft Errors Conclusions


4

Group Introduction

6 PhD, 3 masters, 2 PDFs Applied, industrially

driven research Generous funding levels

Core strengths in circuit design, testing, quality and reliability

http://www.ece.uwaterloo.ca/~cdr


5

Group: Low Power Research

Driven by low power signal processing & bio-implantable applications

Research focus Active power reduction, clocking

strategies Dynamic voltage scaling

architecture for portable app. Leakage power reduction Investigation of RBB effectiveness

with scaling


6

Group: High Performance Circuits

Driven by high speed arithmetic circuits (Adders, registers files, ALU), and CDRs

Research focus Building timing diagnostics into

multi-GHz ALUs Leakage & active power reduction Clock de-skewing Thermal issues in high

performance circuits


7

Group: Memory Research

Driven by embedded SRAMs and CAMs

Research Focus SRAM cell stability, circuit techniques

for detection Low power SRAM architectures Sense amplifiers Soft error robust SRAM and flip-flop

design Leakage reduction, matchline sensing

tech., high speed PE design, and test issues in CAMs

32kb SER SRAM Array

32kb 4T SRAM Array

32kb ECC Protected

SRAM Array


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Talk Outline Group Introduction Motivation SRAM Basics Low Power Architectures Data Stability Soft Errors Conclusions


9

Why SRAM? SRAM occupies majority of SoC die area

Increasing transistor count Contributes to leakage and active power Limits SoC yield, testability & reliability

65nm Dual Core Xeon die


10

Nano-metric Design Hurdles Increased process variability

Wider variations in Ileak, Ion, delay etc. due to intra and inter die variations in VTH, Leff, Weff

Source: Magma Design Automation Source: IBM Research


11

Nano-metric SRAM Design Challenges

Millions of leaking transistors Lower battery life

Process variation Poorer data stability Data retention faults

Smaller transistors Increased soft error

rate

6T cell Nominal Vdd

Pilo et al., JSSC, p. 813, Apr. 2007


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13

SRAM Architecture

Row

add

ress

dec

oder

Column address decoder

Control

2nx2m SRAM cells

A0

A1

An-1

An

An+m-1

2m

2n

2m

2n

BLB0 BL0 BLB2m

-1

WL2n

-1

WL0

Data bus

Data bus

Sense amplifier

Tri-state buffer

Data-outData-in

CS

R/W

WL

BLB BL

BL2m

-1

Pre-charge circuit


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SRAM Cell Cell design objectives

Non destructive read Wdriver = (1.5 ~ 3)Waccess

cell ratio Can be written into

k’n(W/L)access = (2~3)k’p(W/L)load

Design tradeoffs Area, speed, power = f (cell ratio) SNM = f (cell ratio) area, speed, power

Effect of Scaling Supply voltage scaling SNM Process spread cell asymmetry SNM

BL BLBWL

node Bnode AQ1 Q2

Q4Q3

Q5 Q6


15

SRAM Static Noise Margin

Seevink (JSSC ’87)D

D

D

D

0

y

x

v

u

450

D2

1SNM

Vn

Vn

1 01 1

1 1

Q1 Q2Q3 Q4

Q5Q6

+ --+

BLB BLWL

(off) (sat)

(off)

Vn

_+

Vn

_+


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SRAM SNM: Read Access

Worst case SNM – in read-accessed mode Logic “zero” is degraded by

an access transistor

1 0+1 1

1 1

Q1 Q2Q3 Q4

Q5Q6

BLB BLWL

(off) (sat)

(off)

1 0+

Q1 Q2

Q5Q4

(sat)

SNM

0 Vdata_1

Vdata_2 QuiescentRead-accessed

SRAM cell VTC

SNM

Simulated VTCs,CMOS18

0+0


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18

Power Struggle: Leakage

Source: IBM

Tj = 25°C


19

Sub-130nm Scaling Trends

Technology generation (nm)

0.01

0.1

1

10

40 70 100 1300

0.4

0.8

1.2

High VTH

Low VTH

ION/IOFF ratio degradation: ~26x

Berkeley Predictive Tech. Models

No

rmal

ized

th

resh

old

vo

ltag

e

No

rmal

ized

IO

N/I

OF

F

(n-M

OS

tra

nsi

sto

r)

VTH scaled for performance, ION (VDD-VTH)

IOFF/ µm ↑3-5x/generation: result ION/IOFF degradation


20

Transistor Leakage Current Model

Threshold voltage impact DIBL impact

Body bias impact 1 when VDS = VDD

VGS = 0 when transistor is off


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Leakage Control: ION-IOFF Tradeoffs

RBB, non-min. Le “steepest” gradient in ION-IOFF plane

0

0.3

0.6

0.9

1.2

0.50.60.70.80.911.1

Normalized ION

No

rmal

ized

I OFF

stack effect

VDD scaling

70nm, 1100C, typical cornerref. pt. (no leakage ctrl.)

RBB

non-min. Le

4.5x

-12%

Max. ION degradation

Source – Chatterjee, Sachdev et. al, VLSI Sym. 03


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Row based Low-power SRAM Architectures

Kanda & Sakurai (JSSC’04)

Saves Write Power Turn-off the SLC switch

before write Limited swing on BL

For read Turn-on the SLC switch

to drive the BL


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Row based Architectures - Issues Unrealistic approach for multi-word/row

case Write operation would be destructive to all cells in

one row Higher power in read operation

Kanda et. al., JSSC, p.927, June 2004


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Column Based Low-power SRAM Architecture

Four distinct operational modes1. Retention 2. Read 3. Accessed Retention 4. Write

Desirable features Low-leakage Low-write power

Higher write margin

Non-selected words do not discharge BLs Lower read power

Minor speed trade-off

Sharifkhani & Sachdev, TVLSI, p. 196, Feb. 2007


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Retention Mode Array is in hibernation

VH – VL = 0.4V

No multiple VTs! Body effect minimizes

leakage Potential issue: data

stability weak drive transistors

BL

BL

WL

VH

SVG(Nominal voltage:VL)

WL

VSS

VSS

VDD

VSS

VSS

VDD

AB

M1

M4 M3

M5

M6M2

VH

VHVH

VH

VSSVSS

VL

VL


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Read Mode Multiple words/row Only selected word enters

this mode SVG becomes VSS bitline discharges via access &

driver transistors

Good data stability voltage across cell ≈ VH

VB-VA > VH-VL


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Accessed Retention Mode Non-selected words

(BLs) on selected row enters this mode high VWL no SVG variation no bitline discharge

Minimum access leakage

Issue: data stability VWL= VH+Vtha-VΔ VΔ> 200mV recovery after access


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Write Mode Low BL voltage swing

VWR Sufficiently below VH-VΔ

VWR= VL BL swing, VBL ≈ 400 mV

Low power consumption Pwrite ∝ VH. VBL

no SVG variation


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SVGND Architecture

Seg

men

tS

egm

ent

BLBL

Seg

men

tS

egm

ent

BLBL

Seg

men

tS

egm

ent

BLBL

SS0

SS1

Seg

men

t

Seg

men

t

Seg

men

t

SSi

Pos

t D

ecod

er

Pre

-dec

ode

r 1

Pre

-dec

oder

2

Pos

t D

ecod

erP

ost

Dec

ode

r

Row Address

Row decoder

Column Decoder

SA SA

Column Address READ

M

CV

GC

VG

CV

G

CV

G

CV

G

SV

G

SV

G

SV

G

SV

G

SV

G

SV

G

SV

GS

VG

SV

G

CV

G

CV

GC

VG

CV

G

SA

Col

um

n

De

cod

er

Col

um

n V

irtu

al

Gro

und

(CV

G)

Seg

me

nt 0

Se

gm

ent

1S

egm

ent

M

Se

gm

ent

Sel

ect

0 (S

S0)

SS1

SSM

BLBL

WL1

WL2

WLN

VL

VL

VL

VL

READ

SV

GS

VG

SV

GS

VG

0

SV

GM

SW

SW

C

VH

SV

G

VH

SV

G

CELL N

VH

SV

G

VL

CV

G (H

igh

met

al la

yer,

no

min

al

volta

ge V

L e

xcpe

t for

read

op

erat

ion)

SS

Segment VG switch(SW)

CELL 2

CELL 1

WL2

WL1

WLN

BL

BL

WL1

Sharifkhani & Sachdev, TVLSI, p. 196, Feb. 2007


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Column vs Row VGND Column based scheme is superior

Smaller VSS switch: less area overhead Larger drive current during read access Higher operating frequency

VH

SV

G

VH

SV

G

CELL N

VH

SV

G

VL

CV

G (H

igh

met

al la

yer,

no

min

al

volta

ge V

L e

xcpe

t for

read

ope

ratio

n)

SS

Segment VG switch(SW)

CELL 2

CELL 1

WL2

WL1

WLN

BL

BL

Sharifkhani & Sachdev, TVLSI, p. 196, Feb. 2007Kanda et. al., JSSC, p.927, June 2004


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SRAM SNM Sensitivity Analysis

SNM vs. VTH variation

SNM vs. Leff, Weff

SNM vs. VBL, VWL, VDD, T0C

SNM vs. non-catastrophic Rbridge and Rbreak

Multiple parameter variation can lead to much more dramatic decrease in SNM…


33

SNM vs. single VTH variation

Single transistor VTH variation

Typ. case 0% VTH deviation and 0% SNM deviation

Process corners: slowtypfast SNMSNMSNM

VTH_driver – strongest impact on SNM

VTH_access, VTH_load – moderate impact on SNM


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SNM vs. multiple VTH variation

Multiple transistor VTH variation

One VTH is changing, other - biased

SNM degradation may become severe

BL BLBWL

node Bnode AQ1 Q2

Q4Q3

Q5 Q6


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SNM vs. VDD_CELL

1

2

3

0 1.8

1.8

Vdata_1

Vda

ta_2

VDD_WEAK=1.8VVDD_WEAK=1.5VVDD_WEAK=1.2V

1 - SNMweak2 - SNMmarginal3 - SNMgood

Simulated VTCs,CMOS18

SRAM cell VTCs=f(Vdd_cell)

VTCs of SRAM cell with reduced array supply (WL and BL voltages kept at VDD)


36

How to Test Stability Faults??

DRF

Stability faults

Data Retention Faults subset of Stability Faults

For high reliability products DRT (Delay Test) alone is not sufficient anymore


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Stability Fault ModelingBLBBL

WL

node A node B

node A node B

Node A to node B resistive bridge Provides negative

feedback Reduces the SNM by

symmetrical reduction of the both inverter gains

Pavlov, Sachdev & Pineda, pp. 1106-1115, ITC 2004


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Stability Fault Modeling Node A to node B

resistive bridge SNM=linear function of

Rnode A-node B from 50k to

500k SNM range: 0%-80%

Worst case SNM Worst case SNM ~15-

30% of typical


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Detection Techniques: Principle

Principle apply stress such

that “good” cells withstand it, whereas “weak” cells flip

@VTEST weak cell will flip, good cell will retain the data

SNMgood

SNMweakVDD

VnodeA VBL

VnodeBVBLB

VMweak

VMgood

VTEST

Zweak

Bgood Bweak

Aweak

Agood

0

Cell dynamics at VTEST:

good cellweak cell

Zgood


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Stability Fault Detection: DFT

Detection Techniques

Passive Active (DFT)

•DRT•LVT•HTT

•WWTM •SDD •WL overdrive •etc.

•PWWTM •Ratio of Iread’s •WL pulsing

Fixed detection threshold

Programmable detection threshold


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Detection: WL pulsing

VBL

VWL_ref

after 11 WL pulses

VWL_CUT

after 12 WL pulsesafter 13 WL pulsesafter 14 WL pulses

int_weakDidnotflip

Flipped © Philips,UofW

Rweak=200k Weak cell flips

for number of WL_ref pulses>12 (red and violet lines)0

_ _read WL ref pwBL

BL

I tV

C

Pavlov, Sachdev & Pineda, pp. 2334-2343, JSSC Oct 06


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43

Soft Error (SE)

B

S D

p substrate

G

n+n+

+_ -

+

-+ -

+ +- -

+ -+- +- +- +

- - -

V+

‘1’ ‘0’ or ‘0’ ‘1’ 1 0 1 0 0 1

Qcoll<Qcrit no error;

Qcoll>Qcrit soft error

Voltage

Time


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Soft Error Sources External

Alpha particles Doubly ionized 4He2+ atom Penetrates 25m in Si, deposits 4-16 fC/m Sources: Pb in solder balls; U, Th in packaging materials

High energy neutrons Comes from sun or inter-galactic rays Deposits 4-16 fC/m through Si recoil Omnipresent, flux increases with elevation

Internal Power/ground line noise substrate noise capacitive coupling

External sources determine soft error rate

in carefully designed systems


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SE Susceptible Systems Earlier, only space-borne and aircraft

electronics was believed to be prone to SE Now, all ground level electronics is vulnerable

Network servers and routers, memories, FPGA, life saving equipment like cardiac defibrillators, etc.


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SE in SRAM

Particle strikes cause bit flip No masking mechanism Two sensitive nodes

Positive feedback aids bit flipping process Critical charge: crit node trip restore restoreQ C V I

contactM1-M2 viadiffusiongate polyM1M2Sensitive

node

Sensitive noderestoreI


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Scaling and SRAM SER

System SER increases with scaling Lower V & C reduces Qcrit; smaller volume reduces

collected charge Bit SER = constant; system SER = ↑ due to increased # of

bits/chip

Low-power techniques further increase SER

R. Baumann, IEEE Design and Test of Computers, pp. 258-266, May-June 2005

P. Dodd, et. al., IEDM’02, pp.333-336.


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SE Mitigation Layout level

Reduction of sensitive area, using extra doping layer (epitaxial layer can help) or SOI etc.

Circuit level Circuit techniques to reduce sensitivity to transients

Architecture level Parity protection (only error detection), Error

Correction Code (ECC), Error Detection and Correction (EDAC) Code

We consider circuit and architecture level techniques as the first one requires process modification


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Circuit Level MitigationVDD

WLWLBLB

BL

R

R

VDD

WLWLBLB

BL

C

VDD

WLWLBLB

BL

R

R

Ccouple

Cypress Semiconductors

Ootsuka et. al., IEDM 1998

P. Roche, et. al., IRPS 2004

T. M. Mnich, et. al., IEEE Trans. Nucl. Sci., p. 4620, 1983


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Effectiveness of Circuit Tech. Higher Qcrit, but not

immune Lower level of confidence

Exhibits significant area penalty

Immune cells require at least 10 transistors 67% more array area Larger WL and BL

capacitance higher power consumption

CK

D

X1 X2 X3 X4

Calin et. al., IEEE Trans. Nucl. Sci., p. 2874, Dec. 1996

Simulation results in 130nm technology


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Architecture Level Mitigation

0

1

0

1

0

0

0

1

WRITE READ

Unprotected

0

1

0

1

0

0

0

1

WRITE READ

Parity-protected

1 0Parity

bitError

Correction bits

0

1

0

1

0

0

0

1

WRITE READ

EDAC/ECC protected

1 0Parity

bit

Error detected

0

1

0

1

0

1

0

1

1

Error corrected

Parity protection (detection only) Error detection and correction (EDAC) code


52

Cost Effective Approach Architecture level techniques

Bit-flip matters only when visible at system level

Minimum area overhead Area requires for correction bits and

logic circuits only Circuit/layout techniques have

overhead for every single bit in the array

Overhead depends on word size Larger the word, smaller the

overhead

Incurs read delay


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An Energy Efficient SE Mitigation Technique for SRAMs

Low-power SRAM with single error correctable double error detectable (SECDED) code

Improves yield in addition to SE mitigation Simulation shows:

Leakage power saving: ~ 12% Area saving: ~ 12%, i.e., almost half a million less

transistors for a 512kb SRAM array A 32kb SRAM macro has been taped out

The scheme will be published once silicon measurement results are available


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SE Mitigation in Flip-flops SE in flip-flops causes

system malfunction 3 high performance

flip-flops have been designed and taped out in 90nm CMOS Number of transistors per

FF is almost half of commonly used DICE FF

Faster and lower power consuming

0.00

0.50

1.00

1.50

2.00

2.50

3.00

DICE D Master-Slave

SER FF-1 SER FF-2

No

rmal

ized

PD

P


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Conclusions Embedded SRAMs affect overall SoC power,

yield, testability and reliability SRAM design challenges as technology

scales Subtle defects, reduced supply voltage,

random doping effects, SER Circuit innovations are necessary to ensure

robust, reliable SRAMs

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