NONVOLATILE PROCESSOR A EXPLORATION FOR ENERGY...

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NONVOLATILE PROCESSORARCHITECTURE EXPLORATION FOR

ENERGY-HARVESTING APPLICATIONS.................................................................................................................................................................................................................

THIS ARTICLE DISCUSSES THE DESIGN OF NONVOLATILE PROCESSORS (NVPS) FOR

BATTERYLESS APPLICATIONS IN THE INTERNET OF THINGS (IOT), IN WHICH AMBIENT

ENERGY-HARVESTING TECHNIQUES PROVIDE THE POWER. ACHIEVING RELIABLE,

CONTINUOUS, FORWARD COMPUTATION WITH AN UNSTABLE, INTERMITTENT POWER

SUPPLY MOTIVATES THE TRANSITION FROM CONVENTIONAL VOLATILE PROCESSORS TO

EMERGING NVPS. THIS ARTICLE PROVIDES A GUIDELINE FOR FUTURE IOT APPLICATIONS,

REVEALING INHERENT FEATURES OF THE ENERGY-HARVESTING NVP DESIGN.

......The continuous advance of nano-scale circuit technology, improvements inenergy-harvesting techniques, and the risingdemand for low-power wearable sensorsassociated with human healthcare signal apromising era of new embedded processorspowered by ambient energy sources. Theintrinsically unstable, low-power, and inter-mittent nature of ambient energy sourcesprevents the direct deployment of conven-tional digital signal processors designedunder stable power assumptions for use inthese emerging applications without the riskof frequent loss of progress caused by powerfailures (see Figure 1). This challenge hasdriven recent efforts to explore nonvolatileprocessor (NVP) designs that are not subjectto loss of progress.

To deal with power instability, researchershave proposed checkpoint techniques to storethe intermediate computation states before

power failures occur, through power detectingtechniques and external nonvolatile memorystorage such as flash and hard disks.1–5 Still,such processors experience reset and rollbackswhen power failures occur. In contrast, anNVP can maintain its intermediate computa-tion states in its on-chip nonvolatile memoryduring power failures and retrieve them whenthe power is recovered, thus achieving moreforward progress. Given a specific task toboth volatile and NVPs under an unstablepower supply, as shown in Figure 2, the NVPcan finish the task more quickly due to elimi-nation of rollbacks.

NVPs are designed for use in energy-har-vested applications that are severely powerconstrained. However, it is interesting andsurprising that design optimization of lower-ing the power a processor consumes, inher-ited from traditional processor design, doesnot guarantee optimized maximum forward

Kaisheng Ma

Xueqing Li

Pennsylvania State University

Shuangchen Li

University of California,

Santa Barbara

Yongpan Liu

Tsinghua University

John (Jack) Sampson

Pennsylvania State University

Yuan Xie

University of California,

Santa Barbara

Vijaykrishnan Narayanan

Pennsylvania State

University

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32 Published by the IEEE Computer Society 0272-1732/15/$31.00�c 2015 IEEE

progress for an NVP powered by intermittentambient energy. Although there are similar-ities to run-to-halt architectures, the rootcauses in batteryless systems have distinct fea-tures. Namely, without energy storage, anypower in excess of what the processor can useto compute is rejected and wasted. Thus, itpays to be greedy in harvesting systems.

To optimize the processor’s forwardprogress, various factors should be consid-ered, including the overhead due to differ-ent backup and recovery operation policies,the ambient energy characteristics, the selec-tion of processor architectures with differentcomplexities, and the type of nonvolatilememory storage. In this article, we addresshow to build an NVP, its design tradeoffs,and how different optimization choices leadto varying performance in typical applica-tions, which could guide energy-harvestingprocessor design explorations.

From volatile to nonvolatile processorsAs Figure 3 shows, a volatile processor

(VP) resets after power interruptions. In con-trast, an NVP with built-in nonvolatile mem-

ory can back up the intermediate state on thechip when a power failure occurs, and restorethe processor state when power comes back.The NVP’s backup and recovery operationsare at the instruction level and transparent toprogrammers and compilers.

Tip mass

Piezo-films

Vibrationsource

Sun

Solar panelsRF transmitter

RF Receiver

+

– Temperaturedifference

Thermoelectricdevice

Typical efficiency: 8~28%;max 100 mW/cm2; 0.50/1.0 Va single Si/a-Si cell.

Higher output voltage, largearea; highly depending on load,vibration amplitude andfrequency. Up to ~ 4 mW/cm2.

Lower power: tens of µW/cm2.Depending on temperaturedifference, area, interfacesmoothness, etc.

A12-bit 250 S/s A/Dconverter in 65-nmCMOS

Wireless transceiver and 16-bit MCU: PIC24F

A glucose sensor

A temperature sensor

A biomedicaltransmitter

A neural/multimedia transmitter

A UWB transceiverA biosensor interface

1 mW0.1 mW10 µW1 µW0.1 µW10 nW1 nW 10 mW0.1 nW

Power

Power consumption of recently reported applications2

Typical available ambient energy sources1,2

Friis equation: Pr = Pt Gt Gr (λ/4πd )2

Low power: nW to mW. Highlydepending on source, distance,antenna, obstacle objects, etc.

Figure 1. Ambient energy sources including solar energy, ambient RF energy, vibration energy, and thermal energy. Energy

features for power strength, and related parameters are shown along with state-of-the-art application power levels.

0 10 20 30 40 50 60 70 80 90 100Low

High Com

put

atio

n p

rog

ress

(%

)

Power (above/below threshold)Volatile processorNonvolatile processor

Time (s)

0

20

40

60

80

Inp

ut p

ower

leve

l

Figure 2. Percentage of computation progress of a volatile processor (VP) and

a nonvolatile processor (NVP) under an unstable power condition. Unlike a VP,

an NVP’s on-chip backup mechanisms ensure monotonic forward progress.

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SEPTEMBER/OCTOBER 2015 33

BackupA passive capacitor provides the energy for

backup. Unlike a battery, capacitors have nolifetime limitation of charging and discharg-ing cycles, which reduces the risk of chemicalexposure and provides a lighter weight. Thecapacitor size is a design knob that impactsthe backup strategy and efficiency. Whenthere is no capacitor to provide any guaran-teed backup energy, the backup should occurbefore power loss. Therefore, backup andrecovery at a fine granularity are required (forexample, backup at every cycle). However,the fraction of harvested energy used forbackup becomes high. Consequently, it isprudent to use at least a small capacitor.

What to back up. We need to back up thearchitecture state, microarchitecture state, andperformance enhancers. The architecture stateincludes the memory, register files, and pro-gram counter. The memory includes the mainmemory, instruction cache, and data cache. Allthe state elements mentioned earlier shouldeither be designed as nonvolatile memory orbacked up to nonvolatile memory. The archi-tecture state is the minimum state required tobe backed up for an NVP design.

The microarchitecture state includes pipe-line latches, the reorder buffer (RoB), theload/store queue, architectural register files,physical register files, ready table, free list, andmap table. Some states do not require backupbecause they can be recalculated. For example,architectural register files can be recalculatedusing the physical register and map table.

However, the recalculation leads to extra timeand energy penalties and requires complexarchitectural redesign. Moreover, the more amicroarchitectural state is backed up, the lessinstruction reexecution is required. A bettersolution is dynamically incremental backupof the microarchitecture state, according tothe expected energy received during thebackup period.

The performance enhancers include thebranch history table and branch target buffer.Backing up these prediction tables can improvethe prediction accuracy, because there is noneed to rebuild these tables. The tradeoff liesbetween the energy consumed for morebackup and that saved for future executionwith improved prediction accuracy.

How to back up. We perform a temporalselective backup and data compression beforebackup. For the former method, instead ofbacking up all the data, an alternative methodis the temporal selective backup, which backsup only the changed data. The penalty is aflag bit to indicate if the data has been over-lapped and written. In addition, a complexcontrol logic is required to read the flag bits.

For the compression before backupmethod, data compression could reduce theamount of data needing backup. The penaltyis extra compression circuits. Therefore, wemust consider the tradeoff between compres-sion energy and backup energy.

When to back up. There are two main waysto back up data; periodically and on demand.

Operate Power off

Power off

Time

Restore

off

VP

NVP

Inputpower

Operate Operate

Reset

on on

Backup

Figure 3. Fine-grained states of VPs and NVPs under unstable power supply. An NVP enters a

backup phase after power failure, during which it uses the energy stored in its energy storage

capacitor to back up the intermediate computation state. When power is available again, the

supporting circuits first make sure that there is sufficient energy stored for the next potential

backup, and only then restore the computation state and resume execution. The VP, in

contrast, merely resets and resumes.

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ALTERNATIVE COMPUTING DESIGNS & TECHNOLOGIES

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34 IEEE MICRO

In the former method, the processor periodi-cally checkpoints the processor state to thenonvolatile part. The more frequent the pro-cessor checkpoints, the fewer the rollbacksneeded after recovery. The extreme scenariois to back up every clock cycle, where no roll-backs are ever needed. Two methods are pro-posed to implement the checkpoint solution:

� Instruction counter is a small counter tocount instruction numbers between twobackup intervals. It can support dynamicinterval settings to adjust the backupintervals to power profiles. Larger inter-vals for backup risk a large rollback pen-alty to reduce wakeup overheads.

� Compiler-assisted flag is a method inwhich the compiler can add one bitto the program counter to indicatethe backup operation. This methodbenefits from simplicity, but differentexecution paths of the instructionsdue to branch instructions need con-sideration. Moreover, the interval isfixed during compilation time, hurt-ing flexibility.

Backup on demand means that the pro-cessor backs up the state only if there is apower failure. This method can significantlyreduce unnecessary backup operations. Thismethod’s overheads include constantly moni-toring the power supply and identifying thetrigger threshold for backup initiation. Theother penalty is that it requires a capacitor tostore energy to ensure successful backupoperation after power failure occurs. Thelarger energy store required increases the sys-tem recovery latency. Before resuming com-putation, the system must first accumulateenough energy to guarantee sufficient energyfor the next backup operation.

Where to back up. The two primary methodsfor where to perform backup are the all-in-parallel method and via a centralized nonvo-latile block. The former method requires dis-tributed nonvolatile storage structures, suchas nonvolatile SRAM4 or nonvolatile flip-flops.5 The nonvolatile flip-flops are all dis-tributed alongside their volatile counterparts,storing architecture and microarchitecturestates and providing high performance andlong duration. The all-in-parallel structure is

fast in backup time, but suffers from systeminstability caused by a larger temporarypower peak. Another penalty is the large areaof distributed nonvolatile units. Because theyare distributed, the peripheral circuit needs tobe duplicated for each part. Hence, a com-promise is to make the all-in-parallel intopart-in-parallel, or use a multistep approachto finish the backup operation.

The centralized nonvolatile block methodcan use various kinds of available nonvolatileblocks, such as spin-torque-transfer RAM,6

phase-change RAM,7 and memristors.8 Inthis structure, the backup operations are car-ried out serially, which reduces the peakpower. However, the structure requires addi-tional interconnections to connect each far-away register and RAM to the nonvolatileblock far away, and it requires a complex con-trol module to generate the address for thebackup data.

RecoveryDepending on the chosen backup policy,

designers must craft a corresponding recoverypolicy that ensures all state is correctly andatomically restored or recomputed. Addition-ally, recovery policies must be robust againstpower failures occurring during the recoveryphase.

On-demand backup. For the on-demandbackup strategy, the processor cannot startrecovery unless guaranteed enough energy forthe next possible backup operation. This leadsto longer wakeup latencies. However, for theperiodic checkpoint solution, recovery canstart immediately when power is regained.

Microarchitecture state. Two kinds of penaltyexist for microarchitecture state recovery. Thefirst is the time and energy penalty forinstruction reexecution due to missing in-struction information. For example, we canback up only the last uncommitted programcounter in the RoB; all the other instructionsin the RoB are discarded, even if they havealready been analyzed and assigned resourcesto allocate. The second kind of recovery pen-alty is the microarchitecture state recalcula-tion penalty (for instance, restoring the freelist with the help of the map table, architec-tural register files, and physical register files).

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The tradeoff lies between recomputation andrestoring.

On-demand recovery. The states are not allrecovered from nonvolatile parts as soon aspower resumes. We restore parts of data onlywhen we are going to use them. For example,the register files are not all recovered afterpower resumes. The control module analyzesthe next program counter, finds the registerfiles that are going to be used in this programcounter, and recovers them. This solutionavoids restoring some potentially useless dataand might use the otherwise consumedenergy for more forward progress, but it alsorequires additional control logic.

Normal operationA traditional power-efficient processor

focuses on maximizing the computationsperformed for a given amount of power with-out considering power supply variability. Inan NVP, the goal is to maximize the compu-tations performed considering a varyingpower supply, with little provision to back upthe excess instantaneous power due to theabsence of a battery. There are two mainpower consumption considerations in thedesign of an NVP.

Minimum turn-on power. The processor con-figuration determines the smallest amount ofpower required to run the processor. If theprocessor’s configuration is more complex, theprobability of harnessing more power than theminimum required for turning on the pro-cessor is reduced. In contrast, a less-complexprocessor limits the maximum power that canbe used. Consequently, any power that is har-vested that is greater than the peak power ofthe processor is wasted. Hence, an NVPshould attempt to use as much of the instanta-neous power as possible for maximum for-ward progress.

Power that is not used for computation. Backupand recovery costs, and leakage from boththe NVP chip and the capacitor for tempo-rary energy storage constitute waste, that is,energy that was not used for computation.The tradeoff between capacitor volume andleakage plays an important role in the system.A large capacitor stores more energy but also

suffers from more leakage due to the largerarea. Furthermore, a longer time to accumu-late the voltage could also lead to more leak-age. A small capacitor provides low leakagebut increases the potential that the capacitoris full, limiting the ability to store any excesspower not used by the processor.

Figure 4 shows the simulation results ofsome of the tradeoffs associated with the dif-ferent power consumption aspects discussed.

� The VP always resets and experiencesrollbacks to the beginning of executionunder power interruption. The VPcannot finish tasks longer than thelength of uninterrupted power failures.

� The NVP processors all make forwardprogress at different rates determined bytheir turn-on power requirements andthe amount of instantaneous power thatcan be put to use for computations.

� Although the out-of-order (OoO)processor seems to be a nonintuitivechoice for low-power scenarios, despitethe low fraction of turn-on time, theOoO configuration makes the best useof the available instantaneous power toachieve maximum forward progressfor this specific power trace.

Mapping from architecture to applicationand energy profiles

Most of the applications that are expectedto run on an energy-harvesting platform haveeither hard or soft real-time requirements.Quality of service (QoS) is thus an appropri-ate metric to gauge the possibility of practicaldeployment. When these systems run on har-vested ambient energy, the unreliable natureof the input source can degrade the QoS.QoS serves as a standard and target for map-ping from architectures to energy profiles.

Previous works have proposed many non-volatile architectures with different complexitylevels.3 Because many energy sources are avail-able in an ambient environment, dependingon the application requirement for QoS, wecan apply different kinds of architectures todifferent energy sources to satisfy the applica-tion’s QoS as much as possible.

We consider several traditional features toevaluate the input power profiles, including

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36 IEEE MICRO

average power, power variation, and powergranularity. We define the power variation asthe ratio between the maximum and mini-mum power income. The power granularitydescribes how long the power can exceed cer-tain thresholds, and the times for power out-ages. We use these three parameters toevaluate the features of power sources, and wemap architectures to specific power sources tosatisfy the QoS requirement.

The architectures we consider are the non-pipelined (NP), n-stage pipeline (NSP), andOoO design points. The NP architecturerequires a low start-up voltage threshold, andthe backup strategies are relatively simple andstraightforward, which requires little energy.The NSP architecture requires the lowest volt-age threshold, but it can run faster (at higherclock frequency) than NP. The additional

complexity of NSP compared to NP incurs anarea overhead and thus larger leakage power.However, because of the lower VDD requiredby NSP, the front-end circuits’ efficiency canbe higher than NP. From this perspective,NSP fits energy sources with low VDD. NSP’sbackup and recovery strategies are at a rela-tively similar level of energy requirement tothose of NP. The OoO NVP requires thehighest power threshold, limiting its dutycycle relative to NP and NSP for many powerprofiles. When the OoO processor does run,however, it can be much faster than NP andNSP, potentially resulting in better forwardprogress. The backup and recovery energy ofOoO are high, meaning that frequent backupand recovery should be avoided.

Figure 5a shows an example of the simulatedrunning time of a 1-minute electrocardiogram

240

Five-stage: –0.43 dBm (100 uW); OoO: 8.62 dBm (7278.1 uW)

220200180160140120

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dB

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100806040200

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10

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–10

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Volatile: –10 dBm (100 uW); Nonpipelined: –3.5 dBm (446.9 uW)

–5

–20

0 10 20 30 40 50

Time (s)

60

Volatile processor

Nonpipelined nonvolatile processor

Five-stage nonvolatile processor

OoO nonvolatile processor

Figure 4. Forward progress comparison of volatile, nonpipelined, five-stage-pipeline, and out-

of-order NVPs under a TV RF power profile. For this power profile, the OoO processor can

achieve maximum forward progress because of more aggressively using the input energy.

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(ECG) signal processing. The y-axis is therunning time and the x-axis is the architec-ture of the NVP. For ECG data within

1 minute, the NSP, OoO for solar, and OoOfor piezoelectricity can achieve real-time dataprocessing. However, for other energy sourceswith other architectures, the running time islong, meaning that real-time ECG processingis not accessible. We can also see that the TVRF power profile has large variation, andimposes large backup and recovery-time pen-alties. This is because the running timedepends mainly on the above-threshold time,and different power profiles can have differentproportions of what is above and below thethreshold time, resulting in different runningtimes even with the same architecture andtestbench.

Figure 5b illustrates the architecture sug-gestions identified with application complex-ity and power profile features such as averagepower and inverse power variation. The figureshows that the nonpipelined architecture issuitable for low average power with large var-iation, and relatively simple application. TheNSP architecture occupies the middle levelamong design points; it has a large overlapwith the NP architecture because they bothfocus on low threshold design. The OoOarchitecture adapts the most complex applica-tions and performs best with relatively stablepower sources like thermal and solar energysources, with low power variation.

According to different application andpower profile scenarios, we provide the rougharchitecture selection guidelines in Table 1.

I n this article, we have shown that, forenergy-harvesting systems, traditional low-

power design optimizations do not alwaysyield the optimal forward progress for a sys-tem that must contend with high dynamicpower variability and for which backup andrestore costs can consume significant portionsof the total energy expended. Put simply, in adeployment without significant energy stor-age, power austerity is prodigal, and greed isgood if forward progress is the metric ofmerit. NVPs enable more aggressive designsin power-constrained environments and rep-resent a significant step forward on this front.However, our investigations have also shownthat current energy-harvesting systems arebad at being greedy. Key aspects of futurework in the area will be to continuously maxi-mize the fraction of incoming energy that is

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Nonpipelined

Figure 5. Testbench running time simulation results and mapping to

architectures. (a) 1-minute electrocardiogram testbench running time with

different architectures and different power sources. (b) Mapping

architectures to application complexity and power features.

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38 IEEE MICRO

turned into useful computation and todevelop approaches that employ dynamicmicroarchitectural and architectural adapta-tions to successfully capitalize on periods withhigh incoming power. MICRO

AcknowledgmentsThis work was supported in part by the

Center for Low Energy Systems Technology(LEAST), sponsored by MARCO and DARPA,Shannon Lab Huawei Technologies, High-TechResearch and Development (863) Programunder contract 2013AA01320, the Importationand Development of High-Caliber TalentsProject of Beijing Municipal Institutionsunder contract YETP0102, and by theNSF awards 1160483 (ASSIST), 1205618,1213052, 1461698, and 1500848.

....................................................................References1. S. Kim et al., “Ambient RF Energy-Harvesting

Technologies for Self-Sustainable Standalone

Wireless Sensor Platforms,” Proc. IEEE, vol.

102, no. 11, 2014, pp. 1649–1666.

2. X.Li et al., “RF-Powered Systems Using Steep-

Slope Devices,” Proc. IEEE 12th Int’l New Cir-

cuitsandSystemsConf., 2014,pp.73–76.

3. K. Ma et al., “Architecture Exploration for

Ambient Energy Harvesting Nonvolatile Pro-

cessors,” Proc. Int’l Symp. High-Perform-

ance Computer Architecture, 2015, pp.

526–537.

4. T. Miwa et al., “NV-SRAM: A Nonvolatile

SRAM with Backup Ferroelectric Capaci-

tors,” IEEE J. Solid-State Circuits, vol. 36,

no. 3, 2001, pp. 522–527.

5. Y. Wang et al., “A 3us Wake-up Time Non-

volatile Processor Based on Ferroelectric

Flip-Flops,” Proc. 4th European Solid-State

Circuits Conf., 2012, pp. 149–152.

6. H. Noguchi et al., “7.5 A 3.3 ns-Access-

Time 71.2lW/MHz 1Mb Embedded STT-

MRAM Using Physically Eliminated Read-

Disturb Scheme and Normally-Off Memory

Architecture,” Proc. IEEE Int’l Solid-State


7. G. De Sandre et al., “A 90nm 4Mb

Embedded Phase-Change Memory with 1.2

V 12ns Read Access Time and 1MB/s Write

Throughput,” Proc. IEEE Int’l Solid-State


8. M.-F. Chang et al., “19.4 Embedded 1Mb

ReRAM in 28nm CMOS with 0.27-to-1V

Read Using Swing-Sample-and-Couple Sense

Amplifier and Self-Boost-Write-Termination

Scheme,” Proc. IEEE Int’l Solid-State Circuits

Conf., 2014, pp. 332–333.

Kaisheng Ma is a PhD student in theDepartment of Computer Science and

Table 1. NVP architecture selection suggestions for different power sources and scenarios.

Power sources and scenarios Power features Architecture

Solar power inside a room Low power income level with infrequent power boost Nonpipelined (NP)

Solar power while riding a bike in the forest Low power income level with frequent power boost Out of order (OoO)

Solar power on cloudy days or in a shadow Intermediate power NP or n-stage pipeline (NSP)

TV RF fixed antenna Extremely low power with little variation NSP

TV RF antenna worn by human Extremely low power with large variation NP

Office Wi-Fi RF with little movement Extremely low power with little variation NSP

Office Wi-Fi RF with frequent movement Extremely low power with large variation NP

Home Wi-Fi RF Extremely low power with very large variation NP

Thermal band fixed on arms, little movement Relatively stable intermediate power OoO

Thermal band fixed on legs, running Periodical wave with almost no power failure,

but with some variation

NSP or OoO

Piezo device fixed on a bike Near stable power but with frequent short-time

power outage

OoO

Piezo device under the shoes or fixed on

knees and the leg

Periodical power boost with large power outage OoO

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Engineering at Pennsylvania State University.His research interests include energy-harvest-ing architectures, machine learning, and neu-romorphic computing. Ma has an ME inmicroelectronics from Peking University.Contact him at [email protected].

Xueqing Li is a postdoctoral researcher inthe Department of Computer Science andEngineering at Pennsylvania State Univer-sity. His research interests include wirelesstransceivers, high-performance data con-verters, self-powered nonvolatile systems,and circuits and systems using emergingdevices. Li has a PhD in electronics engi-neering from Tsinghua University. He is amember of IEEE. Contact him at [email protected].

Shuangchen Li is a PhD student in theDepartment of Electrical and ComputerEngineering at the University of California,Santa Barbara. His research focuses on com-puter architecture, especially emerging non-volatile memory. Li has an MS in electronicengineering from Tsinghua University. Con-tact him at [email protected].

Yongpan Liu is an associate professor in theDepartment of Electronic Engineering atTsinghua University. His research interests

include nonvolatile computation, low-powerVLSI design, emerging circuits and systems,and design automation. Liu has a PhD inelectronics engineering from Tsinghua Uni-versity. He is a member of IEEE; the ACM;and the Institute of Electronics, Information,and Communication Engineers. Contact himat [email protected].

John (Jack) Sampson is an assistant profes-sor in the Department of Computer Scienceand Engineering at Pennsylvania State Uni-versity. His research interests include energy-efficient computing, architectural adaptationsto exploit emerging technologies, and miti-gating the impact of dark silicon. Sampsonhas a PhD in computer engineering from theUniversity of California, San Diego. He is amember of IEEE. Contact him at [email protected].

Yuan Xie is a professor in the Departmentof Electrical and Computer Engineering atthe University of California, Santa Barbara.His research interests include computerarchitecture, EDA, and VLSI design. Xiehas a PhD in electrical engineering fromPrinceton University. He is a fellow ofIEEE. Contact him at [email protected].

Vijaykrishnan Narayanan is a Distin-guished Professor of Computer Science andEngineering and Electrical Engineering atPennsylvania State University. His researchfocuses on energy-efficient computing. Nar-ayanan has a PhD in computer science fromthe University of South Florida. He is a fel-low of IEEE and the ACM. Contact him [email protected].

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40 IEEE MICRO

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