noc architecture design

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    CONTENTS  Objective.  Introduction.  Block Diagram.  Design Aspects o NoC.

     !outing algorit"ms. #lo$ control.  Error control sc"eme.

     BiNoC !outer Arc"itecture.  C"annel direction control.

     %ork done and $orks to be done.  Simulation results.  Design !e&uirements.  Conclusion.  !eerences

    1

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    Objectives To develop a prototype of bidirectional NoC

    communication having dynamically selfrecongurable channels.

     To increase the noise toleration capability ofthe system using a hybrid scheme of error

    correction and retransmission.

    2

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    INTO!"CTION#oC $ Integrating all the components of an

    electronic system in a single chip.

    Inter processor communication ' An important design

    issue.

    Traditional on'c"ip communication met"ods'global

     bus( )oint to )oint *inks.

    NoC% Communication &ac'bone In #oC.

    (

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    &asic Tiled NoC)rchitecture

    *

    ADVANTAGES

    Commonly used NoC

    architecture

    #imple and scalable

    +igh performance

    DISADVANTAGES

    No e,ective resource

    utili-ation.

    ess band/idth utili-ation.

    Channel Over0o/ occurs

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    &OC !I))3

    4

    3*3 grid structure of bidirectional NoC

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    !esign aspects of NoC Topology.

    outing.

    5lo/ Control.Noise toleration.

    6

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     Topology

    7

    2D mesh topology

    Commonly UsedTopologies

    •2! mesh topology• Torus topology•ing topology

    2D mesh topology

    Advantages

    •#implicity.

    •+igh degree of scalability.

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    outing )lgorithms

    !etermines The 8ath #elected &y a 8ac'et Toeach Its !estination.

    Oblivious routing and adaptive routing.

    Oblivious outing 8ath "ni9uely !ened &y #ource )nd !estination.

    )daptive outing

    8ath chosen based on net/or' conditions. 8ath might be changed /ithin net/or' to avoid

    congestion.

    :

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    Oblivious outingAlgo!ithmsNo Information )bout Conditions Of The

    Net/or'; i'e Tra?ample !imension Order outing@

    !imension Order outing=!O@% !etermines The

    !irection Of 8ac'et !uring >very #tage Of

    outing

    A

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    B routing algorithm

    1D

    •  Type Of !imension Order

    outing.

    •  outes 8ac'ets 5irst in B

    =+ori-ontal !irection@

     Then In =vertical

    !irection@.

    • B outing #uits Eell On

    a Net/or' "sing 3esh

    Or Torus Topology.XY routing

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    5lo/ control

    Net/or' 0o/ control=routing mode@%!etermines +o/ 8ac'ets are Transmittedinside a Net/or'.

     

    outing modes

    #tore%and%5or/ard outing.

    Firtual Cut%Through outing.

    Eormhole outing.

    11

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    "o!mhole outing8ac'ets are !ivided To #mall )nd >9ual #i-ed

    5lits=fow Control Unit @.

    Eormhole 3ode e9uires ess 3emory.

    atency Is ess.

    12

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    5lit structure

    +eader 0it

     Tail 0it

    !ata 0it

    1(

    1D

    LS!S

    !ata 11

    LS!S

    !ata D

    LS!S

    : bit destinationaddress

    : bit #ourceaddress

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    >rror control #cheme

    "sing hamming code $ #ingle error correctiondouble error detection=#>C%!>!@.

    +ybrid #cheme% Combination Of >rrorCorrection #cheme )nd etransmission#cheme.

    Increases the noise toleration capabilityNot Ideal.

    #/itch !rops The 8ac'et In Case Of "ncorrectable>rroneous +eader 5lit.

    1*

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    #>C !>! hamming code

    +amming code can be converted to a #>C%

    !>! code by adding one more chec' bit /hich

    is a parity bit.

    Can detect up to t/o bit errors .

    Correction is possible only for 1 bit error.

    14

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     >rror Control 8olicies#/itch%to%#/itch >rror Control 8olicy 5lits are encoded and decoded at each hop.

    )rea overhead $ * encoders; * decoders and >?tended&u,er egisters

    !elay Overhead 8er 5lit % Nma? G =T>ncoder H T!ecoder@;Nma? is the ma?imum number of hops made by a 0it

    >nd%to%>nd >rror control policy .One >ncoder )nd One !ecoder )re Needed To &e

    Connected To The NI =Net/or' Interface@.

    )rea Overhead %One >ncoder; One !ecoder )nd>?tended &u,er egisters.

    )dditional !elay Overhead 8er 5lit # T!.%5lit J T>ncoder H T!ecoder

    16

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    &iNoC O"T>

    )C+IT>CT">

    17

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    Channel !irectioncontrol=C!C@Channel direction $ controlled using t/o nite

    state machines=5#3s@

    +igh priority 5#3 o/ priority 5#3

    +p 5#3 $ (states.

    8 5#3 $ ( states.

    1:

    "nter router channel direction control

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    1A

    $% &S' (% &S'

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    Eor' in progressEor' doneK

    !eveloped a basic 4 port router used in tiled NoCarchitecture.

    !eveloped the channel direction control scheme usingC!C protocol.

     Eor's to be doneK  !evelop a &iNoC router by integrating the C!C protocol

    concept /ith the basic router structure.

    !evelop the bidirectional NoC model by interconnectingthe routers in mesh topology.

    !esign the Noise toleration scheme to increase thereliability of the #ystem

    2D

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    21

    &)#IC NoC O"T> )C+IT>CT"

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    22

    +8 5#3 8 5#3

    8 5#3 +8 5#3

    Output_request

    Output_request

    Output_request

    Output_request

    input_request

    input_request

    input_request

    input_request

    Channel%1

    Channel%2

    Channel_requestChannel_request

    Inte! oute! Channel Di!e)tion

    Cont!ol

    Din#2

    Dout#2#$

    Dout#2#2

    Din#$

    Dout#$#$

    Dout#$#2

    CL%C&

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    #imulation results

    2(

    Simulation 'esult ( )")% buffer 

    Data input to buffer 

    Data %utput from buffer 

    'ead enable signal

    rite enable signaluffer empty signal

    uffer )ull signal

    Data getting stored in inner registers of buffer 

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    #imulation resultK B logic

    2*

    "nput header flit X coordinate of destination address

    Y coordinate of destination address North#outSouth#out

    est#out

    east#out

    local#out

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    #imulation esult K otating priorityarbiter

    24

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    #imulation esultK 4 port basic NoCrouter

    26

    est#in

    local#in North#in+ast#in

    South#in

    est#outlocal#out

    North#out

    +ast#out

    South#out

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    Contd..

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    Input port +eader lit injected,- address o

    destination

    ,- address o local

    router Output port

    %ESTDDDD1111DDDD11

    11D1DDD1DDD1D1/(/0 /(/0 *OCA*

    *OCA*

    1111DDDD1111DD

    DDD1DDD1D1DDD1 1(/0 /(/0 SO2T+

     NO!T+11111111DDDDDD

    DDD1DD1DDDD1D1/(30 /(/0 EAST

    EAST11111111DDDDDD

    DDD1DDDDDDDDD14(40 /(/0 %EST

    SO2T+DDDD1111DDDD11

    11D1DDD1DDDDD14(/0 /(/0 NO!T+

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    #imultaneous multiple re9uest handling inNoC outer

    2:

    est#inlocal#in

    North#in

    +ast#in South#in

    est#outlocal#out

    North#out

    +ast#out

    South#out

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    2A

    Contd,,

    est#inlocal#in

    North#in

    South#in

    est#outlocal#out

    North#out

    +ast#out

    South#out

    east#in

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    (D

    Contd,,

    est#inlocal#in

    North#in

    +ast#in South#in

    est#outlocal#out

    North#out

    +ast#out

    South#out

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    (1

    Input )ort +eader #lit Injected,- Address O

    Destination

    ,- Address O

    *ocal !outer Output )ort

    Order O

    5rant

    %EST11111111DDDDDD

    DDD1DD1DDDD1D1/(30 /(/0 EAST 3

    *OCA*DDDDDDDD111111

    11D1DD1DDDD1D1/(30 /(/0 EAST 6

     NO!T+D1D1D1D1D1D1D1

    D1D1DD1DDDD1D1/(30 /(/0 EAST 1

    EAST1111DDDD1111DD

    DDD1DDD1D1DDD11(/0 /(/0 SO2T+ '

    SO2T+DD11DD11DD11DD

    11DDDD1DDDD1D1/(30 /(/0 EAST /

    Contd,,

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    Channel direction

    Conguration

    (2

    Channel#$-right

    Channel#2-left

    Channel#2 -right Channel#2- left Channel#$-left

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    ContdL

    ((

    Channel#$-rightChannel#$-left

    Channel#2-left

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     TOO# >M"I>!Bilin? I#> design suite 12.1

    3odelsim #> plus 6.2c

    (*

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    Conclusion!esigned a basic ve port NoC router using

    F+! and simulated the results.

     !esigned the C!C scheme for inter routerchannel direction control at run time.

    (4

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    eference

    (6

    1 . C. an; #. +. o; . C. in; . +. +u; and #. P. Chen; Q&iNoCK ) bidirectionalNoCarchitecture /ith dynamic self%recongurable channel;R IEEE Trans. Comput.-AidedDes,vol. (D; No. (; 8p. *21$*(*; 3arch 2D11.

    2 Q!esign and )nalysis of On%Chip outer for Net/or' On ChipR International Pournal of Computer Trends and Technology% Puly to )ug Issue 2D11

    ( ) #urvey of )rchitectural !esign and Implementation Tradeo,s in Net/or' onChip #ystems !an 3arconett University o Caliornia, Davis, CA 95!, U"A .

    * . &enini and . !e 3icheli; QNet/or's on chipsK a ne/ #oC paradigm;R IEEETransa#tions on Computers; vol. (4; no. 1; pp. 7D$7:; 2DD2.

    4 QNet/or's on ChipsK #tructure and !esign 3ethodologiesR +inda/i 8ublishingCorporation

     Pournal of >lectrical and Computer >ngineering; Folume 2D12; )rticle I! 4DA*64

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    Contd..6Q#imulation S #ynthesis of 5ive 8ort outerR #/ati 3alviya =3.Tech. %!igital

    Communication@ )nurag Pais/al =Capgemini Consulting India 8vt. td.; 5ormer+O!%IT; 53#; 3IT# "niversity@.

    7 QNet/or' on Chip outing )lgorithms QT"C# Technical eport No 77A; )ugust2DD6

    : !avide &erto--i; uca &enini,Q>rror Control #chemes for On%ChipCommunication;in'sK The >nergy$eliability Tradeo,R IEEE Trans. Comput.-

     Aided Des. Fol. 2*; No. 6; Pune 2DD4.

    A *>rror Correction Techni9ues on NoC 8rotocol ayersR )hmed aramoun ;

    +aupt%#eminareliable Net/or's%on%Chip in the 3any%Core >ra; "niversity of #tuttgart.

    (7

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     T+)N O"