Nmos Andd Cmos Dynamic Register

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    Review: Sequential Definitions Static versus dynamic storage

    static uses a bistable element with feedback (regeneration) and thus

    preserves its state as long as the power is on

    static is preferred when updates are infrequent (clock gating)

    dynamic stores state on parasitic capacitors so only holds the state

    for a period of time (milliseconds) and requires periodic refresh

    dynamic is usually simpler (fewer transistors), higher speed, lower

    power

    Latch versus flipflop

    latches are level sensitive with two modes: transparent - inputs arepassed to Q and hold - output stable

    fliplflops are edge sensitive that only sample the inputs on a clock

    transition

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    Review: System Timing Constraints

    Combinational

    Logic

    clock

    Outputs

    Next

    State

    Current

    State

    Inputs

    T tc-q + tplogic + tsutcdreg + tcdlogic thold

    T (clock period)

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    NMOS Dynamic Shift Registers

    A shift register can beconstructed by thecombination of transmissiongates and inverters.

    If VI=VDD and 1=VDD, then alogic 1=VDD-VTN would existat VO1.

    The CL charges through MN1.

    As VO1 goes high, VO2 goes low.

    If 2 is high low willtransmitted through MN2 andVO4 would be at logic 1. Thuslogic 1 shiftedfrom input tooutput.

    In shift register the input signal istransmitted, or shifted, from theinput to the output during one clockcycle.

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    NMOS Dynamic Shift Registers at various times

    Suppose VDD=5V and VTN=1V.

    At t=t1 , V1=1=5V, vO2 goes low

    At this time MN2 is still in cutoff (2=0)even though input of MN2 has

    been changed. This implies that

    vO3 and vO4 depend on the

    previous history.

    Similarly at t=t3, 2 is high, and logic 0 at vO2

    is transmitted to vO3, which force vO4 to5V. Thus the input information istransmitted to output during one clockcycle.

    Transparent mode Hold mode

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    NMOS shift register is also dynamic (why?)

    The output charged capacitordoes not remain constant withtime because it is dischargethrough the transmission gatetransistor.

    In order to prevent logicerrors, the clock signal period Tmust be small compared toeffective RC discharge timeconstant.

    For example at t = t2, VO1=4V, 1=0and MN1 is cutoff.VO1will start toto decay and VO2will begin toincrease.

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    CMOS Dynamic Shift Registers

    The operation of the CMOSshift register is similar tothe NMOS register exceptfor the voltage levels.

    For example, whenvI=1=VDD. Then vO1=VDD andvO2=0. when 2 goes high,then vo3 switch to zero,vo4=vDD.

    Thus input signal is shiftedto the output during oneclock cycle.

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    ynam c ransm ss on ga e e ge-triggered registers (cont.)

    T1

    T2

    I1 I2 QQM

    D

    C1 C2

    !clk

    clk

    clk

    !clk

    !clk

    clk

    mastertransparent

    slave hold

    masterhold

    slave transparent

    master slave

    tsu =

    thold =

    tc-q =

    tpd_tx (delay of the TG)

    zero2 tpd_inv + tpd_tx

    The hold time is approximately zero, since the transmission gate is turned off at clock edge.

    Propagation delay


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NMOS-CMOS INTRODUCTION

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Cours ANDD

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