Nithin Assignment Copy
40
VHDL Assignment No 1 1. Design and simulate a 4 input NOR Gate program using dataflow modeling in VHDL. Program: entity norgate4 is port(a,b,c ,d: in bit; y: out bit); end norgate4; architecture data of norgate4 is begin y<= not(a or b or c or d); end data; Wave output : 2. Design and simulate a 4 input NAND Gate program using dataflow modeling in VHDL. Program:
-
Upload
mohammadakram99gmail -
Category
Documents
-
view
248 -
download
3
description
programs
Transcript of Nithin Assignment Copy
VHDL Assignment No 1
1. Design and simulate a 4 input NOR Gate program using dataflow modeling inVHDL.
Program:
entity norgate4 isport(a,b,c ,d: in bit;y: out bit);end norgate4;architecture data of norgate4 isbeginy
