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Transcript of Nios II DPX Software Development, Nios II DPX Datapath · PDF file 2020-06-18 ·...

  • May 2011 Altera Corporation

    NIIDPXHB-SD-2.0

    © 2011 Altera Corporation. Al QUARTUS and STRATIX are All other trademarks and serv www.altera.com/common/le accordance with Altera’s stand without notice. Altera assume service described herein excep version of device specification

    101 Innovation Drive San Jose, CA 95134 www.altera.com

    Section II. Nios II DPX Software Development

    The Nios® II DPX Software Development section of the Nios II DPX Datapath Processor Handbook provides the basic information needed to develop software for the Altera® Nios II DPX MTP. This section describes the Nios II DPX MTP software development environment, the Altera Embedded Design Suite (EDS) tools available to you, and the process for developing software.

    The Nios II DPX Software Development section assumes you have a basic familiarity with embedded processor concepts.

    Familiarity with Altera hardware development tools can give you a deeper understanding of the reasoning behind the Nios II DPX MTP software development environment.

    This section includes the following chapters:

    ■ Chapter 4, Overview of the Nios II DPX MTP

    ■ Chapter 5, Software Programming Model

    ■ Chapter 6, Getting Started with the Graphical User Interface

    ■ Chapter 7, Getting Started from the Command Line

    ■ Chapter 8, Understanding the Nios II DPX Board Support Package

    ■ Chapter 9, Nios II DPX MTP Instruction Set and Application Binary Interface

    ■ Chapter 10, SBT Reference for the Nios II DPX MTP

    Nios II DPX Datapath Processor Handbook

    l rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. ice marks are the property of their respective holders as described at gal.html. Altera warrants performance of its semiconductor products to current specifications in ard warranty, but reserves the right to make changes to any products and services at any time

    s no responsibility or liability arising out of the application or use of any information, product, or t as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest s before relying on any published information and before placing orders for products or services.

    http://www.altera.com/common/legal.html http://www.altera.com http://www.altera.com/literature/hb/nios2dpx/niidpx-handbook.pdf http://www.altera.com/literature/hb/nios2dpx/niidpx-handbook.pdf

  • II–2 Section II: Nios II DPX Software Development

    Nios II DPX Datapath Processor Handbook May 2011 Altera Corporation

  • May 2011 Altera Corporation

    4. Overview of the Nios II DPX MTP

    This chapter provides a high-level overview of how the Nios II DPX MTP fits into the Nios II DPX datapath processor. It outlines the software development environment for the Nios II DPX MTP. This chapter contains the following sections:

    ■ “The MTP in the Context of the Nios II DPX Datapath Processor”

    ■ “Event-Driven Processing” on page 4–1

    ■ “Nios II DPX Multithreading” on page 4–2

    ■ “Dual-Processor Configurations” on page 4–2

    ■ “Nios II DPX Programming Considerations” on page 4–3

    ■ “The Nios II DPX Software Development Environment” on page 4–4

    The MTP in the Context of the Nios II DPX Datapath Processor The Nios II DPX MTP is a dedicated, special-purpose microprocessor embedded in the Nios II DPX datapath processor. The DPX MTP is a submodule in the Nios II DPX core, which includes instruction memory and hardware support for task and thread control, messaging, system analysis and debugging. The Nios II DPX MTP and its environment are optimized for datapath processing tasks, such as packet processing.

    f For additional information about the Nios II DPX MTP and its hardware environment, refer to the Nios II DPX Architecture chapter, in the Nios II DPX Hardware Reference section of the Nios II DPX Datapath Processor Handbook.

    Event-Driven Processing Nios II DPX designs are based on a event-driven processing paradigm. The programming model for the Nios II DPX MTP is different from that of a conventional processor. Generally, to program the Nios II DPX MTP, you do not write a main() function that executes for the lifetime of the application. Instead, main() typically only executes some minimal initialization tasks and returns. The Nios II DPX software consists of short routines, called tasks, that are executed in response to the receipt of a PE message.

    A task is analogous to an interrupt service routine (ISR). However, a task provides better performance than a conventional ISR, because all necessary context information is provided to the processor through the message interface hardware.

    In a Nios II DPX system, processing elements (PEs) are connected to one another through a message interconnect. The Nios II DPX datapath processor is an example of a PE. PEs can also be specialized hardware accelerators or other processors with message interfaces. Each PE is capable of performing one or more tasks. In a typical system, the Nios II DPX datapath processor communicates with a heterogenous collection of several PEs.

    Nios II DPX Datapath Processor Handbook

    www.altera.com/literature/hb/nios2dpx/niidpx-handbook-01.pdf www.altera.com/literature/hb/nios2dpx/niidpx-handbook-01.pdf

  • 4–2 Chapter 4: Overview of the Nios II DPX MTP Nios II DPX Multithreading

    f For information about PEs and Altera event-driven datapath processing, refer to “Event-Driven Methodology” in the Altera Event-Driven Datapath Processing Design Handbook.

    Nios II DPX Multithreading The Nios II DPX MTP is an interleaved multithreaded processor, capable of executing eight threads simultaneously. Each thread can execute a task.

    Each thread has its own register context, enabling threads to execute independently. You can think of the threads as eight identical, separate processors.

    Each thread is independent of the other threads. If a thread stalls, the remaining threads continue to execute as usual. Thread stalls, however, are rare, because of hardware features such as interleaved multithreading and fixed-latency memory masters.

    MTP hardware threads are interchangeable. Software normally need not determine which hardware thread it is running on at any particular time. However, the current thread number can be read from the threadnum control register if necessary.

    1 Because the threads are independent, you must use care with shared resources, just as in any multithreaded programming environment. You must protect shared resources, such as device registers, with a mutual exclusion mechanism, such as semaphores.

    f For detailed information about Nios II DPX multithreading, refer to “Functional Description” in the Nios II DPX Architecture chapter, in the Nios II DPX Hardware Reference section of the Nios II DPX Datapath Processor Handbook.

    Dual-Processor Configurations If your application requires more than eight threads, you can configure the Nios II DPX datapath processor with dual MTP cores. A dual-core Nios II DPX datapath processor functions the same as a single-core processor, except that it supports sixteen simultaneous threads. The two cores have identical memory maps, and run the same software. When a task needs to run, it can run on either MTP core.

    A dual-processor configuration, which providing sixteen threads, uses less memory than two distinct Nios II DPX MTPs, because the two MTPs share instruction memory.

    f For information about instantiating a dual-core Nios II DPX datapath processor, refer to the Instantiating the Nios II DPX Datapath Processor chapter, in the Nios II DPX Hardware Reference section of the Nios II DPX Datapath Processor Handbook.

    Nios II DPX Datapath Processor Handbook May 2011 Altera Corporation

    www.altera.com/literature/hb/nios2dpx/niidpx-handbook-01.pdf www.altera.com/literature/hb/nios2dpx/niidpx-handbook-01.pdf www.altera.com/literature/hb/nios2dpx/niidpx-handbook-01.pdf www.altera.com/literature/hb/nios2dpx/niidpx-handbook-01.pdf http://www.altera.com/literature/hb/nios2dpx/hb_datapath_processing.pdf http://www.altera.com/literature/hb/nios2dpx/hb_datapath_processing.pdf

  • Chapter 4: Overview of the Nios II DPX MTP 4–3 Nios II DPX Programming Considerations

    Nios II DPX Programming Considerations The event-driven paradigm, and the Nios II DPX MTP’s unique architecture and hardware environment, make programming the MTP different from programming a general-purpose processor. Before you start, become familiar with the Altera Event-Driven Datapath Processing Design Handbook, as well as “Functional Description” in the Nios II DPX Architecture chapter, in the Nios II DPX Hardware Reference section of the Nios II DPX Datapath Processor Handbook. This topic provides a detailed description of the Nios II DPX architecture.

    Memory and I/O The Nios II DPX MTP has separate address spaces for instructions and data.

    Instruction memory is an on-chip memory embedded in the Nios II DPX core, ensuring that threads never stall waiting for an instruction.

    The Nios II DPX MTP possesses two kinds of data master interfaces: fixed-latency and variable-latency.

    The fixed-latency data master interfaces provide access to data that requires time-critical access without stalling. The Nios II DPX MTP can use fixed-latency data master interfaces to connect to any memory or peripheral that has zero wait states and a read latency of two.