Xilinx XAPP753 Interfacing Xilinx FPGAs to TI DSP Platforms using
Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next...
Transcript of Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next...
![Page 1: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/1.jpg)
© Copyright 2020 Xilinx
Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP
Cathal McCabe
Xilinx University Program, Xilinx Ireland
18 February 2020
![Page 2: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/2.jpg)
© Copyright 2020 Xilinx
Overview
Requirements for next generation compute systems
The technology conundrum
FPGA technology evolution
Current and next generation Xilinx technologies
![Page 3: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/3.jpg)
© Copyright 2020 Xilinx
What are your requirements for next generation HEPsystems?
Adaptability
Power
Compute density
Performance CostData rates
Machine Learning Cloud scalability
![Page 4: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/4.jpg)
© Copyright 2020 Xilinx
The Technology Conundrum .. And the Need for a New Compute Paradigm
*John Hennessy and David Patterson, Computer Architecture: A Quantitative Approach, 6/e. 2018
![Page 5: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/5.jpg)
© Copyright 2020 Xilinx
FPGA scaling
0
20
40
60
80
100
120
140
160
180
Virtex 7 (28 nm) Virtex Ultrascale (20nm) Virtex Ultrascale+(16nm)
Siz
e (
MB
s)
On-chip Memory
Distributed RAM BRAM
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Virtex 7 (28 nm) Virtex Ultrascale (20nm) Virtex Ultrascale+(16nm)
LU
T c
ou
nt
(M
)
LUTs
0
2
4
6
8
10
12
14
Virtex 7 (28 nm) Virtex Ultrascale (20nm) Virtex Ultrascale+ (16nm)
DS
P c
ou
nt
(K)
DSPs
25
26
27
28
29
30
31
32
33
Virtex 7 (28 nm) Virtex Ultrascale(20nm)
Virtex Ultrascale+(16nm)
28
30.5
32.75
Speed (
Gbps)
Transceiver speed
![Page 6: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/6.jpg)
© Copyright 2020 Xilinx
FPGA scaling - URAM example
25
26
27
28
29
30
31
32
33
Virtex 7 (28 nm) Virtex Ultrascale(20nm)
Virtex Ultrascale+(16nm)
28
30.5
32.75
Speed (
Gbps)
Transceiver speed
0
100
200
300
400
500
600
Virtex 7 (28 nm) Virtex Ultrascale (20nm) Virtex Ultrascale+(16nm)
Siz
e (
MB
s)
On-chip Memory (with URAM)
Distributed RAM BRAM URAM
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Virtex 7 (28 nm) Virtex Ultrascale (20nm) Virtex Ultrascale+(16nm)
LU
T c
ou
nt
(M
)
LUTs
0
2
4
6
8
10
12
14
Virtex 7 (28 nm) Virtex Ultrascale (20nm) Virtex Ultrascale+ (16nm)
DS
P c
ou
nt
(K)
DSPs
![Page 7: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/7.jpg)
© Copyright 2020 Xilinx
FPGA scaling – transceivers example
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Virtex 7 (28 nm) Virtex Ultrascale(20nm)
Virtex Ultrascale+(16nm)
1.4
2.8
4.2
Bandw
idth
(T
bps)
Transceiver bandwidth
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Virtex 7 (28 nm) Virtex Ultrascale (20nm) Virtex Ultrascale+(16nm)
LU
T c
ou
nt
(M
)
LUTs
0
2
4
6
8
10
12
14
Virtex 7 (28 nm) Virtex Ultrascale (20nm) Virtex Ultrascale+ (16nm)
DS
P c
ou
nt
(K)
DSPs
0
100
200
300
400
500
600
Virtex 7 (28 nm) Virtex Ultrascale (20nm) Virtex Ultrascale+(16nm)
Siz
e (
MB
s)
On-chip Memory (with URAM)
Distributed RAM BRAM URAM
![Page 8: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/8.jpg)
© Copyright 2020 Xilinx
Xilinx TransformationS
W P
rog
ram
ma
bilit
y
Device Category
SoCFPGA
MPSoC
RFSoC
ACAP
From Devices to Platforms
![Page 9: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/9.jpg)
© Copyright 2020 Xilinx
Xilinx technologies
![Page 10: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/10.jpg)
© Copyright 2020 Xilinx
ACCESSIBLEDeploy in the cloud or on-premises
Rich set of accelerated Applications
FASTBuilt for high throughput, ultra-low latency
Accelerate compute, networking, storage
ADAPTABLEDeploy optimized domain-specific architectures
Adapt to changing algorithms
![Page 11: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/11.jpg)
© Copyright 2020 Xilinx
Database Search & Analytics
90xFinancial
Computing
89xMachineLearning
20xVideo
Processing
12xHPC &
Life Sciences
10x
Data Center and AI Accelerator Cards
![Page 12: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/12.jpg)
© Copyright 2020 Xilinx
Unified Software Platform
• Unified methodology edge to cloud
• Focus on platform and acceleration
• Available for free
*Open source Xilinx Runtime library (XRT), Accelerated libraries, AI Models
![Page 13: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/13.jpg)
© Copyright 2020 Xilinx
2012 2019
#D
EV
EL
OP
ER
S
Vivado
OS and
Firmware SDK
SDSoC
(Embedded)
SDAccel, Data Center
(FaaS, Alveo)
AI Inference
Acceleration
Vitis UnifiedSoftware Platform
Platform Transformation
![Page 14: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/14.jpg)
© Copyright 2020 Xilinx
Xilinx runtime libraries (XRT)
Vitis target platform
Domain-specific
development
environment
Vitis core
development kit
Vitis accelerated
libraries
OpenCV
Library
BLAS
Library
Vitis AI Vitis Video
Partners
Genomics,
Data Analytics,
And moreFinance
Library
Analyzers DebuggersCompilers
Vitis: Unified Software Platform
![Page 15: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/15.jpg)
© Copyright 2020 Xilinx
Build: Extensive, Open Source Libraries
400+ functions across multiple libraries for performance-optimized out-of-the-box acceleration
Vision &
Image
Finance Data Analytics &
Database
Data Compression Data Security
Math Linear Algebra Statistics DSP Data Management
Domain-Specific Libraries
Common Libraries
![Page 16: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/16.jpg)
© Copyright 2020 Xilinx
Frameworks
Vitis AI
development kit
Vitis AI
models
Deep Learning
Processing Unit
Vitis AI: Deep Learning Acceleration
Xilinx runtime library (XRT)
AI Optimizer AI Quantizer AI Compiler AI Profiler AI Library
![Page 17: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/17.jpg)
© Copyright 2020 Xilinx
Example performance
![Page 18: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/18.jpg)
© Copyright 2020 Xilinx
Computational Fluid Dynamics
18
ALVEO Accelerated CFD Kernels
Faster Time to insight, Fewer Nodes
• 4x Faster simulation time• 80% lower energy consumption• 6x better performance per Watt
![Page 19: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/19.jpg)
© Copyright 2020 Xilinx
Computational StorageLine-rate Data Compression Acceleration
Compression, decompression, erasure coding,
encryption all accelerated on one platform
19Source: Xilinx Analysis
1x
20x
0 5 10 15 20
CPU
Alveo U50
Intel Skylake-SP 6152 @2.10GHz 22-core CPU (Ubuntu 16.04), GB/s compression per CPU core = .0229. Alveo U50 = 10GB/s
![Page 20: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/20.jpg)
© Copyright 2020 Xilinx 20
Alveo U50
Acceleration
2x Less Nodes
40% Lower Total Cost
20x Throughput Per Node
Intel Skylake-SP 6152 @2.10GHz CPU (Ubuntu 16.04), GB/s compression per CPU core = .0229. Alveo U50 = 10GB/s, Assume 2:1
compression
192TB SSDs, 1GB/sec Per Node
Compression Throughput
2x Dual CPU Servers96TB SSDs (192TB effective),
20GB/sec Per Node Compression
Throughput
Alveo Server with 2x Alveo U50
Computational StorageLine-rate Data Compression Acceleration
![Page 21: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/21.jpg)
© Copyright 2020 Xilinx
Advantages in Machine Learning Inference
0
500
1000
1500
2000
2500
3000
3500
4000
4500
Intel Xeon Skylake Intel Arria 10 PAC Nvidia V100 Xilinx U200 Xilinx U250
Imag
es/s
INCREASE REAL-TIME MACHINE LEARNING* THROUGHPUT BY 20X
* Source: Accelerating DNNs with Xilinx Alveo Accelerator Cards White Paper
20x advantage
![Page 22: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/22.jpg)
© Copyright 2020 Xilinx
Advantages in Latency
0 5 10 15 20 25 30 35 40 45 50
CPU+ Alveo
CPU+ GPU
CNN+BLSTM Speech-to-Text Latency (ms)
REDUCE ML INFERENCE LATENCY BY 3X
Lower value is better
Alveo Provides Massive Parallel Compute with Lowest Latency vs GPUs
![Page 23: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/23.jpg)
© Copyright 2020 Xilinx
Xilinx – Matched Throughput
Other solutions – Mismatched Throughput
AI InferencePerformance
Critical Functions
Performance
Critical Functions
AI InferencePerformance
Critical Functions
Performance
Critical Functions
Whole Application Acceleration
![Page 24: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/24.jpg)
© Copyright 2020 Xilinx
AI Accelerated Dark Matter Search (CERN)
https://www.xilinx.com/content/dam/xilinx/publications/powered-by-xilinx/cern-case-study-final.pdf
Real-time ML Inference + Sensor pre-processing
100ns Inference Latency on 150 Terabytes/Second Data Rates
Xilinx FPGA
CMS
Sensor
![Page 25: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/25.jpg)
© Copyright 2020 Xilinx
Introducing the Versal ACAP
![Page 26: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/26.jpg)
© Copyright 2020 Xilinx
AC AP
![Page 27: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/27.jpg)
© Copyright 2020 Xilinx
daptiveomputeccelerationlatform
ACAP
![Page 28: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/28.jpg)
© Copyright 2020 Xilinx
Compute Acceleration
AdaptableEngines
ScalarEngines
IntelligentEngines
![Page 29: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/29.jpg)
© Copyright 2020 Xilinx
For Any Developer
For Any Application
Heterogeneous Acceleration
The Industry’s First ACAP
7nm FinFET
![Page 30: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/30.jpg)
© Copyright 2020 Xilinx
Scalar Processing Engines
Versal ACAPTechnology Tour
Adaptable Hardware Engines
Intelligent Engines SW Programmable, HW Adaptable
Breakout Integration of AdvancedProtocol Engines
![Page 31: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/31.jpg)
© Copyright 2020 Xilinx
Scalar Processing Engines
Arm Cortex-A72Application Processor
Arm Cortex-R5Real-Time Processor
Platform Management Controller
![Page 32: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/32.jpg)
© Copyright 2020 Xilinx
Adaptable Hardware Engines
Re-architected foundational HWfabric for greater compute density
Enables custom memory hierarchy
8X Faster Dynamic Reconfiguration (“on-the-fly”)
![Page 33: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/33.jpg)
© Copyright 2020 Xilinx
Intelligent Engines
DSP EnginesHigh-precision floating point & low latency
Granular control for customized datapaths
AI EnginesHigh throughput, low latency, and power efficient
Ideal for AI inference and advanced signal processing
![Page 34: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/34.jpg)
© Copyright 2020 Xilinx
AI Engines
Optimized for AI Inference andAdvanced Signal Processing Workloads
VECTOR CORE
MEM
OR
Y
VECTORCORE
MEM
OR
Y
VECTORCORE
MEM
OR
Y
VECTORCORE
MEM
OR
Y
![Page 35: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/35.jpg)
© Copyright 2020 Xilinx
Network-on-Chip (NoC)Ease of UseInherently software programmableAvailable at boot, no place-and-route required
High Bandwidth and Low LatencyMulti-terabit/sec throughputGuaranteed QoS
Power Efficiency 8X power efficiency vs. soft implementationsArbitration across heterogeneous engines
![Page 36: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/36.jpg)
© Copyright 2020 Xilinx
Xilinx University Program
Donation program
Training materials
Request tutorials
www.Xilinx.com/university
![Page 37: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/37.jpg)
© Copyright 2020 Xilinx
Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP
Try the new Vitis software for
platform design free
Test drive Alveo – production ready
accelerator cards
Next generation Versal ACAP
Adaptability
Power
Compute
density
Performance CostData rates
Machine
Learning
Cloud
scalability
![Page 38: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/38.jpg)
© Copyright 2020 Xilinx
Thank You
![Page 39: Next generation compute efficiency with Xilinx FPGAs and the … · 2020. 2. 18. · Next generation compute efficiency with Xilinx FPGAs and the new Versal ACAP Try the new Vitis](https://reader036.fdocuments.net/reader036/viewer/2022062606/5fe9445c9396147a47666dc3/html5/thumbnails/39.jpg)
© Copyright 2020 Xilinx
Building the Adaptable,
Intelligent World
Xilinx Mission