[Nexite] Bios Overview

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x86 BIOS Overview

nexite R&D Center

S/W 개발팀 이 태 현 부장2008. 12.16

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AgendaBIOS DefinitionBIOS DefinitionBIOS RoleBIOS RoleBIOS FlowBIOS FlowBIOS FeaturesBIOS FeaturesPOST CardPOST CardBIOS ROM BIOS ROM BIOS Development StageBIOS Development StageThe Customized x86 BIOS example for Embedded The Customized x86 BIOS example for Embedded SystemSystemQ&AQ&A

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1. What BIOS Stands for?

-Basic -Input -Output -System

1) Definition

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SystemInput Output

Keyboard

Mouse

Video

Printer

Scanner Speaker

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2) BIOS Vendor List

-Bought Award Software International in 1998-Bought General Software in 2008

http://www.ami.com

http://www.phoenix.com

http://www.insydesw.com

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<Basic System Structure>

Hardware

System Software

Application/OS

2. BIOS Role

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HardwareHardware

App./OSApp./OS

Initializatio

n

Pro

vide in

fo

Basic IO

INT

Config

uratio

n

DOSLinuxWindows

Functio

n T

est

Reso

urce

Allo

cation

2. BIOS Role (Cont’d)

Pro

vide I/F

System Software (Firmware)System Software (Firmware)

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ex) Keyboard Operation

MOTHERBOARDKEYBOARD

CONTROLLER(8042)

MOTHERBOARDKEYBOARD

CONTROLLER(8042)

INT 9 HANDLER

INT 9 HANDLER INT 16

HANDLER

INT 16HANDLER

OPERATINGSYSTEM

ANDAPPICATIONS

OPERATINGSYSTEM

ANDAPPICATIONS

BIOS DATA AREABIOS DATA AREA

2. BIOS Role (Cont’d)

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ENABLEA20

PORT DECODE

INTERRUPTCONTROLLER

SYSTEMCONTROL ANDINFORMATION

8042

IOR

IOW

SYSTEMRESET

CPU

60/64

SERIAL LINK8

DATA BUS

KEYBOARDCONTROLLER

IRQ1

1

“Q” KEY (Pressed)

Kscan code (15h)

0 1 0 1 0 1 0 0 0 0 1

Odd paritystart

stop

data

clock

data

IRQ1

ex) Keyboard Operation

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Boot BlockBoot Block POSTPOST Boot-Strap LoaderBoot-Strap Loader

OSOS

3. BIOS Flow

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Boot BlockBoot Block POSTPOST Boot-Strap LoaderBoot-Strap Loader

OSOS

Memory Auto DetectionBy using SPD

Go to Recovery ModeIf requested,If BIOS Checksum isfailed

Power On Self Test

Initialize & Configure chip Timer, Interrupt, DMA

System Resource AllocationPCI/ PnP DevicePCI IRQ Routing

Configure Bootable DevicesHDD, CD, USB, Network

Configure APM/ACPI

Configure SMBIOSProvide system Info.

Save System Info.Memory SizeSystem Equipment

Load Boot DevicesHDD, CD, USB, Network

Prepare INT SVC Routine

3. BIOS Flow (cont’d)

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1) Boot Block Mode

WhatThe Boot Block is a mini scale BIOS.Contains system initialization code.

WhyRecover faulty BIOS (without physically removing the ROM )BIOS upgrade.

WhenBIOS checksum fails.User Force, Specific Key


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2) POSTPower On Self Test

A diagnostic testing sequence run by the BIOS as the computer’s power is initially turned on.

Tests all system components

Configures and initializes configurable components

Prepares PC to boot OS

Bootstrap : Loads the operating system ( O/S). If it can’t do that, it will ask for an alternate source for an O/S such as a diskette.

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3) Runtime Code

Runtime is the BIOS code that runs after POST.

Legacy Interrupt Services for low level I/O.IDE, Floppy, Keyboard, Screen, Serial, Parallel,…

SMI/SCI service for Power Management.

PnP/PCI services

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4) ROM Information

(참고, AMI BIOS 기준)

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OSOS

BootblockBootblock POSTPOST Boot-Strap LoaderBoot-Strap Loader


BIOS Setup

reset

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[ BIOS(CMOS) Setup ]

Where is CMOS?In South-Bridge, SIO, etc

What to do?Set/Change

Date/Time info.Chipset Register (NB, SB, SIO)Booting Sequence (FDD, CDROM, HDD, Network, USB)Password (Supervisor, User)

Show Info.BIOS VersionDate/TimeCurrent configurationH/W Monitor (FAN/Voltage/ Thermal)


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[ BIOS(CMOS) Setup ]



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1) DRAM Auto Detection

Fully support every possible DRAM combination

DRAM Auto Detection by SPD

SPD (Serial Presence Detect) information# of Row Addresses on this assembly# of Col Addresses on this assemblyDIMM configuration type (parity, ECC)DRAM type (EDO, SDRAM, DDR…)Manufacturer informationTiming Values, …

4. BIOS Features

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2) CPU Auto DetectionSupport Intel, AMD, VIA

Auto detect CPU ID and display string on screen

Auto detect running speed

Automatically program timing related chipset parameters when different CPU running with different clock speed

Automatically apply appropriate power management code for different CPU

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3) DMIDesktop Management Interface

Database of computing system

Types, capabilities, operational status, installation date, and other information about the system components.

Example : System Information (Type 1)

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4) Plug and PlayFocus on easy-of-use for the end-user

Dynamic resources assignment (DMA, IRQ, I/O, Memory) Preserve resources for legacy usageISA PnP CardPCI Card

PnP service routine

Dynamically report device node to OSEnable/Disable onboard device via setupReassign resources for all M/B devices

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5) Power Management

APMAdvanced Power ManagementPower Management by BIOSSMI (System Management Interrupt)

ACPIAdvanced Configuration and power InterfaceCurrent Revision 3.0bPower Management by OS and BIOSSMI/SCI (System Control Interrupt)

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5. POST CardShows the value of IO PORT 80H

Shows the progress status of BIOS POST

Interface: ISA/PCI/Mini-PCI/PCI-E(1x) Type

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Write Value#1 to POST CardWrite Value#1 to POST Card

DO BIOS POST #1DO BIOS POST #1

Write value#2 to POST CardWrite value#2 to POST Card


Write value#3 to POST CardWrite value#3 to POST Card


Concept

5. POST Card (Cont’d)

“ If system is hanged and POST code value is say #2?”

“Like bookmark to show where you are”

How should we understand the POST Code?

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1) BIOS Post Code (Boot Block)

Before D1

Early chipset initialization is done. Early super I/O initialization is done including RTC and keyboard controller. NMI is disabled.

D1 Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch CMOS.

D2 Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum.

D4 Disable CACHE before memory detection. Execute full memory sizing module. Verify that flat mode is enabled.

D5 Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM.

D6 Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to checkpoint E0.

D7 Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.

D8 The Runtime module is uncompressed into memory. CPUID information is stored in memory

D9 Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory.

DA Restore CPUID value back into register. Give control to BIOS POST.


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03 Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area.

04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system

05 Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.

06 Initializes 8254 timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt.

08 Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5.

0A Initializes the 8042 compatible Key Board Controller.

0C Detects the presence of Keyboard in KBC port.

0E Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.

13 Early POST initialization of chipset registers.

20 Uncompress and initialize any platform specific BIOS modules.

2A Initializes different devices through DIM.

2C Detects and initializes the video adapter installed in the system that have optional ROMs.

0B Detects the presence of PS/2 mouse.

2) BIOS Post Code (POST 1)


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31 Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.

40 Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, … etc.) successfully installed in the system and update the BDA, EBDA…etc.

52 Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory.

60 Initializes NUM-LOCK status and programs the KBD typematic rate.

75 Initialize Int-13 and prepare for IPL detection.

85 Display errors to the user and gets the user response for error.

87 Execute BIOS setup if needed / requested.

33 Initializes the silent boot module. Set the window for displaying text information.

37 Displaying sign-on message, CPU information, setup key message, and any OEM specific information.

38 Initializes different devices through DIM.

39 Initializes DMAC-1 & DMAC-2.

3A Initialize RTC date/time.

3B Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.

3C Mid POST initialization of chipset registers.



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8C Late POST initialization of chipset registers.

8D Build ACPI tables (if ACPI is supported)

8E Program the peripheral parameters. Enable/Disable NMI as selected

90 Late POST initialization of system management interrupt.

A0 Check boot password if installed.

A2 Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module.

A4 Initialize runtime language module.

B1 Save system context for ACPI.

00 Passes control to OS Loader (typically INT19h).

A7 Displays the system configuration screen if enabled.

A9 Wait for user input at configuration display if needed.

AA Uninstall POST INT1Ch vector and INT09h vector. De-initialize the ADM module.

AB Prepare BBS for INT 19 boot.

AC End of POST initialization of chipset registers.



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6. Where is the BIOS?

ISA LPC FWH SPIBIOS I/F:

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7. BIOS Development Stage

1. Review Stage1. Review Stage

2. Alpha Stage2. Alpha Stage

3. Beta Stage3. Beta Stage

4. Final Stage4. Final Stage

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Schematic ReviewSchematic Review

BIOS Source RequestBIOS Source Request

Summary of GPIO Usage

Summary of Device Usage

Summary of PCI IRQ Routing

NB (North-Bridge) Type

SB (South-Bridge) Type

SIO (Super I/O) Type

CPU Type

Features to be supported

Summary of OEM Spec. and Implementation(BIOS Implementation Spec.)

1) Review Stage

Datasheet ReviewDatasheet Review

CPU Review

NB/SB Review

SIO Review

Other chipset Review

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Initial Stage that Video can be displayed and POST is completed

2) Alpha BIOS Development Stage

Initial Stage that H/W Engineer can check basic hardware signal

Meets BIOS Implement Spec.

3) Beta BIOS Development Stage

Can use Onboard Device

Can use a device through PCI Slot/ PCI-E/ USB I/F

Can go on DVT Function Test

DVT Function Test is completed and RC TEST is ready

All R&C Errors are fixed

4) Final BIOS Development Stage

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8. The Customized x86 BIOS example for Embedded System

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Q & A

감사합니다.

[Nexite] Bios Overview

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