New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC

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LUKAS PÜLLENNew prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC

New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC

Lukas Püllen, Jennifer Boek, Susanne Kersten, Peter Kind, Peter Mättig, Christian Zeitnitz

PIXEL 2012, Inawashiro, Japan

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Introduction

Upgrade of LHC to the High-Luminosity-LHC (HL-LHC) in the years around 2020

– Increase of luminosity to L = 5·1034 cm-2s-1

– Targeted integrated luminosity 3000 fb-1

ATLAS inner tracker will be replaced entirely

– Pixel detector (inner layers)

– Strip detector (outer layers)

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Requirements of a control system for the new ATLAS pixel detector

To ensure a safe operation if the ATLAS Pixel Detector the detector control system (DCS)

has to meet several requirements:

Radiation hard

Low material cost and impact to measurements of the other ATLAS subdetectors

Low power consumption (passive cooling)

Easy to integrate into the ATLAS DCS framework

Reliable steering of all operation relevant quantities:– Supply voltages for detector components

– Switching of detector components

– Temperature, voltage and current monitoring

– Providing reset signals

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Idea of a control system for the new pixel detector

Radiation tolerant control system for a reliable monitoring and control of the pixel detector

Splitted in three paths:

– safety path

• Hardwired interlock system

– control-feedback path

• For all use cases

– diagnostics path

• Detector calibration

(embedded into the

optical link)

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Idea of a control system for the new pixel detector

The control-feedback path

Star shaped network of two chips

– DCS controller

– DCS chip

Counting room to DCS controller via CAN*

DCS controller to DCS chip via I2C-HC**

Data is processed locally to reduce lines

Tasks of the network

Measuring voltages, temperatures and

humidities

Delivering measured data from the detector

to the user

Delivering and executing user

commands to the detector

Distance from interaction point

100m

20m

<1m

*Controller Area Network**I²C-Hamming Code

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The I2C-HC protocol

Extension to the known I²C protocol by four check bits

– Shortened, cyclic Hamming code (12,8)

– Detects errorneous messages with two false bits

– Corrects errorneous messages with one false bit

Differential transmission across 20 m

S 8-bit data4 check

bitsAck8-bit data

4 check bits

Ack

Physical layer for the I2C-HC bus is inspired by CAN

2 differential lines (SDA + SCL) Dominant and recessive state Multiple nodes (4 DCS chips) on one bus

Robust protocols decrease the errors in data transmission due to radiation in the DCS to less than 1 undetected error in 10 years of operation!

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Nodes of the network

Concept of the DCS controller CAN node

Master of the DCS chip interface

Bridge between CAN and I2C-HC

Multiplexer connects I2C-HC master

to the corresponding I2C-HC bus (1 out of 4)

Provides clock for the DCS chip

Located at a service point in ATLAS (20m from the IP)

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Nodes of the network

Concept of the DCS chip

Radiation hard

Measures environmental conditions– Temperatures (NTCs)

– Voltages

– Humidity (capacitive sensors)

Communication interface

16 ADC channels (10 bit)

2 channels for humidity measurements

8 digital outputs– Switching parts of the detector

– Distributing reset signals

Low power consumption– Operational without cooling

Located at the EoS card in the pixel detector (<1m from the IP)

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Existing prototypes

Digital Prototypes

DCS chip– Name: CoFee1

– I2C-HC slave

– Chip ID

– Digital outputs

– Single ended data lines

– TMR (Triple modular redundancy)

DCS controller

– Name: CoFee2

– CAN node

– I2C-HC master

– Bridge

– Single ended data lines

– 2 versions:

• With and without TMR

Analog prototypes

Voltage reference

– 3 references in 1 chip (still under studies)

– Chip contains a synthesized shift register with

1500 FF for irradiation measurements

Physical layer for I2C-HC

– Differential driver and receiver

– Dominant and recessive state

– Inspired by CAN

All prototypes in 130 nm process

recessive dominant recessive

0 1 0

300 mV

0 V

V

t

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Dry runs with prototypesTesting in the lab: Tested components:

– CoFee1 (DCS chip)

– CoFee2 without TMR (DCS controller)

– CoFee2 with TMR (DCS controller)

– Physical Layer

Results:– CoFee2 with TMR does not work completely

• Clock tree issues

– Communication chain from PC to DCS chip works

– Max cable length for I2C-HC ~80m at 200kHz:

DCS computer

Kvaser CAN

DCS controller(without TMR)

PhysicalLayer

DCS chip

VP230

PhysicalLayer

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Radiation tolerance

Radiation exposure of electronics in the pixel detector up to 570 MRad Neutron equivalent dose 2·1016 neq/cm2 at 3000 fb-1

Expected flux of charged hadrons at the EoS card: 3·108s-1cm-2 (E>20MeV)

Effects of the radiation:

– Material damage due to long term irradiation

– Single event effects

• Upsets (SEU) → bitflips

• Latchups (SEL) → shorts

• Transients (SET) → glitches

• Etc

Design kit issue

In clocked designs handled as SEU

Redundancy

Triple Modular Redundancy (TMR)

Each register has two clones

Voter logic produces single outputVoter logic

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Irradiation at PSI

Proton Irradiation Facility (PIF)– Located at Paul Scherrer Institute (Switzerland)

– Proton beam

– Beam energy up to 99.7 MeV

– Flux up to 4.25·109 p+s-1cm-2

• EoS: 3·108s-1cm-2 (E>20MeV)

Several prototypes irradiated:

– Physical Layer

– CoFee1 (DCS chip)

– CoFee2 (DCS controller) with TMR

– CoFee2 (DCS controller) without TMR

– Shift register (4x1500 FlipFlops)

Verify reliability under irradiation

Measure cross section for SEUs

Test for necessity of TMR

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Irradiation of the Shift Register

4 chips on a carrier pcb with 1500 FF each

Filled and read out with a ...0011... pattern every 1-2 minutes

Reference chip was operated in radiation free environment

– Observed no bitflips

Homogenious beam profile with a diameter of 2 cm

Crossection (4.4±0.3)·1014cm2/bit 0->1: (1.4±0.2)·1014cm2/bit 1->0: (3.0±0.4)·1014cm2/bit

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Irradiation of the Cofee2 without TMR

Operated with beam fluxes between

5·108 – 4.25·109 cm-2s-1 and

E = 99.7 MeV

Operated with commercial physical layer

for differential lines

Reference setup in the control room

showed no errors

Results:

– Stable communication could not be established

– Chip hang up several times and had to be

resetted

– Reliable operation without TMR NOT possible

TMR is necessary!

DCS computer

Kvaser CAN II

CoFee2No TMR

DCS chip

VP230

Beam

VP230

CoFee2No TMR

DCS chip

VP230

VP230

VP230

VP230

Beam areaControl room

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Irradiation of the Cofee2 with TMR

Chip has clock tree issues– Only several commands work stable


1·109 – 4.25·109 cm-2s-1 and E = 99.7 MeV

Overall fluence on the chip 4.97·1013cm-2

Operated with commercial physical layer

for differential lines

Results:

– Writing commands work stable during irradiation

– TMR corrects bitflips

– Comparing measurment with the same commands

in noTMR chip produced 4 errors in a fluence of

1.53·1013cm-2

DCS computer

Kvaser CAN II

CoFee2with TMR

DCS chip

VP230

Beam

VP230

CoFee2with TMR

DCS chip

VP230

VP230

VP230

VP230

Beam areaControl room

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Irradiation of the CoFee1 and the Physical Layer


1·106 – 5·108 cm-2s-1 and E = 99.7 MeV

Overall fluence on the chip 4.2·1012cm-2

Operated with single ended lines

Physical Layer chip placed behind the

CoFee1 chip

Results CoFee1– 5h of DCS communication were entirely faultless

– TMR cleaned out all errors

Results Physical Layer– No change in transition times and signal delay

within the errors of the measurements of the

scope

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Summary and Outlook

We aim for a reliable control system for ATLAS pixel

– Radiation tolerant

– Network topology

– Reliable busses

– Measure voltages, temperatures and humidity

– Switch detector components

– Provide reset signals

3 digital prototypes– Working DCS chip

– DCS controller with issues (understood)

2 Analog prototypes– Working physical layer

– Voltage references

Study voltage references Further study the results of the

irradiation at PSI– Power consumption

Next Chip in development: ADC parts– DAC + comparator

– Successive approx logic

Next submission: Corrected DCS controller design

New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC

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