New Applications of CMP for Non-Traditional Semiconductor Manufacturing

SEMICONSEMICON Taiwan 2006Taiwan 2006

New Applications of CMP for Non-Traditional Semiconductor

Manufacturing

Robert L. Rhoades, Ph.D.Entrepix, Inc.


Outline

IntroductionNew Applications of CMP

MEMSNon-CMOS Devices

New MaterialsEpitaxial Layers and Engineered SubstratesDirect Wafer Bonding

Summary and Future Outlook


Introduction

CMP has been a mainstream process <15 yearsCMP processes in CMOS flow include:

Oxide (pre-metal or interlevel dielectric planarization)Tungsten (contacts, plugs, local interconnect)Shallow trench isolationCopper dual damascene

Other technologies are now adapting CMP to solve planarization challengesSome require only process modifications …and some require new pads and/or slurries


CMP Process ComplexityWafer / Materials Parameters

Size / Shape / FlatnessFilm Stack Composition

Metals (Al, Cu, W, Pt, etc.)Oxide (TEOS, PSG, BPSG, etc.)Other (polysilicon, low-k polymers, etc.)

Film Quality IssuesStress (compressive or tensile)Inclusions and other defectsDoping or contaminant levels

Final Surface RequirementsUltralow surface roughnessExtreme planarization, esp. CopperLow defectivity at <0.12 um defect size

Pad IssuesMaterials (polyurethane, felt, foam, etc.)Properties must be chosen for the jobConditioning method often not optimizedLot-to-lot consistency

Slurry IssuesChemistry optimization often requiredMixing and associated inconsistencyShelf life and pot life sometimes very shortSlurry distribution system (design, cost, upkeep)

Agglomeration and gel formationFiltration is often required

Cleaning method specific to slurry and filmWaste disposal and local regulations

Process IssuesLong list of significant input variables

DownforcePlaten speedCarrier speedSlurry flowConditioning method

Disk used (material, diamond size, spacing, etc)ForceSpeedSweep profile

Highly sensitive to local pattern variationMust maintain consistency at high throughputMust optimize for variation of incoming films

Integration IssuesMaterials Compatibility

Electrochemical interactions with two or more metalsFilm integrity and delamination, esp. low-kFilm stack compressibility

Interactions with adjacent process modulesPhotolithographyMetal deposition and metal etchDielectric deposition and etch

Electrical design interactionsFeature size constraintsInteractions with local pattern densityLine resistance variation, esp. damascene copperDielectric thickness variation Contact resistance variation

Any one of these areas can create major headaches for process engineers & integration teams.


MEMS ApplicationsTypical Devices:

Accelerometers

Torque sensors

Optical devices

Microfluidic processors

Key Aspects of the ApplicationMaterials and core processes generally adapted from CMOS fabrication

CMP is an enabling technology for many designs

Thicknesses and step heights substantially larger than typical of CMOS

Lengthy polish times challenge process stability & consumables lifetime

Photos downloaded from web sites, including Sandia National Lab

Typical MaterialsUndoped oxides (TEOS, silane, etc.)

Doped oxides (PSG, BPSG, etc.)

Polysilicon

Some metals (specialized apps)


MEMS Processing

Typical Parameters & Targets

> 90%Planarization Efficiency

> 0.5 um/minRemoval Rate

2 – 20 micronsTopography

2 – 15 micronsFilm Thickness

MEMS Examples:Thick Poly Stop on oxide

Thick Oxide Stop on poly

Thick Oxide Stop on silicon

Thick Metal Stop on oxide

Tungsten Stop on oxide

Copper Stop on oxide

Any dielectric Stop mid-layer

And many more …


Example: MEMS over CMOSKey Process Metrics & Constraints

n/a

2.8 um

6.5 um

Incoming Value

0.5

< 0.4 um

3.0 um

Post-CMP Target

3.02 umOxide film thickness

0.488Removal Rate (um/min)

0.2 umStep Height

ActualMetric

Critical Concerns:Final topography must be < 0.4um

Smooth – No sharp corners anywhere

Batch to batch consistency

0

1000

2000

3000

4000

5000

6000

1 2 3 4 5 6 7 8 9 10 11 12

Run #

Rem

oval

Rat

e (A

ng/m

in)


Selectivity for Specialized Integrations

Other SystemsPolysilicon over oxides

Oxides over single crystal silicon

Inlaid metals (damascene)

Example:

BPTEOS on Silicon NitrideTopography patterned in nitride

Deposit doped (or undoped) TEOSfor inlaid planarization layer

Goal of CMP process is to stop on nitride without breaking through and planarize across all inlaid features

>25 : 1Selectivity (BPTEOS:SiN)

BPTEOS oxideTop layer material

> 98%

4900 Ang/min

LPCVD silicon nitride

Value or Description

Bottom layer material

Planarization Efficiency

BPTEOS removal rate

Example Parameter


Direct Wafer BondingTypical Materials

Silicon-on-Something

Ge-on-Something

TEOS over almost anything

Compound semi sandwich

Inlaid structures

Key Aspects of the TechnologySurface roughness is generally the most critical metric

Short range and long range topography also major metrics on patterned wafers

Post-CMP cleaning is often supplemented by aggressive pre-bond cleaning

New applications for DWB are emerging at a rapid pace

Types of DevicesHigh performance substrates

Integrated optics devices

Buried device functionality


Examples: DWB

Example #2: Inlaid Cu in TEOSIncoming topography >2.5 kA

Goal of <200 A total topography

POST-CMP TOPOGRAPHY ACHIEVED

70-90 Angstroms

Example #1: TEOS on XOxide surfaces tend to bond well

when polished to sufficiently low Ra

Incoming roughness driven by surface prep of underlying material

Sufficient oxide thickness must be deposited to remove at least 2x initial peak-to-valley roughness

Flat across

Feature

11187TEOS on AlN

37TEOS on Silicon

332

87

72

Incoming Ra (A)

7TEOS on SiC

8TEOS on Metal

7TEOS on Polysilicon

Post-CMPRa (A)Material Stack


Backside Stress Relief CMP

Backgrind is a nearly universal technique for wafer thinningCMOS, discrete devices, MEMS, sensors, etc.

Different device technologies have different drivers. [1]Packaging (space limitations, 3D systems, ultrathin applications, etc.)Heat dissipationLower noise and other electrical performance improvements

Damage created during backgrind creates a compressive stress layer that penetrates into the Si crystal. (Previous studies indicate a depth between 8 and 30 microns.) [2]Wafer and die strength are compromised by the damage layer. [3]CMP is an effective technique for creating low-defect surfaces and can be used to remove the damage layer (similar to prime wafer polishing).

[1] M. Reiche and G. Wagner, “Wafer Thinning: Techniques for Ultra-thin Wafers”, Advanced Packaging, March 2003.

[2] C. McHatton and C. Gumbart, “Eliminating Backgrind Defects with Wet Chemical Etching”, Solid State Technology, November 1998.

[3] E. Gaulhofer, “Wafer Thinning and Strength Enhancement to Meet Emerging Packaging Requirements”, IEMT Symposium, IEEE, April 2000.


Example: Backside CMP

As ground surface (20x objective lens)

Deep grooves easily seen with naked eye

Post decoration etch (50x objective lens)

Clean (no visible particles) with very mild etch roughening

No pits or strong dislocation lines observed

Conclusion Regardless of backgrind or CMP process parameters, decoration etch does not reveal significant damage as long as CMP removes at least 4.5 um of silicon.

0

1

2

3

4

5

6

7

0 1 2 3 4 5 6 7 8Thickness Removed (um)

Surf

ace

Rat

ing

Minimal surface pitting after decoration etchSignificant subsurface damage evidentas pits or scratch tracks after decoration etch


New Materials

Reasons for introducing new materialsEnhance performance of next generation deviceDevelop completely new type of deviceImprove yield or lower cost

Largest volume application is CMOSStrained layer technology Low-k dielectricsPt, Ru, or other refractory metals

Many new device applications being developed


Evolution of CMP applications ... And that’s just Si electronics !!

Future

Trend?


Engineered SubstratesTypical Materials

SOI

Strained Layer SiGe

Custom III-V or II-IV composites

Key Aspects of the ApplicationSOI helps circuit isolation and power consumption (less coupling)

Strained layer technology being used to increase carrier mobility in Si devices

Heteroexpitaxy of mismatched materials seeing growing # of applications

Usually creates huge density of threading dislocations and other issues

Extremely high roughness needs to be polished to achieve <1nm Ra

Some materials (esp. II-IV blends) difficult to polish w/o anisotropic etching

Cleaning of polished surfaces is often difficult (some are etched by NH4OH)

Base Substrate

Epi Layer


Specialty Substrates: SiGe Layers

0

500

1000

1500

2000

2500

0% 20% 40% 60% 80% 100%

Epi Layer %Ge

Polis

h R

ate

(Ang

/min

)

n/a

n/a

>10 nm

Incoming Value

0.25-0.75 um

>500 A/min

<1 nm

Target

0.2-1.4 nmSurface Roughness, Ra

Within 5%Total Mtrl Removal

480-1600A/min

Removal Rate

ActualMetric

0

3

6

9

12

Pre-CMP Post-CMP

Rou

ghne

ss, R

a (n

m)


Other Novel CMP Applications

Integrated OpticsWaveguidesReflective surfacesActive switches, multiplexers, etc.In-plane or through plane

Packaging ApplicationsLarge Cu vias and feedthroughsPolymer planarization for multiple layers

Compound Semiconductor DevicesUnique integration schemes and process flowsMuch more delicate substrates Generally involve smaller wafer sizes (100mm, etc.)


Current Status

CMP is accepted as a mainstream process Adaptation to numerous other technologies is well underway

Often involve materials not found in CMOS mfgFilm thickness can be 10’s of microns … or more!

Specialization of pads/slurries is usually only required if standard products failDifficult to predict which segments will grow the fastest, but MEMS has the leadCMP suppliers and technologists will continue to be challenged as new applications emerge


Acknowledgments

Jeanie Simmons, Terry Pfau, Paul Lenkersdorfer, Donna Grannis, Dwaine Halberg, and the rest of the Entrepix process staff.

For more information, please contact:

Mike BowmanDirector of Business Development

Tel: 602 [email protected]

Rob RhoadesChief Technology Officer

Tel: 602 426-8668Fax: 602 426-8678

[email protected]

Bob TuckerVP and General Manager

Tel: 602 [email protected]

New Applications of CMP for Non-Traditional Semiconductor Manufacturing

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