NetFusion-M2S-SOM-F484 SFP SERDES Main-Board PCB

NetFusion-M2S-SOM-F484 SFP SERDES Main-Board PCB

Design Hardware-Architecture Draft 0.3 – September 12th 2014

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NetFusion-M2S-SOM-F484-SFP PCB

Nine Ways R&D Design Hardware-Architecture



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Contents

1 INTRODUCTION .......................................................................................................................................... 6

1.1 WHAT IS THE NETFUSION PROJECT? ......................................................................................................... 6 1.2 DESIGN SUMMARY .................................................................................................................................... 7 1.3 DESIGN OBJECTIVE ................................................................................................................................... 8

2 DESIGN IDE AND FILE STRUCTURE FOR DEVELOPMENT .................................................................. 9

2.1 OVERVIEW ................................................................................................................................................ 9 2.2 ALTIUM DESIGNER .................................................................................................................................. 10 2.3 DIRECTORY STRUCTURE OF NETFUSION SUB-REPOSITORY ...................................................................... 10

3 FORM FACTOR OF THE PCB .................................................................................................................. 12

4 TOP LEVEL ARCHITECTURE .................................................................................................................. 13

4.1 OVERVIEW .............................................................................................................................................. 13 4.2 BLOCK DIAGRAM OF FUNCTIONALITY ........................................................................................................ 13

5 COMPONENT DESCRIPTION DETAILS .................................................................................................. 14

5.1 SOM CONNECTORS ................................................................................................................................ 14 5.2 USB UART INTERFACE .......................................................................................................................... 14 5.3 ETHERNET INTERFACE ............................................................................................................................ 14 5.4 USB OTG INTERFACE ............................................................................................................................ 14 5.5 FLASHPRO JTAG INTERFACE .................................................................................................................. 14 5.6 ARM JTAG INTERFACE .......................................................................................................................... 14 5.7 POWER SUPPLY ...................................................................................................................................... 15 5.8 RESET BUTTON....................................................................................................................................... 15 5.9 GENERIC OPTION-JUMPERS AND CONFIGURATION DIALS .......................................................................... 15 5.10 USER BUTTONS & LCD DISPLAY ......................................................................................................... 15 5.11 AUDIO COMPATIBILITY......................................................................................................................... 16 5.12 VOLTAGE MONITOR & TEMPERATURE SENSOR .................................................................................... 16 5.13 REAL-TIME CLOCK (RTC) ................................................................................................................... 16 5.14 RS232 PERIPHERAL ........................................................................................................................... 17 5.15 RS485 PERIPHERAL ........................................................................................................................... 17 5.16 VOLTAGE FREE RELAY PERIPHERAL .................................................................................................... 17 5.17 ANALOGUE CONTACT INPUTS PERIPHERAL .......................................................................................... 18 5.18 GPIO PERIPHERAL ............................................................................................................................. 18 5.19 SIGNAL LOS SWITCH ........................................................................................................................... 18 5.20 EARTH PROTECTION ........................................................................................................................... 18

6 TYPICAL SOM ARCHITECTURE (CURRENT SMARTFUSION2 M2S-SOM-F484) ............................... 19

6.1 HARDWARE PLATFORM OVERVIEW .......................................................................................................... 19 6.2 MICROCONTROLLER & SMARTFUSION2 FPGA ......................................................................................... 20 6.3 SMARTFUSION2 ON-CHIP CONFIGURATION AND FPGA DESIGN ................................................................ 20

7 CONNECTORS .......................................................................................................................................... 21

7.1 CONNECTOR SUMMARY ........................................................................................................................... 21 7.2 MINI USB TYPE B CONNECTORS ............................................................................................................. 22 7.3 RJ45 ETHERNET DUAL CONNECTOR BLOCK (HALO HFJ12-1G16ER) ..................................................... 22 7.1 SFP FIBER MATING CONNECTOR BLOCK ................................................................................................. 23 7.2 SOM INTERFACE CONNECTORS .............................................................................................................. 24 7.3 JTAG CONNECTORS ............................................................................................................................... 30 7.4 POWER SUPPLY ...................................................................................................................................... 31



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7.5 OPTION JUMPER HEADERS ...................................................................................................................... 32 7.6 LCD CONNECTOR ................................................................................................................................... 34 7.7 ANALOGUE CONTACT INPUT CONNECTOR ................................................................................................ 35 7.8 RELAY OUTPUT CONNECTOR ................................................................................................................... 35 7.9 SERIAL CONNECTORS ............................................................................................................................. 36 7.10 GPIO CONNECTOR ............................................................................................................................ 37 7.11 STEREO AUDIO PHONO-JACKS ............................................................................................................ 38 7.12 SIGNAL LOS SWITCH ........................................................................................................................... 39 7.13 EARTHING .......................................................................................................................................... 39

8 FUTURE PCB CONSIDERATIONS WITH NEWER VERSIONS .............................................................. 40

9 CONTACT .................................................................................................................................................. 41

10 DOCUMENT HISTORY ........................................................................................................................ 42



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Document Founder

Mr. Paul. P. Bates Nine Ways Research & Development Ltd (UK)

About This Specification

This specification introduces the design and hardware architecture of the NetFusion PCB as an internal document for Nine Ways R&D Ltd and MorethanIP GmBH. It details and illustrates the schematic design and structure along with design considerations and workings.

Intended Audience

This specification is written for associates and employees of Nine Ways Research & Development Ltd MorethanIP GmbH. It is an internal full specific design document that is confidential for anyone outside the organizational group.



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List of Figures

Figure 1 - Generic PCB Ideology ..................................................................................................................................... 7 Figure 2 – Altium Designer IDE Environment .............................................................................................................. 10 Figure 3 - Example of Schematic editor with Altium Designer IDE........................................................................... 10 Figure 4 - Start point for NetFusion PCB development base directory .................................................................... 11 Figure 5 - PCB Form Factor Nano-ITX ......................................................................................................................... 12 Figure 6 - Graphical Comparison of Nano-ITX ............................................................................................................ 12 Figure 7 - Block Diagram Architecture of the NetFusion-M2S-SOM-F484-SFP Main Board ............................... 13 Figure 8 – SmartFusion2 M2S-SOM-F484 Functional Block Diagram .................................................................... 19

List of Tables

Table 1: Summary of PCB Connectors ......................................................................................................................... 21 Table 2: USB Receptacles .............................................................................................................................................. 22 Table 3: RJ45 (HALO HFJ12-1G16ER) Dual Connector (U5) .................................................................................. 22 Table 4: SFP Mating connector interface (J35, J37) .................................................................................................. 23 Table 5: SOM Header 1 (J12) ........................................................................................................................................ 24 Table 6: SOM Header 2 (J13) ........................................................................................................................................ 27 Table 7: FlashPro JTAG Connector (J28) .................................................................................................................... 30 Table 8: ARM JTAG Connector (J26) ........................................................................................................................... 30 Table 9: Removable Power Connectors (J30, J32) .................................................................................................... 31 Table 10: Molded Power Receptacle (Q2) ................................................................................................................... 31 Table 11: External Power Connector (J33) .................................................................................................................. 31 Table 12: JTAG Mode Selection (LK3) ......................................................................................................................... 32 Table 13: Generic Configuration Header (J9) .............................................................................................................. 32 Table 14: GPIO Sharing RS232 (JP3, JP4, JP5, JP6, JP7) ...................................................................................... 32 Table 15: GPIO Sharing Relays (JP8, JP9) ................................................................................................................. 33 Table 16: Relay 1 Polarity (LK1) .................................................................................................................................... 33 Table 17: Relay 2 Polarity (LK2) .................................................................................................................................... 33 Table 18: LCD Mating Connector (J17) ........................................................................................................................ 34 Table 19: Contact Input Connector (J1 – J8) ............................................................................................................... 35 Table 20: Voltage Free Relay 1 Connector (J10) ........................................................................................................ 35 Table 21: Voltage Free Relay 2 Connector (J11) ........................................................................................................ 36 Table 22: COM1 Serial RS232 9-Way D-Type Connector (J15) .............................................................................. 36 Table 23: COM1 Serial RS232 VERT Connector (J16) ............................................................................................. 36 Table 24: COM2 Serial RS485 4-Way Connector (J19) ............................................................................................ 37 Table 25: Generic General Purpose I/O Connector (J27, J31) ................................................................................. 37 Table 26: Stereo Audio Line OUT Connector Jack (J14) ........................................................................................... 38 Table 27: Stereo Audio Line IN Connector Jack (J18) ............................................................................................... 38 Table 28: Signal los conversion CD74ACT (U39) ....................................................................................................... 39 Table 29: Local Clean Earth Connection (J29) ............................................................................................................ 39 Table 30: Contact Information ........................................................................................................................................ 41 Table 31: Document History Entry Log ......................................................................................................................... 42



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1 Introduction

This document covers the schematic design, block structure and connectivity detail of the NetFusion PCB. The product is an individual PCB based motherboard that will house an industry standard connector to allow for SOM (System-On-Module) FPGA and Processors. This will eventually even include compatibility for Altera and other SOM units that may take a big market share.

Each NetFusion PCB will be specific to a SOM header board as they are very electrically specific. This derivative is the [NETFUSION-M2S-SOM-F484-SFP].

The specific capabilities are set out below and later in this document. This design document will take the details of the development up to the PCB layout phase as this document only covers the schematic functional element of the PCB design. The final PCB implementation will be detailed in the User Reference, Customer reference guide PDFs.

1.1 What is the NetFusion Project?

● An electronic product providing Ethernet connectivity to a new modern range of powerful FPGA/ASIC processing boards (SOM) – System-On-Module.

● It encompasses many different interface media and quantities of interface by utilitizing a range of connectors on varying product ranges.

● It is provided by Nine Ways Research & Development Ltd in Europe on support, design, manufacturing and rights.

● Fully compatible with MorethanIP IP cores to bridge hardware interface capability and the SOM core processors.

● Capable of supporting Altera and MicroSemi standard SOM sub-systems (maybe future releases).

● Can be supplied as a small basic product or larger more comprehensive version.

● Can be used as a prototyping development base or using the vast connector variation, be deployed in the field – forming the same product familiar to that used in early and late stage development.

● Unlike many other development PCBs, NetFusion offers a post-development pathway to market as is – with no design changes required for production (only if need a different production code for de-population or varying parts list.

● Designed to -40 to +85 degrees Celsius industrial temperature specification

● Conforms to EN-61000-4-4 European Electromagnetic Certification: Emissions + Immunity, Electrical safety, surge and transients. USA: FCC conformity can be available.

● Physical orientation allows for boxed or rack-mount layout.

● Use a blank SOM module to design your own entire IP and incorporate the on-board ASIC “hard” dedicated processor (usually ARM).

● Use a start-off template with support IP cores for the PCB hardware. The MAC + DMA combination shall not be offered as standard. Customization then can take place on the design and application software. Possibility of PTP 1588 project integration with the software stack.

● Customer asks for Nine Ways design support to help or fully create IP design (with or without MorethanIP IP cores), write device drivers, help with overall hardware design and if necessary, write application software as an add on service.



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Figure 1 - Generic PCB Ideology

1.2 Design Summary

The NetFusion PCB product implements the following functionalities:

A standardized Nano-ITX form-factor PCB to fit into a 1u-rack.

To support the SmartFusion2 Emcraft SOM as a start point. Includes a JTAG FlashPro interface.

Two 80-pin SOM connectors.

Feature 1 x RJ45 10/100 dedicated to the MSS of any SOM board.

Main channel 2 x Fiber SFP 1.25Gb/s for Mutli/Single Mode operation

Features USB, RS232, RS422, RS485, Audio IN, audio OUT, SPI, Relays, Contacts

Consideration of LCD display and buttons (budget and maybe not at all)

The general operation will allow for an Ethernet switch core. However, additional cores can be used in the FPGA SOM boards.

Full compatibility with Nine Ways R&D Ltd and MorethanIP GmbH IP cores. A software distribution will be made available to launch and use the product as a start point. This features “Hello World” RTOS stub and IP core development project for the IDEs.

Full ISO EN-61000:2011 EMI/EMC compatibility for electrical noise emission/immunity for both radiated and conducted categories.

Industrial temperature capability of -40C to +85C degree Celsius for the main PCB. This will not guarantee a SOM unit but the customer would have to ensure this.

A full DC 9-18V power input range with integrated suppression/protection/earth/smoothing. A battery holder will be foot-printed to supply an RTC IC for time keeping purposes.

This product shall be designed in mind of being deployable at customer sites. This will be a full development platform capable with no additional steps to becoming a deployable industrial product.



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1.3 Design Objective The NetFusion PCB product is an all-in-one main board that allows FPGA/ASIC/CPU SOM units to mount and interface the real-world interfaces. The interfaces will be high-end common Ethernet media, typical GPIO connections such as relays and protected common inputs, audio line-in and audio line-out, SPI, RS232 and RS485 along with other useful hardened connectors. The SOM consists of the processor sub-system, SDRAM, Flash, clock crystals/oscillator ICs and usually a single PHY. This is a common part that the manufacturer of an FPGA/ASIC will provide to make easier for developers. This new type of support has been born out of the essential requirement to keep the sensitive and expensive sub-system separate from the main power supply, interfaces and connectors. NetFusion forms a main board for the SOM of the SmartFusion2 from Emcraft, and also any other compatible SOMs for the high precision SOM mating connector. It is designed for a standard form factor shape and overall fit for a 1u rack installation. The product will be designed to be manufactured as a customer prototype development PCB that can without any modification serve as a production model for market launch. This is because of the EN61000 EMC/EMI certification, the Industrial temperature specification and the various real-world connectors and interfaces housed on a single PCB. Moreover, de-population will allow more cost effective releases chosen to the specific needs of customer’s usage and functional requirements. With a fully smoothed and filtered on-board power regulation from a wide-range DC voltage input, the main board NetFusion PCB product fulfils the design requirement of all-in-one need to provide customer/users with FPGA fabric space, CPU sub-systems, multi-SERDES 1.25Gb/s, vast GPIO and fully regulated power supply. Ideally, hardware cores such as those from Nine Ways & MorethanIP GmbH like the PTP-1588, DMA Controller, MACs, PCSs, Ethernet Switch and many more can all be incorporated along with a chosen industrially or commercially standard operating system running regular services, application and customer specific programs. This add-on allows for the end-user to choose a product such as NetFusion as a prototype development PCB and then move it forwards into the mass-produced industrially hardened market. With de-population available, this design fulfils the requirements of the NetFusion project.



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2 Design IDE and File Structure for Development

2.1 Overview

The project is designed fully, both schematically and PCB layout, in Altium’s Designer 6 and beyond. This is advancement on its predecessor Designs DXP. All of the files associated with this design are kept in the same encapsulated folder in the main Nine Ways design repository. The design documents, Gerber files, PCB files, schematic files, parts lists, Altium libraries for schematic and footprints, will all have appropriately and intuitively named directories within the NetFusion sub-repository.



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Figure 2 – Altium Designer IDE Environment

2.2 Altium Designer

The Designer IDE can import and use older Designs DXP files, libraries and projects. An import process is usually required however. All designers in this project uses SVN subversion to keep the projects synchronized. SVN is able to be integrated into the Designer projects in this IDE.

Figure 3 - Example of Schematic editor with Altium Designer IDE

2.3 Directory Structure of NetFusion Sub-Repository

● NetFusion PCB <directory>

This forms the main base directory inside SVN repository of Nine Ways server). As well as the following directory folders, this base directory contains the Altium main project file.

● Documentation <directory>

The documentation is all stored neatly and together in this folder. This includes this Hardware architecture and all customer release documents and any PCB component specification PDFs.



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● Altium Library Store <directory>

The library store contains the main instantiated library containers for this NetFusion project. Unlike many companies, Nine Ways R&D uses separately instantiated folders per project. There is no common library for all Nine Ways PCBs reference by each and every project. Each PCB development has a new copy of the libraries for customization.

● NDT Library <directory>

This mainly small footprint components and mating connectors.

● NINEWAYS Library <directory>

Contains larger more common components, headers and ICs

● NetFusion Altium Revision <directory>

Each revision has its own separate folder. The directory contains the PCB file, schematic file(s), the Altium PCB project and a system IDE generated sub-folder shown below. Every new revision no matter how small the change, has a newly named folder with all of the previous revision copied in as a start point. Alterations are then made. Importantly, the library folders are outside of these revision folders so remain common to the whole PCB project revisions.

. ● Project Outputs <directory>

This folder mainly contains system generated Gerber and binary files for the PCB manufacturer. The exceptions are the manually created parts lists, PCB specification document and the ZIP package file. The Pick & Place file generated by the Altium system IDE also is contained in the folder. As this directory is situated in each revision folder, obviously this automatically maintains a new and separately generated PCB output per iteration.

.

. (Repeated directories for each revision of the PCB that may exist during development) Each repeated iteration directory would be named NetFusion Altium Rev[x] Issue.[n]

Figure 4 - Start point for NetFusion PCB development base directory



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3 Form Factor of the PCB

Figure 5 - PCB Form Factor Nano-ITX

The NetFusion PCB will use the Nano-ITX form factor. This is a very common standard for the micro-motherboards available in the world-wide commercial market for miniature PCs. It is targeted at smart digital entertainment devices such as PVRs, set-top boxes, media centers and Car PCs, and thin devices.

The dimensions are 170mm x 170mm to form a square. The holes will be 4 x corner @ 5mm hole, 2mm ring of copper surround with hole centre at 10mm diagonal from corner of PCB on all holes.

Figure 6 - Graphical Comparison of Nano-ITX

http://en.wikipedia.org/wiki/Set-top_box

http://en.wikipedia.org/wiki/Home_theater_PC



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4 Top Level Architecture

4.1 Overview

The main NetFusion NETFUSION-M2S-SOM-F484-SFP motherboard PCB has its own DC input power supply, Ethernet fiber connections for 1.25Gb/s SERDES, a variety of peripheral connections for real-world applications, SOM core, USB connectivity, audio compatibility, an option for a comprehensive LCD display together with buttons.

4.2 Block Diagram of Functionality

Figure 7 - Block Diagram Architecture of the NetFusion-M2S-SOM-F484-SFP Main Board



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5 Component Description Details

5.1 SOM connectors

The NetFusion PCB provides two Hirose DF40 series connectors (J12, J13) for the connection to the SOM. The connectors are 80-pin, 0.4mm pitch receptacles, providing 4mm stacking height.

5.2 USB UART Interface

The NetFusion PCB provides a USB UART interface on the type B mini USB connector (JP2). The interface is provided using an FTDI FT232RL USB-UART bridge (U33). The FT232RL UART TX and RX pins are connected to the SOM serial console UART port.

5.3 Ethernet Interface

The NetFusion NETFUSION-M2S-SOM-F484-SFP PCB provides 2 x SERDES Fiber interface using the (J35, J37) SFP cage connectors. These channels route from the SERDES of the Marvell QuadPHY (U3). This device supports SERDES for 1.25Gb/s speed of operation. Additionally a dual RJ-45 Ethernet port allows SDI-X 10/100/1000 Copper from the Marvell QuadPHY (U3) as the PHY can run different channels in different modes of media type.

The 2nd RJ45 port as part of the integrated HALO HALO HFJ12-1G16ER connector block is wired directly through the SOM connectors to the SOM on-board PHY and dedicated MAC to the MSS for the ARM processor. This can be re-routed inside the fabric of the FPGA by the system designer to IP hardware Ethernet switch (either by MorethanIP or 3

rd party) but will only operate at 10/100 because of the SOM

PHY being limited to only Fast Ethernet 10/100.

5.4 USB OTG Interface

The NetFusion PCB provides a USB OTG interface on the type B mini USB connector (JP1). The interface is implemented using the USB ULPI interface of the SmartFusion2 FPGA. The interface is buffered using an SMSC USB3300-EZK ULPI USB PHY device (U26).

To improve the quality of the USB signals for customers and project designers/integrators it is recommended to add voltage suppressors such as the Littelfuse PGB1010603M device to the USB data lines (USB_OTG_N, USB_OTG_P, USB_N and USB_P).

Note: The SmartFusion2 SOM has to be the M2S-SOM Rev 1A-F484 for correct operational functionality. There is no board modification that allows for the M2S-SOM Rev 1A/2A/3A-F896 version that preceded the newer version.

CAUTION: Electrical connectivity conflicting with the M2S-SOM F896 Rev 1/2/3A could cause component damage.

5.5 FlashPro JTAG Interface

The NetFusion PCB provides a JTAG interface on the (J28) connector for use with the MicroSemi FlashPro device for programming of the SOM SoC FPGA. The connector is a standard 10-pin header 2x5 that is compatible with FlashPro3/4 devices.

5.6 ARM JTAG Interface

The NetFusion PCB provides an ARM JTAG interface on the (J26) connector for debugging of the FPGA MSS. The connector is a standard 20-pin header 2x10 supported by standard Cortex-M series programmers/emulators.



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When using the Cortex-M series programmer for debugging of the MCU/MSS the settings of the (LK3) header should be closed. For further details on this jumper setting, please refer to the Jumpers sub-section later in this document.

5.7 Power Supply

The NetFusion PCB receives a wide-range voltage capability from 9-18V DC. This is provided from either a VERT 2-way header (Q2) (for industrial deployment) or in parallel with a standard power-pin input (J30, J32). The wide range input is converted via a DC-DC module (PW1) to a steady 5V and 3.3V rail.

The 5V is then available via a connector (J33) for customer’s attached hardware that may wish to use a small amount of 5V DC power from the NetFusion PCB. The 5V rail is distributed across the NetFusion PCB to all components that require 5V voltage levels. The 3.3V rails are then derived from the 5V using TPS73733DCQ LDO regulators (U30, U31, U32, U35, U36). There is in-fact two of such regulators to ease the load across the PCB and into the SOM.

The NetFusion PCB provides a RED power input LED (LED2) (from 5V) and also a RED power good indicator (LED3) from the 3.3V/2.5V outputs of the LDO regulators.

5.8 Reset Button

The NetFusion PCB provides the (S1) edge PCB reset button used to trigger a reset of the SOM. This in turn should propagate reset signals to the PHYs and other circuitry dependant on a reset_n.

5.9 Generic Option-Jumpers and Configuration Dials

The NetFusion PCB provides a 6-Way Option jumper header (J9) for general customer application configuration and basic settings. Additional to this, there is a BCD 0-9 selector switch that offers a form of basic configuration for the high-level operation of the PCB. These are wired to the GPIO of the SOM headers (J12, J13) for FPGA routing to the ARM sub-system for software operation and control.

5.10 User Buttons & LCD Display

The NetFusion PCB provides a standard header for a comprehensive LCD display (U17, J17). The signals lines are routed into the SOM headers (J12, J13) for control from the ARM CPU via GPIO. The LCD header also has 3.3V power rail and GND supplied. The intention of the LCD display is to be controlled simplistically by three buttons on the PCB for configuration and control of customer/client functionality. This is performed using (S4, S5 and S6) by a user in a default manner.

If the LCD display (purchased and supplied separately to this NetFusion PCB), is mounted and in operation, then the user will be able to implement source code in the ARM processor as an application that can control the LCD display. This all assists the user ability of the NetFusion product to facilitate for end-user operation in the field where ever deployed industrially.

The brightness of the backlight in the LCD module is controlled by a POT (VR2) with POT (VR1) adjusting the contrast.



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5.11 Audio Compatibility

The NetFusion PCB provides an Audio Line In connection (J18) and Audio Line Out phone jack connection (J14). These are associated with IC devices (U28) for Line In – which is an ADC AD7911ARMZ dual channel input. The stereo input utilizes the dual channel input on the AD7911ARMZ with Left and Right audio into channels 1 and 2. The audio output is controlled by the AD5621 DAC (U8, U11). Both the ADC and DAC IC devices are SPI bus accessible. This is connected back to the SOM connectors with the GPIO.

Volume and amplitude control can be managed from the software digitally as the operational amplifier and signal conditioning circuitry for the Audio output are fixed and tuned to provide a full-swing voltage not to exceed the clipping threshold when the digital values are at maximum. Therefore, as no variable gain-amplification exists, the software should use digital signal processing algorithms for louder or quieter audio in either direction. For audio output in stereo, two AD5621 SPI DAC ICs will allow SPI addressing from the FPGA/ASIC fabric to an audio Line Out amplifier and signal conditioning circuitry. Again, the volume is set for maximum non-clipping line-out power levels of 600/1KOhm. The software can digitally multiply the signal to allow for changing audible levels.

5.12 Voltage Monitor & Temperature Sensor

The NetFusion PCB has an on-board PCB temperature sensor MAX6577 SOT23-6 SM device (U6). It uses the 3.3V power rail and provides a square wave 50-50 duty cycle 3.3V output frequency. The device has been hard-wired to produce an output frequency of 1Hz per Kelvin degree. So Water melting/freezing is 273 Hz (273 degrees absolute) and boiling point is 373Hz (373 degrees absolute).

The PCB also has an AD7998 ADC SM IC (U15). Like the analogue contact inputs ADC, this is the same device except that it is used to read the analogue proportional levels of the PCBs own voltage power rails. Vin, 5, 2.5, 3.3, 1.2 and 0V are all connected. The reference voltage is 5.1V across Zener diode (D12). Vin is divided down to 25% so that up to 20.4V in the terminals power inputs can be calculated in the micro-processor. The processor interface is an I2C bus that is wired back to the GPIO of the SOM headers (J12, J13).

5.13 Real-Time Clock (RTC)

The NetFusion PCB has a resident real-time IC device (RTC) component (U34). This is backed-up voltage-wise by battery (BATT1) which is 3V. The battery does not have to be populated unless a customer wishes to use the RTC capability which keeps time even during a power-down.

The RTC device is a DS1307 SM IC that has an I2C bus interface. These are wired back to the SOM headers (J12, J13) so that GPIO can be used to allow the software to communicate with the RTC device IC.



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5.14 RS232 Peripheral

The RS232 peripheral on the NetFusion PCB is connected to the SOM header UART signals. The MSS in the SmartFusion2 device has dedicated UART modules but they are used for the USB feature. However, the user can choose to internally wire in the FPGA fabric, the UART signals from the NetFusion PCB to IP hardware UARTS instead which arises in more flexibility.

The RS232 uses connectors (J15, J16) and is wired through the RS232 level shifters (U9, U12) which are MAX232ESE-3.3V SM ICs.

The two connectors are a 9-way D-type for general office debugging and connections on a desk, and the VERT 8-way header is more for the Industrial deployment and is wired in by screw-driver by the installation engineer. This eliminates RX/TX cross-over conflict issues as the RX and TX are clearly labeled on the PCB legend. Extra RS232 signals such as RTS, CTS, DTR, DSR can be driven from GPIO using options jumpers (JP3, JP4, JP5, JP6, JP7).

5.15 RS485 Peripheral

The RS285 peripheral on the NetFusion PCB is connected to the SOM header UART signals. The MSS in the SmartFusion2 device has dedicated UART modules but they are used for the USB feature. However, the user can choose to internally wire in the FPGA fabric, the UART signals from the NetFusion PCB to IP hardware UARTS instead which arises in more flexibility.

The RS485 uses connector (J19) and is wired through the RS485 level shifter (U23, U27, U19, U24) which is a DS75176 RS485 Level Shifter DIP IC.

The connector is a 4-way header for the Industrial deployment and is wired in by screw-driver by the installation engineer. It allows for a 4-wire RS485 system operating at full-duplex rather than the inferior two-wire system at half-duplex.

5.16 Voltage Free Relay Peripheral

The NetFusion PCB has two voltage free relays for general purpose output signaling. This is often used by project designers to communicate basic but important states of equipment in a retro-styled manner. The GPIO from the SOM headers are wired to firstly, a solid-state IC stage (U2, U7) which is an AQW610s device. However, these wirings from the SOM headers are shared with the GPIO lines. Use option jumpers (JP8, JP9) to select the usage of these relays.

These devices are good for being able to have the polarity changed by option header jumpers. The output from this device then feeds to a relay coil 1D device (RL1, RL2) that connects to the Relay connectors (J10, J11). This provides protection for the ARM and the SmartFusion2 device with the SM IC solid-state device then staging to a relay coil double-pole output.

These can therefore, by being staged in this manner, switch high voltage, high current equipment directly. The earth connection on the NetFusion PCB provides protection in addition to the solid-state device.

Jumpers (LK1, LK2) provide the polarity settings (detailed later in the sub-sections).



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5.17 Analogue Contact Inputs Peripheral

The NetFusion PCB provides 8 contact input channels from connectors (J1-J8). These channels are treated as an analogue signal for two reasons; (a) so that they can be used to sample analogue levels at a relatively slow sampling rate if required and (b) some digital readings use “monitored contacts” with resister biasing to detect sabotage – and analogue to digital conversion can detect the change.

The sampling is performed by (U1) which is an AD7998 SM IC that allows for 8-channel on a single device. The communication is controlled by an I2C bus which is wired back to the SOM headers for GPIO access from the ARM/MSS.

These inputs from the connectors on the NetFusion PCB also have passive-ferrite and transzorb protection.

5.18 GPIO Peripheral

The NetFusion PCB provides for 14 of the GPIO lines from the SOM. This implies that SPI, I2C, TTL can all be applied to these signal lines as they are all fed and driven/sensed by the GPIO in the SOM.

The connectors on the PCB (J27, J31) also provide the 3.3V rail and GND as these levels are referenced to the signals.

Note: GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 and GPIO7 are available through option jumpers (JP3, JP4, JP5, JP6, JP7, JP8, and JP9). They share with the relays and the RS232 extra signals.

CAUTION: These lines are NOT protected. They are direct to the SOM FPGA and must only be used with-in an electrically safe environment and controlled enclosure especially when industrially deployed.

5.19 Signal Los Switch

The Signal los switch allows the user to switch the signal los from digital high being good to digital low being good.

The connectors on the PCB (J56, J57) are set to ‘Normal’ being digital high good, the signals are inputted as a single ended signal and converted to a diff pair, this is done through the CD74ACT (U39).

5.20 Earth Protection

An EARTH spade (J29) is provided on the NetFusion PCB. This is kept away from the main circuitry and planes. It is used to allow excessive voltages on the relays, input contacts and RS232/485 lines to route safely back to a local ground situated by the deployment of the PCB and its housing.

Note: The outer shielding of the HALO connector however is not connected to the Earth as the design of the differential pairs is transformer isolated.



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6 Typical SOM Architecture (Current SmartFusion2 M2S-SOM-F484)

Figure 8 – SmartFusion2 M2S-SOM-F484 Functional Block Diagram

6.1 Hardware Platform Overview The following are the key hardware features of the SmartFusion2 SOM:

Compact (34 mm x 59 mm) mezzanine module;

External interface using two 80-pin 0.4 mm-pitch connectors;

Compliant with the Restriction of Hazardous Substances (RoHS) directive;

SmartFusion2 SoC FPGA in FG896 package capable of running the system clock at 166 MHz;

JTAG interface to SmartFusion2;

Powered from single +3.3 V power supply;

Low-power mode with fast wake-up times;

On-module clocks;

64 MBytes LPDDR;

16 MBytes SPI Flash;

Serial console interface at UART CMOS levels;

802.3 Ethernet interface;

Watchdog Timer (WDT);

Key uncommitted interfaces of the SmartFusion2 device available on the interface connectors.



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6.2 Microcontroller & SmartFusion2 FPGA The architecture of the SmartFusion2 SOM is built around the Microsemi SmartFusion2 SoC FPGA that combines a 32-bit ARM Cortex-M3 processor core with a wide range of the integrated peripheral controllers as well as the FPGA fabric. The SmartFusion2 device is implemented using the FG896 package.

6.3 SmartFusion2 On-Chip Configuration and FPGA Design

Users of the SmartFusion2 SOM are provided with a SmartFusion2 on-chip configuration and FPGA design suitable for the intended operation of the SmartFusion2 SOM. The SmartFusion2 SOM on-chip configuration and FPGA design can be viewed as an extension of the SmartFusion2 SOM hardware design. It contains a logical definition of the internal SmartFusion2 architecture, which consists of the Microcontroller Subsystem (MSS) configuration, as well as FPGA logic developed by Microsemi and Emcraft Systems. It also describes an electrical interface between the SmartFusion2 device and external components, such as the SmartFusion2 device pin configuration and assignment. On a baseboard, the SmartFusion2 SOM is installed into two 80-pin Hirose DF40 series 0.4 mm-pitch board-to-board connectors. The exact part number of the connectors is Hirose DF40C-80DP-0.4V(51). The recommended mating connectors for a baseboard are the Hirose DF40HC(4.0)-80DS-0.4V connector, which provides 4 mm stacking height for the SmartFusion2 SOM. The maximum height of the SOM above a baseboard for 4 mm stacking height is 7.6 mm.

For extensive details please refer to the SmartFusion2 SOM Hardware Architecture Specification - Microsemi document.

http://www.google.co.uk/url?sa=t&rct=j&q=smartfusion2%20som%20hardware%20architecture%20document&source=web&cd=1&ved=0CDsQFjAA&url=http%3A%2F%2Fwww.microsemi.com%2Fdocument-portal%2Fdoc_download%2F131610-smartfusion2-som-hardware-architecture-specification&ei=_dSMUv_hGqWR7Abt1YGQBw&usg=AFQjCNHCHcdqlBvKhJmMBhUcQgwSl5SEQA&bvm=bv.56643336,d.d2k



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7 Connectors

7.1 Connector Summary Table 1: Summary of PCB Connectors

Connector Description

JP2 Mini USB type B connector (USB UART interface)

U5 RJ45 Dual Ethernet interface (HALO HFJ12-1G16ER)

J26 ARM JTAG connector

J35,J37 SFP Mating connector interface

J12, J13 SOM header interface connectors

J28 Microsemi FlashPro JTAG connector

JP1 Mini USB type B connector (USB OTG interface)

Q2, J30, J32, J33 Input D.C Power Supply & External +12V Output

J9 Generic User option jumper header

J17 LCD connector mating interface

J1 – J8 Analogue input contacts connectors

J10, J11 Voltage free output relays connector

J27, J31 General purpose I/O (GPIO) user interface

J14, J18 Standard phono-jack for Audio Line IN/OUT

J29 Earth spade attachment for transient protection

JP3, JP4, JP5, JP6, JP7, JP8, JP9

GPIO sharing option jumpers with relays and RS232 extra signals



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7.2 Mini USB Type B Connectors

The (JP1) and the (JP2) USB connectors have a standard mini-B receptacle pin-out.

Table 2: USB Receptacles

Pin Signal Type Description

1 USB_VCC POWER VCC from USB cable to the USB IC PHY

2 USB_DATA+ I/O USB Data differential positive

3 USB_DATA- I/O USB Data differential negative

4 USB_ID I/O USB presence detection

5 USB_GND POWER GND from USB cable to the USB IC PHY

7.3 RJ45 Ethernet Dual Connector Block (HALO HFJ12-1G16ER)

Table 3: RJ45 (HALO HFJ12-1G16ER) Dual Connector (U5)

Pin Signal Description

P1_1 VCCETH PHY VCC power voltage level

P1_2 ETH1_TDO_P RJ45 Port 1 positive differential

P1_3 ETH1_TDO_N RJ45 Port 1 negative differential

P1_4 ETH1_TD1_P RJ45 Port 1 positive differential

P1_5 ETH1_TD1_N RJ45 Port 1 negative differential





P1_10 GND PHY ground

P1_11 ETH1_LED1A RJ45 Port 1 yellow LED anode

P1_12 ETH1_LED1K RJ45 Port 1 yellow LED cathode

P1_13 ETH1_LED2A RJ45 Port 1 green LED anode

P1_14 ETH1_LED2K RJ45 Port 1 green LED cathode

P2_1 VCCETH PHY VCC power voltage level

P2_2 ETH2_TDO_P RJ45 Port 2 positive differential



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P2_3 ETH2_TDO_N RJ45 Port 2 negative differential







P2_10 GND PHY ground

P2_11 ETH2_LED1A RJ45 Port 2 yellow LED anode

P2_12 ETH2_LED1K RJ45 Port 2 yellow LED cathode

P2_13 ETH2_LED2A RJ45 Port 2 green LED anode

P2_14 ETH2_LED2K RJ45 Port 2 green LED cathode

7.1 SFP Fiber Mating Connector Block

Table 4: SFP Mating connector interface (J35, J37)

Pin Signal Description

1 GND Chassis GROUND

2 TXFAULT Transmit SERDES Fault Detection

3 TXDIS Enable/Disable for the TX

4 MOD2 I2C Bus for IC communication



7 RATE Speed/Rate selection for the device

8 LOS Fiber signal analog no present indicator




12 RD- RX differential negative

13 RD+ RX differential positive




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15 TXVCC TX VCC

16 RXVCC RX VCC


18 TD+ TX differential positive

19 TD- TX differential negative


7.2 SOM Interface Connectors

Table 5: SOM Header 1 (J12)

Pin Signal Type NetFusion Usage

Power signals

2, 3, 5,

8, 9, 11, 14, 57, 75, 76

GND POWER SOM Ground

77, 79 VCC3 POWER 3.3V

13 nRESET_IN INPUT Reset IN

15 nRESET_OUT OUTPUT Reset OUT to PHY ICs

JTAG signals

20 JTAG_TCK INPUT ARM & Flash Pro JTAG

22 JTAGSEL INPUT ARM & Flash Pro JTAG

24 JTAG_TMS INPUT ARM & Flash Pro JTAG

36 JTAG_nTRST INPUT ARM & Flash Pro JTAG

38 JTAG_TDO OUTPUT ARM & Flash Pro JTAG

47 JTAG_TDI INPUT ARM & Flash Pro JTAG

62 VJTAG_VPP POWER ARM & Flash Pro JTAG

Serial UART-TTL signals

28 UART_1_TXD OUTPUT RS232 Peripheral Interface

29 UART_0_TXD OUTPUT USB UART Interface

30 UART_0_RXD INPUT USB UART Interface

31 UART_1_RXD INPUT RS232 Peripheral Interface

Default Ethernet MSS MAC signals

1 LED_ACT OUTPUT 2nd

10/100 SOM PHY Copper Ethernet



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4 TD_P OUTPUT 2nd


6 TD_N OUTPUT 2nd


7 LED_SPD OUTPUT 2nd


10 RD_P INPUT 2nd


12 RD_N INPUT 2nd


GPIO signals

16 MSIO102NB8 I/O Temperature Sensor Output

17 MSIOD121PB7 I/O GMII3RD0 (3rd

GMII Bus)

18 MSIOD121NB7 I/O GMII3RD1 (3rd

GMII Bus)


GMII Bus)


GMII Bus)


GMII Bus)


GMII Bus)


GMII Bus)


GMII Bus)

37 MSIOD127NB7 I/O GMII3TD0 (3rd

GMII Bus)

39 MSIOD127PB7 I/O GMII3TD1 (3rd

GMII Bus)


GMII Bus)


GMII Bus)


GMII Bus)


GMII Bus)


GMII Bus)


GMII Bus)

46 MSIOD123NB7 I/O GMII3TEN (3rd

GMII Bus)

48 MSIOD125PB7 I/O GMII3TER (3rd

GMII Bus)

49 MSIOD118PB7 I/O GMII3TCK (3rd

GMII Bus)

50 MSIOD125NB7 I/O GMII3GTCK (3rd

GMII Bus)

51 MSIOD118NB7 I/O GMII3RCK (3rd

GMII Bus)

52 MSIOD124PB7 I/O GMII3REN (3rd

GMII Bus)

53 MSIOD132PB7 I/O GMII3RER (3rd

GMII Bus)

54 MSIOD124NB7 I/O Input Analogue Contacts ADC I2C Bus

55 MSIOD132NB7 I/O Input Analogue Contacts ADC I2C Bus

56 MSIOD131PB7 I/O GMII3IRQ (3rd

GMII Bus)



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58 MSIOD131NB7 I/O SDA_LCD (LCD I2C Bus)

60 MSIOD133PB7 I/O SCL_LCD (LCD I2C Bus)

I2C Bus signals

25 I2C_1_SCL I/O SCL_GPIO (GPIO Extender IC I2C Bus)

26 I2C_1_SDA I/O SDA_GPIO (GPIO Extender IC I2C Bus)

27 I2C_0_SDA I/O SDA_RTC (Real-Time Clock IC I2C Bus)

33 I2C_0_SCL I/O CLK_RTC (Real-Time Clock IC I2C Bus)

SPI Bus signals

59 SPI_1_SDO OUTPUT Stereo Audio Line-IN SPI Bus

61 SPI_1_SDI INPUT Stereo Audio Line-IN SPI Bus

64 SPI1_nSS1 I/O LCD_RS (LCD Control)

66 SPI1_nSS2 I/O GMII1IRQ (1st GMII Bus)

68 SPI1_nSS3 I/O LCD_EN (LCD Control)

67 SPI_1_CLK OUTPUT LINEIN_SPICLK (Stereo Audio Line-IN SPI Bus)

69 SPI1_nSS0 OUTPUT LINEIN_SPInCS (Stereo Audio Line-IN SPI Bus)

70 FPGA_RPRG OUTPUT NOT CONNECTED

73 SC_SPI_nSS OUTPUT

Unconnected Pins

63, 65, 71, 73, 72, 74,

78, 80

N/A N/A N/A



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Table 6: SOM Header 2 (J13)

Pin Signal Type NetFusion Usage

Power signals

24, 28, 52 GND POWER SOM Ground

GPIO signals

1 MSIO103NB8 I/O GMII1RD0 (1st GMII Bus)

2 MSIO101PB8 I/O GMII1RD1 (1st GMII Bus)







9 MSIO99PB8 I/O GMII1TD0 (1st GMII Bus)

10 DDRIO148NB5 I/O GMII1TD1 (1st GMII Bus)

11 MSIO98NB8 I/O GMII1TD2 (1st GMII Bus)

12 RIO148PB5 I/O GMII1TD3 (1st GMII Bus)





17 MSIO107PB8 I/O GMII1REN (1st GMII Bus)

18 DDRIO156NB5 I/O GMII1RER (1st GMII Bus)

19 MSIO108NB8 I/O GMII1TEN (1st GMII Bus)

20 DDRIO156PB5 I/O GMII1TER (1st GMII Bus)

21 MSIO117NB8 I/O GMII1TCK (1st GMII Bus)

22 DDRIO166NB5 I/O GMII1GTCK (1st GMII Bus)

23 MSIO117PB8 I/O GMII1RCK (1st GMII Bus)

25 MSIO108PB8 I/O GMII2RD7 (2nd GMII Bus)

26 ULPI_CLK I/O USB OTG

27 MSIO22NB3 I/O GMII2RD6 (2nd GMII Bus)



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30 ULPI_DATA7 I/O USB OTG











41 MSIO23PB3 I/O GMII2TD0 (2nd GMII Bus)


43 MSIO44NB1 I/O GMII2TD1 (2nd GMII Bus)



46 ULPI_DIR I/O USB OTG


48 ULPI_NXT I/O USB OTG


50 ULPI_STP I/O USB OTG



54 MSIOD120PB7 I/O PHY 3 MDIO Bus


56 MSIOD120NB7 I/O PHY 3 MDC Bus

57 MSIO43PB1 I/O GMII2REN (2nd GMII Bus)

58 MSIOD119NB7 I/O ADC Conversion Control for Voltage Supervisor

59 MSIO19NB3 I/O GMII2RER (2nd GMII Bus)

60 MSIOD119PB7 I/O ADC Conversion Control for Analogue Contact Inputs

61 MSIO19PB3 I/O GMII2RCK (2nd GMII Bus)

62 DDRIO164PB5 I/O GMII2GTCK (2nd GMII Bus)



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63 MSIO45PB1 I/O GMII2TEN (2nd GMII Bus)

64 DDRIO164NB5 I/O GMII2TER (2nd GMII Bus)

65 MSIO45NB1 I/O GMII2TCK (2nd GMII Bus)

66 DDRIO172NB5 I/O Stereo Line OUT SPI Bus

67 MSIO47NB1 I/O Stereo Line OUT SPI Bus

68 DDRIO172PB5 I/O Stereo Line OUT SPI Bus

69 DDRIO181PB5 I/O Stereo Line OUT SPI Bus



72 DDRIO182PB5 I/O PHY 2 MDIO Bus

73 DDRIO167PB5 I/O PHY 2 MDC Bus

74 DDRIO182PB5 I/O PHY 1 MDIO Bus

75 DDRIO184PB5 I/O PHY 1 MDC Bus

76 DDRIO174PB5 I/O Analogue Monitored Contacts I2C Bus

77 DDRIO184NB5 I/O Analogue Monitored Contacts I2C Bus

78 DDRIIO174NB5 I/O GMII2IRQ (2nd GMII Bus)

79 MSIO0PB3 I/O RS485 Peripheral Interface

80 DDRIO177PB5 I/O RS485 Peripheral Interface

Please Note: For extensive details of the SOM pin-out usage, please refer to the SmartFusion2 SOM Hardware Architecture Specification - Microsemi document.





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7.3 JTAG Connectors

Table 7: FlashPro JTAG Connector (J28)


1 JTAG_TCK INPUT JTAG clock signal to the SOM

2 GND POWER Target ground

3 JTAG_TDO OUTPUT JTAG data output from the SOM

4 N/C JTAG mode set target MCU

5 JTAG_TMS INPUT JTAG mode select

6 VJTAG_VPP POWER For IC on PCB. Not for SOM

7 VJTAG_VPP POWER For IC on PCB. Not for SOM

8 JTAG_nTRST INPUT JTAG controller reset

9 JTAG_TDI INPUT JTAG data input to the SOM


Table 8: ARM JTAG Connector (J26)


1 VJTAG_VPP POWER Target MCU reference voltage

2 N/C

3 JTAG_nTRST INPUT JTAG controller reset

4, 6, 8, 10, 12, 14, 16, 18, 20

GND POWER Target ground

5 JTAG_TDI INPUT JTAG data input to the SOM

7 JTAG_TMS INPUT JTAG mode select

9 JTAG_TCK INPUT JTAG clock signal to the SOM

11 GND TIE LOW Not connected to the SOM

13 JTAG_TDO OUTPUT JTAG data output from the SOM

15 SOM_nRESET I/O Target MCU reset signal





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7.4 Power Supply

Table 9: Removable Power Connectors (J30, J32)


1 +VIN POWER Input main DC-wide range

2 GND POWER Power supply ground

3 +VIN POWER Input main DC-wide range

(Duplicated for chain wiring)


Table 10: Molded Power Receptacle (Q2)


A GND POWER Power supply ground

B +VIN POWER Input main DC-wide range

Table 11: External Power Connector (J33)


1 +5VEXT POWER Output Voltage for Slave Hardware




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7.5 Option Jumper Headers

Table 12: JTAG Mode Selection (LK3)

Name Settings Description

JTAG Mode Selection

1-2 Closed The SOM JTAG controller is in the Cortex-M3 debug mode. The JTAGSEL pin of the

SOM is LOW

1-2 Open The SOM JTAG controller is in the FPGA programming mode. The JTAGSEL pin of

the SOM is HIGH

Table 13: Generic Configuration Header (J9)


Generic Configuration Header

1-2 Closed User Customer Option Strap 1

1-2 Open User Customer Option Strap 1











Table 14: GPIO Sharing RS232 (JP3, JP4, JP5, JP6, JP7)


RS232 / GPIO Sharing

1-2 Closed RS232 signal used and GPIO line not used

2-3 Closed RS232 signal not used and GPIO line active

1-2-3 Open No Operation for either RS232 or GPIO



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Table 15: GPIO Sharing Relays (JP8, JP9)


Relays / GPIO Sharing

1-2 Closed Relay signal used and GPIO line not used

2-3 Closed Relay signal not used and GPIO line active

1-2-3 Open No Operation for either Relay or GPIO

Important Note: the first 7 GPIO lines do not go to the GPIO header (J27, J31). The lines are fed through 3-way option jumpers to select differing functionality. The tables above illustrate the split functionality.

Table 16: Relay 1 Polarity (LK1)


Voltage Free Relay 1 Polarity

1-2 Closed J10 Normally Closed when Relay1 de-asserted

2-3 Closed J10 Normally Open when Relay1 de-asserted

1-2-3 Open No Relay Connector (J10) Operation

Table 17: Relay 2 Polarity (LK2)


Voltage Free Relay 2 Polarity

1-2 Closed J11 Normally Closed when Relay2 de-asserted

2-3 Closed J11 Normally Open when Relay2 de-asserted

1-2-3 Open No Relay Connector (J11) Operation



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7.6 LCD Connector

Table 18: LCD Mating Connector (J17)


1 GND POWER Power Supply Ground

2 +5V POWER 5V Power Rail

3 CONTRAST INPUT Contrast Setting from POT (VR1)

4 LCD_RS INPUT LCD Control Line

5 LCD_RW INPUT LCD Control Line

6 LCD_EN INPUT LCD Control Line

7 LCD_D0 INPUT LCD Data Bus








15 BACKLIGHT POWER Backlight Current Sink

16 BACKLIGHT POWER Backlight Current Source



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7.7 Analogue Contact Input Connector

Table 19: Contact Input Connector (J1 – J8)


1 ACI_1 INPUT Analogue Input 1 reference to GND
















7.8 Relay Output Connector

Table 20: Voltage Free Relay 1 Connector (J10)


1 RLY_1_A OUTPUT Floating isolated relay signal

2 RLY_1_B OUTPUT Floating isolated relay signal



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Table 21: Voltage Free Relay 2 Connector (J11)


1 RLY_2_A OUTPUT Floating isolated relay signal

2 RLY_2_B OUTPUT Floating isolated relay signal

7.9 Serial Connectors

Table 22: COM1 Serial RS232 9-Way D-Type Connector (J15)

Pin (on PCB) Signal Type Description

1 DCD INPUT Data Carrier Detect

2 RxD INPUT Receive Data

3 TxD OUTPUT Transmit Data

4 DTR OUTPUT Data Terminal Ready

5 SG POWER Signal/Chassis Ground

6 DSR INPUT Data Set Ready

7 RTS OUTPUT Request To Send

8 CTS INPUT Clear To Send

9 RI INPUT Ring Indicator

Table 23: COM1 Serial RS232 VERT Connector (J16)


1 COM1_232TX OUTPUT COM1 RS232 TX

2 COM1_232RX INPUT COM1 RS232 RX

3 COM1_232RTS OUTPUT COM1 RS232 RTS

4 COM1_232CTS INPUT COM1 RS232 CTS

5 COM1_232DTR OUTPUT COM1 RS232 DTR

6 COM1_232DSR INPUT COM1 RS232 DSR

7 GND POWER Signal ground

8 GND POWER Signal ground



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Table 24: COM2 Serial RS485 4-Way Connector (J19)


1 COM2_485TX+ I/O COM2 TX+

2 COM2_485TX- I/O COM2 TX-

3 GND POWER Chassis Ground

4 COM2_485RX+ I/O COM2 RX+

5 COM2_485RX- I/O COM2 RX-

6 GND POWER Chassis Ground

7.10 GPIO Connector

Table 25: Generic General Purpose I/O Connector (J27, J31)


1 VCC3 POWER GPIO power supply level

2 GPIO_USR1 I/O GPIO User I/O 1

















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7.11 Stereo Audio Phono-Jacks

Table 26: Stereo Audio Line OUT Connector Jack (J14)


1 Left AUDIO Left Audio Analogue Channel

2 GNDAA POWER Analogue Ground

3 Right AUDIO Right Audio Analogue Channel




Table 27: Stereo Audio Line IN Connector Jack (J18)


1 Left AUDIO Left Audio Analogue Channel


3 Right AUDIO Right Audio Analogue Channel






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7.12 Signal Los Switch

Table 28: Signal los conversion CD74ACT (U39)


1 FB1LOS INPUT FB1 SIG LOS INPUT

2 FB1LOS_P OUTPUT FB1 SIG LOS_P OUTPUT


4 FB1LOS_N OUTPUT FB1 SIG LOS_N OUTPUT

5 - N/C -

6 - N/C -

7 GND POWER Target Ground


9 FB2LOS_P OUTPUT FB2 SIG LOS_P OUTPUT


11 FB2LOS_N OUTPUT FB2 SIG LOS_N OUTPUT

12 - N/C -

13 - N/C -

14 +5V POWER 5V Power Rail

7.13 Earthing

Table 29: Local Clean Earth Connection (J29)


1 PEARTH EARTH Local EARTH reference



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8 Future PCB Considerations with Newer Versions

This board will be designed in-house by Nine Ways R&D. Typical features of a newer PCB could be;

More SERDES SFP connections if a larger n-Port Switch IP core is utilized inside the FPGA/ASIC of the SOM.

Additional GPIO and/or another unforeseen communication bus mechanism.

Protection & Isolation unit for signals incoming from/going to harsh electrical environments.

Any other unforeseen interface or functionality that can be driven and processed by new customer IP core instantiation and/or additional new application layer API.

Support for other types of M2S-SOM from SmartFusion2. Also, other vendors of FPGA or ASIC.



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9 Contact

Table 30: Contact Information

Nine Ways Research & Development Ltd

E-Mail : [email protected]

Internet : www.nineways.co.uk

UK

Unit G.15, iDCentre, Lathkill House, rtc Business Park

London Road, Derby. DE24 8UP

United Kingdom

Tel : +44 (0) 1332 258847

FAX : +44 (0) 1332 258823

MorethanIP GmbH facilitate Ethernet IP cores for this product which can be found at

www.morethanip.com

mailto:[email protected]

http://www.morethanip.com/



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10 Document History

Document Change Notices (DCO)

Version Description Created/Changed By Date

0.1 Draft Initial start to the

NetFusion PCB project

design and system

specification

Paul Bates: Nine

Ways R&D (UK) Ltd

17th July 2014

0.2 Draft Changes made to

designators and some

explanations.

James Brayford: Nine

Ways R&D (UK) Ltd

11th September 2014

0.3 Draft Inclusion of FB1 Los table

inclued

James Brayford: Nine

Ways R&D (UK) Ltd

12th September 2014

Copyright © Nine Ways Research & Development Ltd 2013. All Rights Reserved.

Table 31: Document History Entry Log

NetFusion-M2S-SOM-F484 SFP SERDES Main-Board PCB

Documents

Transcript of NetFusion-M2S-SOM-F484 SFP SERDES Main-Board PCB